JPH0653742A - Oscillation circuit - Google Patents

Abstract

PURPOSE:To obtain an oscillation circuit in which stable oscillation is obtained over a wide frequency range in the oscillator employing the oscillation circuit comprising odd number of inverters connected in cascade. CONSTITUTION:The oscillating circuit being a component of the oscillator together with externally mounted components such as a crystal oscillator and a feedback resistor is formed in cascade connection of an odd number of inverters 11-15. The oscillation circuit is also provided with selectors 31/32, 33/34, 35/36 selected by a control signal inputted to control signal input terminals 3-5 and the selectors select outputs of an odd number stages of inverters 11, 13, 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator circuit, and more particularly to an oscillator circuit made of semiconductor.

[0002]

2. Description of the Related Art In a conventional oscillator circuit of this type, as shown in FIG. 4, inverters are cascade-connected in an odd number of stages. In the figure (a), three inverters 11, 12, and 13 are connected, and in the figure (b), one inverter 11 is connected.
1 is an oscillator input terminal and 2 is an oscillator output terminal. For such an oscillator circuit, as shown in FIG.
An oscillator is configured by adding external parts. In the figure, a crystal oscillator 41, a feedback resistor 42, and capacitors 43 and 44 are connected as external parts to a semiconductor oscillator circuit 62 having the circuit of FIG. 4A or 4B mounted therein. .

This oscillator circuit has a problem that it is difficult to stably oscillate in a wide frequency range.
For example, when the delay times of the inverters 11 to 13 in FIG. 4 are equal to 10 ns, respectively, in the oscillation circuit of FIG. 4A, frequency 1 ÷ (10 ns × 3) ÷ 2≈1
It does not oscillate at frequencies above 6.7MHz. On the other hand, in the oscillation circuit of FIG. 4B, the frequency 1/10 ns /
Oscillation is possible up to 2 = 50 MHz.

[0004]

However, this oscillator circuit has a problem in that if an attempt is made to oscillate at a low frequency, high-order parasitic oscillation is likely to occur. For example, when a crystal oscillator with an oscillating frequency of 10 MHz is connected, overtone oscillation occurs, and the frequency is tripled to 30 M instead of 10 MHz.
It may oscillate at 50 Hz, which is 5 or 5 times. An object of the present invention is to provide an oscillation circuit that can obtain stable oscillation over a wide frequency range.

According to the present invention, an oscillation circuit that constitutes an oscillator together with external components such as a crystal oscillator and a feedback resistor is connected in cascade with an odd number of inverters and selectively outputs the outputs of the odd-numbered inverters. The configuration is such that selection means is provided.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an oscillator circuit according to an embodiment of the present invention. Five inverters 11 to 15 are connected in series between the oscillator input terminal 1 and the oscillator output terminal 2. Furthermore, P
The channel MOS transistors 32, 34, 36 and the N-channel MOS transistors 31, 33, 35 are respectively connected in pairs to form a selector circuit composed of three transfer gates, and the selector circuits are cascade-connected to the inverters 11-15. Connected between the output of the inverter 11, the output of the inverter 13, the output of the inverter 15 and the oscillator output terminal 2, and select these outputs to output the oscillator. It is configured to output to the output terminal 2. Each selector is controlled by a signal applied to the control signal input terminals 3-5.

That is, when the control signal input terminal 3 is fixed to the power supply voltage and the other control signal input terminals are grounded, the output of the first stage of the cascaded inverters is selected and the control signal input terminal 4 is selected. When the power supply voltage is fixed and the other control signal input terminals are grounded, the output of the third stage is selected, and when the control signal input terminal 5 is fixed to the power supply voltage and the other control signal input terminals are grounded. Selects the output of the fifth stage.

In this oscillator circuit, the inverter 1
If the delay times of 1 to 15 are equal to 10 ns, the oscillation frequency is 1 / (10 ns * 5) / 2 = 10.
When the frequency is lower than MHz, the output of the fifth-stage inverter 15 is selected by the selector 5, and the oscillation frequency is higher than 10 MHz,
When 1 ÷ (10 ns × 3) ÷ 2≈16.7 MHz or less, the output of the third-stage inverter 13 is selected by the selector 4, and when the oscillation frequency is 16.7 MHz or more, the selector 3
Therefore, the output of the first-stage inverter 11 may be selected. In this way, it is possible to change the number of cascaded inverters so that the inverter array of the oscillation circuit has an appropriate delay time according to the oscillation frequency. In the circuit of FIG. 1, the frequency is 1/10 ns / 2 = 50 MHz in principle.
It does not oscillate above.

FIG. 2 shows an example in which an oscillator is constructed by adding external parts. 61 is the oscillation circuit shown in FIG.
In addition to this crystal oscillator 41, feedback resistor 42, capacitor 4
3, 44 are connected. In addition, the control signal input terminal 3,
5, the control signal input terminal 4 is fixed to the power supply voltage, and the third stage inverter output is selected.

FIG. 3 shows a second embodiment of the present invention.
NAND gates 51 to 53 are used instead of the transfer gates of the circuit of FIG. 1 to configure a selector circuit.
Also in this embodiment, like the first embodiment, when the control signal input terminal 5 is fixed to the power supply voltage and the other control signal input terminals are grounded, the output of the fifth stage of the cascaded inverters is selected. When the control signal input terminal 4 is fixed to the power supply voltage and the other control signal input terminals are grounded, the output of the third stage is selected, the control signal input terminal 3 is fixed to the power supply voltage, and the other control signal is set. When the input terminal is grounded, the output of the first stage is selected.

[0011]

As described above, according to the present invention, the output of the odd-numbered stages of the odd number of cascade-connected inverters can be selected and output. Therefore, the oscillation circuit suitable for the oscillation frequency is selected. The internal delay time can be selected, and there is an effect that stable oscillation can be performed over a wide frequency range.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an oscillator circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an oscillator using the oscillator circuit of FIG.

FIG. 3 is a circuit diagram of an oscillator circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing two examples of conventional oscillation circuits.

5 is a circuit diagram of an oscillator using the oscillator circuit of FIG.

[Explanation of symbols]

 1 Oscillator Input Terminal 2 Oscillator Output Terminal 3-5 Control Signal Input Terminal 11-15 Inverter 31, 32, 33, 34, 35, 36 Selector 41 Crystal Oscillator 61, 62 Oscillation Circuit

Claims (1)

[Claims] 1. A selection means for connecting an odd number of inverters in cascade and selectively outputting outputs of odd-numbered inverters in an oscillation circuit that constitutes an oscillator together with external components such as a crystal oscillator and a feedback resistor. An oscillator circuit characterized by being provided.