JPH0653714A - Low noise amplifier input device - Google Patents

Abstract

PURPOSE:To reduce the occurrence of the dispersion in the performance by connecting a gate electrode of a FET for the low noise amplifier to an input probe provided on a dielectric substrate with an interval therefrom. CONSTITUTION:A FET 30 is fitted onto a dielectric base 40. An input probe 41 to which an antenna output is led is provided on the substrate 40 with an interval from the arranged location of the FET 30. Since a long gate electrode 3G of the FET 30 is used for an input lead, and the length of the gate electrode 3G and the distance thereof from the substrate 40 are formed in advance and the tip is soldered to the probe 41 so as to obtain an impedance minimizing a noise figure of the FET 30. Furthermore, when the electrode 3G is parted from the substrate 40, a long hole 42 is formed on the substrate opposite to the electrode 3G shown in figure B. Then a dielectric loss is eliminated and the characteristic impedance of the lead part is increased and the adjustment to obtain the optimum matching is facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low noise amplifier input device used in an input stage of an SHF converter in a satellite broadcasting or satellite communication receiving system.

[0002]

2. Description of the Related Art In satellite broadcasting receiving systems, the aperture of recent antennas tends to be smaller. The aperture of the antenna can be made small by introducing the antenna output S
This is because the noise reduction of the HF converter has advanced. SHF
In reducing the noise of the converter, not only the noise reduction of the active element (low noise amplifier) used but also the loss reduction of the input part of the converter is an important factor. The input structure of the low noise amplifier should be designed to be low loss and match the noise minimum impedance of the active device. Due to the above requirements, the input section structure shown in FIG. 5 is generally adopted for the low noise amplifier.

In the structure shown in FIG. 5, a signal from the coaxial-waveguide converter (input probe) 11 is transferred to a dielectric substrate 12 having a low loss.
The microstrip line 13 configured above leads to the gate terminal 2G of the first-stage field effect transistor (FET) 20.

As shown in FIG. 4, the microstrip line 13
When a signal is guided by, even if the dielectric substrate 112 used has a low loss, there is a dielectric loss in the input line portion, which deteriorates the noise temperature. Especially 4
In the converter for GHz, the active element (F
ET) noise minimum impedance is usually

| P | = 0.7 to 0.8, LΓ = 50 to 6
It is 0, and in order to match with this, it is necessary to draw around 0.15λ with a high impedance line (about 100Ω), and the effect of conductor loss as well as dielectric loss will occur. There's a problem.

[0006]

As described above, according to the conventional input device, a skill is required for the assembling work for matching the noise minimum impedance of the active element, and the influence of the dielectric loss appears. There is. Further, there is a problem that the soldering operation causes the destruction of the FET and the variation of the characteristics due to the influence of heat and static electricity.

Therefore, a first object of the present invention is to provide a low noise amplifier input device which is not affected by dielectric loss and which can be easily adjusted to obtain matching with the noise minimum impedance of an active element. is there. A second object of the present invention is to provide a low noise amplifier input device in which the safety of the FET is high and the performance variation is small.

A third object of the present invention is that there is no influence of dielectric loss, the adjustment is easy to obtain matching with the minimum noise impedance of the active element, the possibility of FET destruction is low, and the performance is low. An object is to provide a low noise amplifier input device with less variation.

[0009]

According to the present invention, a gate electrode of an FET arranged on a dielectric substrate is connected to an input probe with a space between the dielectric substrate and an adjustment allowance. It is what

[0010]

With the above structure, the input line of the gate electrode is separated from the dielectric substrate, the influence of the dielectric loss is reduced, and there is a sufficient length to obtain the matching with the minimum impedance of noise. It is possible to easily adjust the characteristic impedance of the transmission line to the optimum matching state by adjusting the capacitance and the like in accordance with the distance.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

1A and 1B are embodiments of the present invention. In FIG. 1A, 30 is a field effect transistor (FET), and the FET 30 is mounted on the dielectric substrate 40. An input probe 41 into which an antenna output is introduced is attached to the dielectric substrate 40 at a distance from the location of the FET 20.
The tip of the gate electrode 3G of the FET 30 is used as an input lead in its long state, and is preliminarily formed to a length such that the impedance that minimizes the noise figure of the FET and a distance from the substrate are formed, It is soldered to the input probe 41.

The embodiment shown in FIG. 1B is realized without forming the gate electrode 3G when the gate electrode 3G is moved away from the dielectric substrate 40.
This is an example in which an elongated hole 42 is formed in the substrate portion facing G. Also by this, it is possible to eliminate the loss of the dielectric and increase the characteristic impedance of the lead portion,
Adjustment work is easy to obtain the optimum matching state. In this embodiment, since there is the elongated hole 42, there is a margin in the lead portion, and it is easy to adjust the height (spacing) from the substrate. Also,
It is possible to further increase the characteristic impedance of the lead portion by opening the elongated hole 42 in the substrate and simultaneously sitting on the chassis.

FIG. 4 is a diagram for explaining a general matching condition of the SHF converter at 4 GHz. Now, Fig. 4
In order to match the impedance at the point B with the impedance Γopt having the minimum noise figure of the FET, instead of the characteristic impedance Z0 of the transmission line in (A), FIG.
It is sufficient to increase the characteristic impedance of the transmission line as shown in. In order to increase the characteristic impedance in this way, there are a method of narrowing the line width and a method of separating the transmission line from the dielectric and the ground plane (chassis plane).

In the case of the embodiment shown in FIGS. 1A and 1B, the transmission line is kept away from the dielectric and the ground plane (chassis plane),
This is an example of adopting a method of adjusting the capacity. In this case, the position of the FET 30 is determined so that the length of the gate electrode, that is, the lead corresponds to the length from point B to point C in FIG.

In the above embodiment, the long gate electrode 3G of the FET 30 is directly used as a lead. Therefore, the number of times the soldering work is performed near the body of the FET 30 is reduced. As a result, there is no problem that the FET is broken or the characteristics are varied due to thermal or electrostatic influences.

FIG. 1C shows another method for increasing the characteristic impedance of the transmission line, and the width of the gate electrode 3G of the FET 30 may be narrowed or shaped in advance. The present invention is not limited to the above embodiments.

FIG. 2A shows another embodiment of the present invention. This embodiment is an example in which the shape of the gate electrode 3G of the FET 30 is transformed into a substantially L shape, and a substantially L-shaped elongated hole 43 is formed in the dielectric substrate 40 corresponding to this portion. With such a shape, as shown in FIG. 2B, when the distance from the dielectric substrate 40 (capacitance with the substrate) is adjusted to perform matching adjustment, the gate electrode 3G
1 has some elastic force, there is a margin in the space around the electrode, and there is a margin in the length due to the L shape, the adjustment work performed by displacing the electrode is shown in FIG. It will be easier than the example.

In each of the embodiments described above, the number of times of soldering work near the body of the FET 30 is reduced, and the risk of destruction of the FET and variations in characteristics due to thermal and electrostatic influences is prevented. There is. However, if attention is paid to easily obtaining matching with the minimum noise impedance of the active element without being affected by the dielectric loss, the embodiment shown in FIG. 3 may be used.

The embodiment of FIG. 3 is different from the embodiment shown in FIG. 2 in that an FET 30 having a short gate electrode 3G is used. In this embodiment, the jumper wire 44 is used to connect the gate electrode 3G and the input probe 41. In the case of this embodiment, the long hole 44 is L-shaped,
Since the jumper wires 44 are arranged along this line, it is possible to reduce variations in the attachment of the jumper wires 44 and to improve the matching accuracy. Further, even if the champagne wire 44 is thermally expanded and contracted, the expansion and contraction is absorbed due to the L-shape, which prevents stress from being applied to the gate electrode 3G of the FET 30 and the accident where the soldered portion is detached. Furthermore, it is a structure in which it is easy to perform fine adjustment of input matching by pushing down or pushing up the deflection of the jumper wire 44 (FIG. 3).
(See (B)).

[0021]

As described above, according to the present invention,
There is no influence of dielectric loss, and matching with the minimum noise impedance of the active element can be easily obtained. Further, since the electric field concentration is weakened, the conductor loss is also reduced. Further, if the gate electrode of the FET is used as it is as the input transmission line, the safety of the FET is high and it is possible to reduce the occurrence of variations in performance.

[Brief description of drawings]

FIG. 1 is a structural explanatory view and an FET showing an embodiment of the present invention.
Explanatory drawing of.

FIG. 2 is a structural explanatory view showing still another embodiment of the present invention.

FIG. 3 is a structural explanatory view showing another embodiment of the present invention.

FIG. 4 is an explanatory diagram of characteristic impedance of a low noise amplifier input device.

FIG. 5 is an explanatory diagram of a conventional low noise amplifier input device.

[Explanation of symbols]

30 ... Field effect transistor (FET), 3G ... Gate electrode, 40 ... Dielectric substrate, 41 ... Input probe, 42 ...
Long hole.

Claims (6)

[Claims] 1. A transmission line in which an input probe is connected to a gate of an FET constituting a low noise amplifier, wherein the FET for the low noise amplifier is disposed on a dielectric substrate.
The gate electrode of the input is provided on the dielectric substrate with a gap from the dielectric substrate to prevent the influence of dielectric loss and with an adjustment margin to facilitate input matching adjustment. A low noise amplifier input device characterized by being connected to a probe. 2. The low noise amplifier input device according to claim 1, wherein the gate electrode of the FET is substantially directly connected to the input probe. 3. The gate electrode of the FET is deformed in advance so as to float from the dielectric substrate in order to have the space and the length margin. Low noise amplifier input device. 4. The gate electrode of the FET has the space and the length margin with the dielectric substrate,
The low noise amplifier input device according to claim 2, wherein the low noise amplifier input device is arranged along an elongated hole formed in the dielectric substrate. 5. The low noise amplifier input device according to claim 4, wherein the elongated hole is substantially L-shaped. 6. The dielectric substrate is provided with an elongated hole formed in a substantially L shape between the gate of the FET and the input probe, and a jumper wire is arranged along the elongated hole. The low noise amplifier input device according to claim 1, wherein the input probe and the gate are connected to each other.