JPH0653333A - Forming method for contact hole in semiconductor device - Google Patents

Abstract

PURPOSE:To prevent overetching and simplify a step for forming a plurality of deep and shallow contact holes in a semiconductor device. CONSTITUTION:A photolithographically antireflective film 14 (a TiN film in this embodiment) is formed on an insulating film 5 for forming contact holes. Then, contact holes 6a, 7a, and 8a are formed by use of this antireflective film 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming contact holes in a semiconductor device.

[0002]

2. Description of the Related Art Two conventional methods for forming contact holes in a semiconductor device will be described below.

The first conventional method is shown in FIG. The section will be described below.

First, as shown in FIG. 3A, the semiconductor substrate 1
Then, a diffusion layer 2 is formed, and then, for example, a first polysilicon layer 3, a second polysilicon layer 4, etc. are formed, and an insulating film layer 5 is deposited and planarized. Next, as shown in FIG. 3B, a resist 6 is applied to form a plurality of contact holes, and patterned by a known photolithography (photolithography) technique.
The pattern of the contact holes 6a, 7a, 8a is obtained.

Next, as shown in FIG. 3 (c), the contact holes 6a,
7a and 8a are formed. This contact hole formation method is also used, but there is a second conventional method. The second conventional method will be described with reference to the sectional views of FIGS.

First, as shown in FIG. 4A, the semiconductor substrate 1
Diffusion layer 2 and the like are formed on top, and then, for example, first polysilicon layer 3 and second polysilicon layer 4 and the like are formed, and insulating film layer 5 is deposited and planarized. Next, as shown in FIG. 4B, in order to form the first contact hole formation on the second polysilicon 4, the contact hole 6a is formed in the insulating film layer 5 by a known photolithography (photolithography) technique.

Next, etching is performed by known dry etching, and then the second contact hole 7a is formed using the pattern of the resist 7. Second contact hole 7a
Are provided on the first polysilicon layer 3. Next, the third contact hole 8a is formed using the pattern of the resist 8. The third contact hole 8a is provided on the diffusion layer 2. At this time, contact implantation (implantation) (impurity implantation) 10 is simultaneously performed to increase the concentration of the upper portions 10a of the first and second polysilicon layers 3 and 4 (FIG. 4).
(D)).

Next, as shown in FIG. 5E, the resist 11 is formed.
Then, the area other than the contact hole 8a is covered, and the contact implanter 12 is driven. Basically the contact implant 10
And 12 are different kinds of impurities and need to be separated. Next, as shown in FIG. 5F, the contact holes 6a, 7a, 8a
In this process, the blanket tungsten 13 is buried by a cold wall type device. Next, as shown in FIG. 5 (g), the tungsten 13a is left only in the contact holes 6a, 7a, 8a by the overall etchback technique. Next, as shown in FIG. 5H, for the wiring metal, first, TiN14, Al.Si.Cu1
5, TiN 16 is applied in order, and wiring is patterned using the resist 17.

[0009]

As described above, in order to form the contact hole, the surface is flattened at the time of forming the contact hole. At this time, conversely, as a problem, the depth of the layer to be etched is different, so that a certain contact hole has a large amount of overetching. In the case of the first conventional method, the time for exposing the shallowest part of the contact hole to etching becomes long until the deepest contact hole is formed, and the overetching of parts A and B shown in FIG. Is a problem. In particular, since the gate electrode is generally inevitable in the shallow portion of the contact hole due to the device structure, it is necessary to prevent charge-up from occurring so as not to cause gate breakdown, and when there are many steps as in the second conventional technique. The process was complicated because it was necessary to perform contact photolithography on each and etch each.
Further, since the contact hole is also fine, the insulating film of the flattening film has a problem that the i-line stepper, for example, has a high transmittance and the hole cannot be opened due to its high viscosity.

The present invention avoids the above-described overetching at the time of contact etching and eliminates the complexity of contact hole formation, and the photolithography of the contact opening is performed only once, and gate breakdown and charge-up occur. The present invention has the advantage of improving the contact opening characteristics as well as providing a method of forming the same.

[0011]

For the above-mentioned purpose, the present invention provides a method for forming a contact hole having a deep hole and a shallow hole in terms of device structure, which is a photolithographic antireflection film (AR).
M) (the present invention is TiN), photolithography of the contact holes is performed once to improve the contact opening characteristics, and each of these is individually etched using this ARM film,
In each case, contact implants were applied at the same time.

[0012]

As described above, according to the present invention, the anti-reflection film of photolithography is used, contact photolithography is performed once, and accordingly, only one mask is required and each etching process is divided. Therefore, it is possible to avoid damage and contamination of each exposed part of deep hole and shallow hole, and even if there is a part to open a contact hole on the gate electrode, the process does not cause gate breakdown and charge up does not occur. You can do it.

[0013]

1 to 2 are process sectional views showing an embodiment of the present invention, which will be described step by step below.

First, as shown in FIG. 1A, the semiconductor substrate 1
A diffusion layer 2 is formed thereon, a first polysilicon layer (eg, first gate electrode) 3 and a second polysilicon layer 4 are formed, and then a planarization insulating film 5 (eg, BPSG (boron phosphorus silicate glass)) is formed. ) Is formed of TEoS (tetraethoxylane) or the like (up to here is the same as before), and then a photolitho antireflection film (ARM), for example, a TiN film 14 is formed thereon.

Next, a plurality of predetermined positions (three in this example)
Resist 6 for opening contacts 6a, 7a, 8a
Then, as shown in FIG. 1B, patterning is performed by a known photolithography technique to obtain a resist pattern 6. Next in FIG.
As shown in (c), the etching on the second polysilicon layer 4 is performed, but at the same time, the etching on the first polysilicon 3 and the diffusion layer 2 also progresses. The etching at this time is performed so that any contact hole (6a, 7a, 8a) is formed in the second polysilicon layer 4.
Etching to the upper position. In this etching, first, the etching gas for the TiN film 14 is BCl ₃
+ Cl ₂ is used. When etching with this gas, Ti
Since it is known that the N film 14 and the BPSG 5 are etched at the same time, the BPSG ₅ changes the gas to CF ₄ and increases the pressure to perform etching.

Next, as shown in FIG. 1 (c), the contact implant 10 is applied to the entire surface. In this case, impurities are implanted only in the second polysilicon layer 4 and other contact holes 7
In a and 8a, the insulating film 5 is implanted. Next, as shown in FIG. 1D, only the contact hole 6a is covered with the resist 9,
The contact etching of a is performed, and etching is performed up to the first polysilicon layer 3. At this time, the contact hole 8a is also etched. Where there is no resist 9, TiN
14 is a mask. Further, since the implantation (impurity implantation) is performed, the etching rate is high. Next, the same impurities 10 as those on the second polysilicon layer 4 are formed.
Are implanted into the first polysilicon layer 3. At this time, impurities are also implanted into the contact hole 8a. Next, as shown in FIG. 2E, the contact holes 6a and 7a are covered with a resist 11,
The contact hole 8a is etched. Since impurities are implanted, the etching rate is fast. After that, the contact implant 12 is driven. This completes the contact hole and contact implantation. After that, the embedding blanket W13 is formed of a cold wall type CUD (FIG. 2 (f)). Next, the entire surface is etched back, and thereafter, the same steps as the conventional method are performed (FIGS. 2 (g) (h)).

[0017]

As described in detail above, according to the present invention, since the antireflection film for photolithography is formed and the photolithography of the contact hole is performed once, only one mask is required. By dividing the etching process, damage to exposed parts of deep holes and shallow holes
Contamination can be avoided, and even if there is a portion where a contact hole is formed on the gate electrode, a manufacturing method that does not cause gate breakdown and does not cause charge-up can be realized.

[Brief description of drawings]

FIG. 1 is a first embodiment of the present invention.

FIG. 2 is a second embodiment of the present invention.

FIG. 3 Conventional Example 1

FIG. 4 Conventional Example 2 (1)

FIG. 5 Conventional Example 2 (Part 2)

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Diffusion layer 3 First polysilicon layer 4 Second polysilicon layer 5 Flattening insulating film 6 Resist pattern 6a, 7a, 8a Contact hole

Claims (1)

[Claims] 1. Forming a contact hole in a semiconductor device, comprising forming an insulating film on a semiconductor substrate, forming a photolithographic antireflection film on the insulating film, and then forming a contact hole. Method.