JPH0653227A - Semiconductor device and electric circuit - Google Patents

Abstract

PURPOSE:To obtain the title semiconductor device wherein, when it is operated at high current density, its characteristic change is extremely small and it is provided with a mesa-shaped heterojunction bipolar transistor by a method wherein at least the circumference on the side face of an emitter layer is formed as a space which is filled with the air or an inert gas. CONSTITUTION:A semiconductor device is provided with a heterojunction bipolar transistor which is constituted of a base layer 4, of an emitter layer 6 formed at the upper part of the base layer 4 and of a collector layer 3 formed at the lower part of the base layer 4. In the semiconductor device, at least the circumference on the side face of the emitter layer 6 is formed as a space which has been filled with the air or an inert gas. For example, a subcollector layer 2, a collector layer 3, a base layer 4,a spacer layer 5, an emitter layer 6 and cap layers 7, 8 are grown on a semiinsulating GaAs substrate 1, and an AlGaAs/ Gaps mesa-shaped heterojunction bipolr transistor is manufactured by photolithography and etching. Then, a surface protective film is not formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a heterojunction bipolar transistor and an electric circuit using the heterojunction bipolar transistor.

[0002]

2. Description of the Related Art A conventional III-V compound semiconductor device having a heterojunction bipolar transistor is disclosed, for example, in Japanese Journal of Applied Physics, Vol. 24 (1985), pages L596 to L59.
Page 8 (Japanese Journal of Applied Physics 24 (1
985) pp. L596 to L598), a so-called mesa-type emitter layer is provided on the base layer, and a collector layer is provided below the base layer.
O ₂ or SiN was used, and a metal containing Au as a main component was used for the emitter electrode, the base electrode and the collector electrode.

[0003]

The above prior art is particularly concerned with AlGaAs / Ga using Be as the base layer p-type impurity.
1 × for As heterojunction bipolar transistors
There is a problem that the collector current is reduced when continuously operated at a collector current density of 10 ⁵ A / cm ² or more. AIE International Electron Device Meeting 1990 (1990)
Year) 673 to 676 (IEEE International
l Electron Device Meeting 1990 (1990) pp. 673
~ 676). The same problem applies to the case of the III-V group compound semiconductor mesa type heterojunction bipolar transistor using Zn as the base layer impurity and the case of other mesa type heterojunction bipolar transistors. It is considered that this is because the energy generated in the recombination process of carriers generated by the energization promotes the diffusion of the base layer impurities into the emitter layer around the emitter mesa. Such a phenomenon causes problems such as deterioration of current amplification factor and shift of on-voltage, which impairs reliability of the mesa heterojunction bipolar transistor and an electric circuit using the same.

It is an object of the present invention to provide a semiconductor device having a mesa type heterojunction bipolar transistor in which characteristic fluctuation during high current density operation is extremely small. Another object of the present invention is to provide an electric circuit using a mesa type heterojunction bipolar transistor in which characteristic fluctuation during high current density operation is extremely small.

[0005]

The above objects are (1) a heterojunction bipolar transistor including a base layer, an emitter layer provided above the base layer, and a collector layer provided below the base layer. (2) In the semiconductor device according to the above (1), the base layer surface may be a space filled with air or an inert gas at least around the side surface of the emitter layer. A semiconductor device in which only the spacer layer and the base electrode are in contact, (3) a base layer, an emitter layer provided above the base layer, and a collector layer provided below the base layer In the semiconductor device having the heterojunction bipolar transistor described above, the stress generated in the emitter layer becomes substantially zero. (4) A heterojunction bipolar transistor including a base layer, an emitter layer provided above the base layer, and a collector layer provided below the base layer. In the semiconductor device having the semiconductor device, the insulating film provided around the side surface of the emitter layer has a surface at a position lower than a bottom surface of the emitter layer, (5) The semiconductor device according to 4 above, The insulating film near the base layer has a surface position lower than that of the base layer surface, (6)
7. The semiconductor device according to any one of 1 to 5 above, wherein the semiconductor forming the base layer, the emitter layer, and the collector layer is a III-V group compound semiconductor. ) In the semiconductor device as described in 6 above, the base layer contains Be as an impurity and its conductivity type is p-type. (8) In the semiconductor device as described in 6 above, the base is The layer contains Zn as an impurity and its conductivity type is p
(9) In the semiconductor device according to any one of 1 to 8 above, the emitter electrode and the base electrode electrically connected to the emitter layer and the base layer respectively are A semiconductor device having a coefficient of expansion of 10% or less difference from the coefficient of thermal expansion of a semiconductor layer on which each electrode is formed, (10) In the semiconductor device described in 9 above, the metal is W. Or Ta
Alternatively, a semiconductor device characterized by being an alloy containing any of these as a main component, (11) In the semiconductor device according to any one of 1 to 10, the exposed portion of the heterojunction interface of the heterojunction bipolar transistor is exposed. , S, S
This is achieved by a semiconductor device characterized by the presence of at least one element selected from the group consisting of e and Te.

Another object is to (12) have at least two bipolar transistors, the collectors of the two bipolar transistors being coupled through resistors, and the respective emitters being coupled to the respective bases. In an electric circuit having a differential amplifier circuit having a function of amplifying a difference between input signals, the two bipolar transistors are heterojunction bipolar transistors of the semiconductor device according to any one of 1 to 11 above. This is achieved by an electric circuit characterized in that

The present invention is effective when applied to a compound semiconductor device. In particular, the III-V group compound semiconductor device has the above-mentioned problems conspicuously recognized. Therefore, it is preferable to apply the present invention to the III-V group compound semiconductor device. Further, in order to take the configurations of the above items (1) and (3), for example, at least the side surface of the emitter layer may not be in contact with the insulating film.
Furthermore, it is preferable that the surface of the base layer does not come into contact with the insulating film.

[0008]

By at least forming the emitter layer or its side surface periphery as described above so that the side surface of the emitter layer does not come into contact with the insulating film, and further, the surface of the base layer does not come into contact with the insulating film. In addition, it is possible to suppress the characteristic fluctuation during high current density operation as compared with the conventional one. in addition,
By using a metal having a coefficient of thermal expansion which is less than 10% of the coefficient of thermal expansion of the semiconductor layer on which the emitter electrode and the base electrode are provided as the metal forming the emitter electrode and the base electrode, a high current density can be obtained. Characteristic fluctuation during operation can be minimized. This is based on the newly found experimental fact that the characteristic fluctuation during high current density operation has a stress dependency between the insulating film and the semiconductor interface. Hereafter, this is shown in FIG.
Starting from FIG. 7, description will be made.

FIG. 4 is a sectional view of a conventional AlGaAs / GaAs mesa heterojunction bipolar transistor fabricated on a GaAs (100) substrate. Semi-insulating GaA
Highly doped n-type GaAs layer (Si concentration = 5
X10 ¹⁸ / cm ³ , thickness 0.5 μm, subcollector layer 2, n-type GaAs layer (Si concentration = 5 × 10 ¹⁶ / c)
m ³ , and a thickness of 0.4 μm), a collector layer 3, a highly-doped p-type GaAs layer (Be concentration = 4 × 10 ¹⁹ / cm ⁹ , and a thickness of 0.1 μm) 4, an undoped GaA.
Spacer layer 5 consisting of s layer (thickness 0.01 μm), n-type AlGaAs layer (AlAs molar ratio = 0.3, Si concentration =
1 × 10 ¹⁸ / cm ³ , thickness 0.15 μm), emitter layer 6, highly doped n-type InGaAs layer (InAs molar ratio gradually changes from 0 to 0.5, Si concentration = 1 × 10
¹⁹ / cm ³ , thickness 0.1 μm) cap layer 10
1 was grown by a molecular beam epitaxy method, and photolithography and etching were performed. Emitter electrode 102
The AuGe-based material is used for the collector electrode 104 and the AuZn-based material is used for the base electrode 103.
SiO ₂ was used for 5.

FIG. 5 shows typical current-voltage characteristics before and after the high current density operation test of the conventional heterojunction bipolar transistor shown in FIG. The energization test was performed at room temperature for 10 minutes with an initial collector current density Jco of 2.5 × 10 ⁵ A / cm ² . The solid line shows the current-voltage characteristics before energization and the broken line shows the current-voltage characteristics after energization. The collector current density was reduced by energization, and as a result, the current amplification factor was also reduced. When the ratio of the collector current density after energization to the collector current density before energization at the base-emitter voltage V _BE = 1.2 V is defined as k, k is SiO ₂ used as a protective film as shown in FIG. It was found that depending on the film thickness d, k becomes closer to 1 as d becomes smaller, that is, characteristic fluctuations are less likely to occur. Since the smaller the d is, the smaller the stress applied to the emitter layer and the base layer from the insulating film, the B
This is probably because the diffusion of e into the emitter layer was reduced. It is presumed that the reason why k = 1 does not hold even when d = 0 is that the semiconductor layer provided with the emitter electrode and the base electrode has residual stress applied from those electrodes. In this case, the stress that the cap layer provided with the emitter electrode receives from the electrode also extends to the emitter.

Therefore, FIG. 7 shows the result of conducting a high current density operation test by changing the main component of the metal material of the emitter electrode and the base electrode in the state of d = 0. A metal having a smaller difference in coefficient of thermal expansion from the semiconductor layer provided with the emitter electrode and the base electrode is less likely to cause characteristic variations, and particularly W or Ta having the difference in coefficient of thermal expansion of 10% or less or containing these as the main components. It was found that the use of metal can reduce the characteristic variation during high current density operation to a negligible level. Other III-V
Since the coefficient of thermal expansion of group III compound semiconductors is almost equal to that of GaAs, the same effect can be obtained by using Zn as a mesa type heterojunction bipolar transistor using another III-V group compound semiconductor or a mixed crystal thereof, a base layer and p type impurities. It was also observed for the existing mesa-type heterojunction bipolar transistor.

Further, in order to integrate the III-V group mesa type heterojunction bipolar transistor using the above means, it is necessary to provide wiring to each electrode of the emitter, the base and the collector. By allowing only air or an inert gas to exist in the space between the heterojunction interface exposed around the mesa, it is possible to prevent the occurrence of characteristic fluctuations when the wiring interlayer insulating film is used. . Further, by having S, Se or Te of 2 atomic layers or less on the heterojunction interface exposed around the mesa type portion, dangling bonds of the element in that portion are terminated, and long-term reliability is guaranteed. Obtainable.

Further, by using the above-mentioned mesa type heterojunction bipolar transistor in all or at least the differential amplifier circuit section to form an electric circuit,
An electric circuit with excellent reliability can be manufactured over a long period of time. The differential amplifier circuit requires two transistors with uniform characteristics, but if the above-mentioned mesa heterojunction bipolar transistor is used in this part, the characteristic fluctuation during high current density operation is extremely small, and This is because the characteristic of does not change.

[0014]

EXAMPLES Example 1 Hereinafter, as a base layer impurity, which is a first example of the present invention, B was added.
A semiconductor device having an AlGaAs / GaAs mesa heterojunction bipolar transistor using e will be described.
As shown in FIG. 1, a highly-doped n-type GaAs layer (Si concentration = 5 × 10 ¹⁸ / c) was formed on the semi-insulating GaAs substrate 1.
m ³ , thickness 0.5 μm) of the sub-collector layer 2, n
-Type GaAs layer (Si concentration = 5 × 10 ¹⁶ / cm ³ , thickness 0.4 μm), collector layer 3, highly-doped p-type Ga
As layer (Be concentration = 4 × 10 ¹⁹ / cm ⁹ , thickness 0.1 μm)
m) the base layer 4, the undoped GaAs layer (thickness 0.01 μm) the spacer layer 5, and the n-type AlGaA.
s layer (AlAs molar ratio = 0.3, Si concentration = 1 × 10 ¹⁸
/ Cm ³ , the thickness of 0.15 μm), the emitter layer 6,
Highly doped n-type InGaAs layer (InAs molar ratio gradually changes from 0 to 1, Si concentration = 1 × 10 ¹⁹ / cm ³ ,
0.1 μm thick cap layer 7, highly doped n-type InAs layer (Si concentration = 1 × 10 ¹⁹ / cm ³ , thickness 0.
A cap layer 8 of 1 μm) was grown by a molecular beam epitaxy method, and an AlGaAs / GaAs mesa heterojunction bipolar transistor was manufactured by photolithography and etching. W was used for the emitter electrode 9, the base electrode 10, and the collector electrode 11.

In this mesa type heterojunction bipolar transistor, k = 1 even when the Jco was 2.5 × 10 ⁵ A / cm ^{2 and} current was applied for 10 minutes at room temperature, that is, no characteristic variation was observed. According to the present embodiment, the stress generated in the semiconductor layer is not used because the surface protective film is not used and W having a difference in coefficient of thermal expansion from the semiconductor layer provided with the electrode is 8% is used as the electrode material. Can be substantially zero,
We were able to realize a mesa-type heterojunction bipolar transistor with extremely small characteristic fluctuations at high current density operation.

In this embodiment, W is used for each of the emitter, base, and collector electrode materials, but Ta may be used, or an alloy film containing W or Ta as a main component or a laminated film having these as lower layers. Good. In the case of Ta, the difference in the coefficient of thermal expansion from the semiconductor layer provided with the electrode is 4%. Further, the collector electrode does not need to be the above metal material. In this embodiment, A
Although the case of the 1GaAs / GaAs heterojunction bipolar transistor is shown, other III-V group compound semiconductors such as InAlAs / InGaAs and InP / InGaAs are shown.
The same can be applied to the case of the mesa type heterojunction bipolar transistor using. Further, although Be was used as the base layer impurity in this example, similar effects were obtained when Zn was used.

Second Embodiment A semiconductor device having an AlGaAs / GaAs heterojunction bipolar transistor having a space between a wiring metal extracted from an emitter electrode and a side surface of the emitter layer, which is a second embodiment of the present invention, will be described below. To do. 2a is a plan view of the AlGaAs / GaAs mesa heterojunction bipolar transistor, FIG. 2b is a cross-sectional view taken along the cut plane AA ', and FIG. 2c is a cross-sectional view taken along the cut plane BB'. The structure is the same as that of the mesa heterojunction bipolar transistor shown in Fig. 1 except for the wiring metals 12, 12 ', 12 "and the insulating film 13. The wiring metals 12, 12', 1
Al is used for 2 ″ and a SiO ₂ film is used for the insulating film 13, but other metal materials and other insulating films may of course be used. The insulating film 13 is only for the semiconductor layers below the base layer 4. It is formed so as to be in contact with and not to contact with the semiconductor layers above the spacer layer 5. The wiring metal 12 extracted from the emitter electrode is isolated from the semiconductor layer by separating the air 14 as shown in FIG. It is formed so as to reach the film 13. On the other hand, the wiring metal 12 ″ drawn from the base electrode extends as it is on the insulating film 13 as shown in FIG.

This structure was formed as follows. After forming the structure shown in FIG. 1, an insulating film 13, a wiring metal 12 ′ to the collector electrode and a wiring metal 12 ″ to the base electrode are formed by photolithography and etching to have a thickness of about 1
A pattern of the lower layer resist 110 having a thickness of μm is formed, and an Au film 12a having a thickness of 500 Å which is a part of the wiring metal is deposited (FIG. 2d). Next, the upper layer resist 11 having a thickness of about 1 μm
A pattern of 0 ′ is formed, and Au is plated by 0.9 μm on the exposed Au film 12a by the selective plating method to form the wiring metal 12 (FIG. 2e). Further, the lower layer resist 110 and the upper layer resist 110 'are removed to obtain the structure shown in FIG. 2b.

FIG. 2f is a sectional view after encapsulation of the package. A semiconductor chip 15 including an AlGaAs / GaAs mesa heterojunction bipolar transistor is sealed in a metal package 16 together with an inert gas 17 such as Ar. Therefore, the space between the emitter layer 6 and the wiring metal 12 is filled with the inert gas.

Even when the present AlGaAs / GaAs mesa heterojunction bipolar transistor is energized for 10 minutes at room temperature with Jco of 2.5 × 10 ⁵ A / cm ^{2 in} the state of FIGS. 2c and 2d, k = 1, that is, No characteristic variation was observed. According to this example, the insulating film is not in contact with the side surface of the emitter layer and the surface of the base layer, the wiring metal extracted from the emitter electrode is not in contact with the emitter layer and the base layer, and the semiconductor provided with the electrode is further provided. By using W or Ta whose coefficient of thermal expansion is almost the same as that of the layer material as the electrode material, the stress generated in the semiconductor layer can be substantially reduced to zero, and the characteristic variation during operation at high current density is extremely small. Type heterojunction bipolar transistor could be realized.

In this embodiment, AlGaAs / GaA is used.
Although the case of the s heterojunction bipolar transistor is shown, the same applies to the case of the mesa type heterojunction bipolar transistor using another III-V group compound semiconductor. Further, although Be is used as the base layer impurity in the present embodiment, similar effects can be obtained when Zn is used.
Further, a ceramic package may be used instead of the metal package, and the gas to be sealed may be air.

Example 3 A sample containing a mesa heterojunction bipolar transistor in the state shown in FIGS. 2b and 2c of Example 2 was immersed in an ammonium sulfide solution to form a sulfur (S) deposition layer on the surface of the semiconductor layer. did. After washing the sample with water, in a hydrogen atmosphere at 350 ° C,
By heating for 15 minutes, S remaining on the surface of the semiconductor layer was reduced to 2 atomic layers or less.

This mesa-type heterojunction bipolar transistor also had no characteristic fluctuation during high current density operation as in the second embodiment. According to this embodiment, the surface of the semiconductor layer is S
Since it is covered with an atomic layer, dangling bonds of elements on the surface are terminated, there is no concern about characteristic fluctuation due to contamination with impurities, etc., and there is an effect that reliability can be guaranteed for a long period of time.

In this embodiment, AlGaAs / GaA is used.
Although the case of the s heterojunction bipolar transistor is shown, it can be similarly applied to the case of the mesa type heterojunction bipolar transistor using another III-V group compound semiconductor. Further, although Be was used as the base layer impurity in this example, similar effects were obtained when Zn was used.

Example 4 A sample including the mesa heterojunction bipolar transistor in the state shown in FIGS. 2b and 2c of Example 2 was placed in a vacuum container and irradiated with Se molecular beam at 350 ° C. On this occasion,
The Se layer formed on the surface of the semiconductor layer was 2 atomic layers or less.

This mesa type heterojunction bipolar transistor also had no characteristic fluctuation during high current density operation as in the second embodiment. According to this embodiment, the surface of the semiconductor layer is S
Since it is covered with the e atomic layer, dangling bonds of elements on the surface are terminated, there is no fear of characteristic fluctuation due to contamination with impurities, etc., and there is an effect that reliability can be guaranteed for a long period of time.

In this embodiment, AlGaAs / GaA is used.
Although the case of the s heterojunction bipolar transistor is shown, it can be similarly applied to the case of the mesa type heterojunction bipolar transistor using another III-V group compound semiconductor. Further, although Be was used as the base layer impurity in this example, similar effects were obtained when Zn was used. Furthermore, the same effect was obtained by using Te instead of Se.

Although the above-mentioned Examples 1 to 4 describe the mesa type heterojunction bipolar transistor using the III-V group compound semiconductor, the mesa type heterojunction using the II-VI group compound semiconductor or the Si-SiGe compound semiconductor. The same can be applied to the case of the junction bipolar transistor.

Example 5 Hereinafter, as a base layer impurity, which is a fifth example of the present invention, B was added.
A differential amplifier circuit using an AlGaAs / GaAs heterojunction bipolar transistor using e will be described with reference to FIG. A differential amplifier circuit was manufactured using the mesa type heterojunction bipolar transistor shown in Example 1 as the transistors Q ₁ , Q ₂ and Q ₃ in FIG. In the figure,
V _i is an input voltage, V _R is a reference voltage, V ₀₁ and V ₀₂ are output voltages, and R ₁ , R ₂ and R ₃ are resistors.

In the conventional differential amplifier circuit using the mesa type heterojunction bipolar transistor, Jco is 2 × 10 ⁵
When operating at a high current density higher than A / cm ^2, the characteristics of the transistors Q ₁ and Q ₂ fluctuated, the characteristics of the transistors Q ₁ and Q ₂ changed independently, and the differential amplifier circuit could not operate normally. However, since the differential amplifier circuit of the present embodiment uses the heterojunction bipolar transistor whose characteristic fluctuation during high current density operation is extremely small, the characteristic fluctuation during high current density operation of the differential amplifier circuit can be suppressed to be extremely small. I was able to.

The above embodiment is the same as A shown in the first embodiment.
Although the 1GaAs / GaAs mesa type heterojunction bipolar transistor is used, the other AlGaAs / GaAs mesa type heterojunction bipolar transistors shown in Examples 2 to 4 may be used instead. A mesa heterojunction bipolar transistor using another III-V compound semiconductor and Zn as a base layer impurity
The same effect was observed using a mesa type heterojunction bipolar transistor using.

[0032]

According to the present invention, there is an effect that the characteristic variation of a semiconductor device having a heterojunction bipolar transistor at the time of high current density operation can be made extremely small. Further, in the semiconductor device having a structure in which dangling bonds on the heterojunction interface exposed at the periphery of the mesa are terminated, there is no fear of characteristic fluctuation due to contamination with impurities or the like, and therefore, there is also an effect that long-term reliability can be guaranteed. . Further, an electric circuit using such a heterojunction bipolar transistor in a differential amplifier circuit can reduce characteristic fluctuation during high current density operation.

[Brief description of drawings]

FIG. 1 is an AlGaAs / GaA according to a first embodiment of the present invention.
It is sectional drawing of an s heterojunction bipolar transistor.

FIG. 2a is a second embodiment of the present invention AlGaAs / Ga.
It is a top view of an As heterojunction bipolar transistor.

FIG. 2b is an AlGaAs / Ga according to a second embodiment of the present invention.
It is sectional drawing of an As heterojunction bipolar transistor.

FIG. 2c is an AlGaAs / Ga according to a second embodiment of the present invention.
It is sectional drawing of an As heterojunction bipolar transistor.

FIG. 2d is a second embodiment of the present invention AlGaAs / Ga.
FIG. 9 is a cross-sectional view for explaining the manufacturing process of the As heterojunction bipolar transistor.

FIG. 2e: AlGaAs / Ga according to the second embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the manufacturing process of the As heterojunction bipolar transistor.

FIG. 2f: AlGaAs / Ga according to the second embodiment of the present invention.
It is sectional drawing after package encapsulation of an As heterojunction bipolar transistor.

FIG. 3 is a circuit diagram of a differential amplifier circuit of the present invention using a heterojunction bipolar transistor.

FIG. 4 is a cross-sectional view of a conventional AlGaAs / GaAs heterojunction bipolar transistor.

FIG. 5 is a diagram showing changes in current-voltage characteristics of a conventional AlGaAs / GaAs heterojunction bipolar transistor due to energization.

FIG. 6 is a graph showing the SiO ₂ film thickness dependence of the characteristic variation of a conventional AlGaAs / GaAs heterojunction bipolar transistor due to energization.

FIG. 7 is a diagram showing electrode metal material dependence of characteristic variation of an AlGaAs / GaAs heterojunction bipolar transistor due to energization.

[Explanation of symbols]

1 semi-insulating GaAs substrate 2 subcollector layer 3 collector layer 4 base layer 5 spacer layer 6 emitter layer 7, 8, 101 cap layer 9, 102 emitter electrode 10, 103 base electrode 11, 104 collector electrode 12, 12 ', 12 Wiring metal 12a Au film 13 Insulating film 14 Air 15 Semiconductor chip 16 Metal package 17 Inert gas 105 Surface protective film 110 Lower layer resist 110 ′ Upper layer resist Q ₁ , Q ₂ , Q ₃ Transistor R ₁ , R ₂ , R ₃ resistance V ₀₁ , V ₀₂ Output voltage V _i Input voltage V _R Reference voltage

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Chushiro Kusano 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (12)

[Claims] 1. A semiconductor device having a heterojunction bipolar transistor including a base layer, an emitter layer provided above the base layer, and a collector layer provided below the base layer, at least the side surface of the emitter layer. A semiconductor device characterized in that the surrounding area is a space filled with air or an inert gas. 2. The semiconductor device according to claim 1, wherein the surface of the base layer is in contact with only the spacer layer and the base electrode. 3. A semiconductor device having a heterojunction bipolar transistor including a base layer, an emitter layer provided above the base layer, and a collector layer provided below the base layer, wherein the emitter layer comprises: A semiconductor device characterized in that the stress generated in this layer is substantially zero. 4. A semiconductor device having a heterojunction bipolar transistor including a base layer, an emitter layer provided above the base layer, and a collector layer provided below the base layer. The insulating film provided on the semiconductor device is characterized in that its surface is located lower than the bottom surface of the emitter layer. 5. The semiconductor device according to claim 4, wherein the surface of the insulating film near the base layer is located lower than the surface of the base layer. 6. The semiconductor device according to claim 1, wherein the semiconductors forming the base layer, the emitter layer, and the collector layer are III-V group compound semiconductors. Semiconductor device. 7. The semiconductor device according to claim 6, wherein the base layer contains Be as an impurity, and its conductivity type is
A p-type semiconductor device. 8. The semiconductor device according to claim 6, wherein the base layer contains Zn as an impurity, and its conductivity type is
A p-type semiconductor device. 9. The semiconductor device according to claim 1, wherein the emitter electrode and the base electrode, which are electrically connected to the emitter layer and the base layer respectively, are formed with electrodes having a coefficient of thermal expansion. Coefficient of thermal expansion of the semiconductor layer and 10
A semiconductor device comprising a metal having a difference of not more than%. 10. The semiconductor device according to claim 9, wherein the metal is W or Ta or an alloy containing these as a main component. 11. The semiconductor device according to claim 1, wherein the exposed portion of the heterojunction interface of the heterojunction bipolar transistor is at least one selected from the group consisting of S, Se and Te. A semiconductor device characterized by the presence of the element. 12. At least two bipolar transistors are provided, the collectors of the two bipolar transistors are coupled through a resistor, and the respective emitters are coupled to obtain a difference between signals input to respective bases. In an electric circuit having a differential amplifier circuit having a function of amplifying, the two bipolar transistors are heterojunction bipolar transistors of the semiconductor device according to any one of claims 1 to 11. circuit.