JPH0652052A - Virtual shared memory system - Google Patents

Abstract

PURPOSE:To accelerate processing and to perform parallel processing in accordance with the number of processors flexibly by managing by unifying data and a processing program, and loading them on the processor comprehensively. CONSTITUTION:This system is comprised of the processor equipped with a register file and input/output cache. a device managing part which controls the input/output cache, a processor inside register managing part which loads or manages the content of the register file and that of the input cache on the ALU of the processor, a bus managing part, a processor managing part, and a program instruction distribution means which distributes a program instruction to the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output processing system and apparatus from the outside of a computing device, and relates to I / O of data in a storage means and a transmission / reception processing program command in a communication system.
The present invention relates to a batch processing method, a parallel processing method, and a constituent device.

[0002]

2. Description of the Related Art In the prior art, only the I / O processing method in a single processor configuration is taken into consideration. The program instruction is loaded into the processor from the system space or the program instruction storage space, and the contents of the program instruction code are interpreted. After that, the data required by the program instruction is waited for another timing, and the data is loaded from the storage means to the processor every time the data is required.

After the loaded data is interpreted by the program stored in the register and processed by the ALU, it is written back to the cache or memory, and data is newly added from the cache or memory according to the content of the next program instruction. Is loaded and the following processing is performed.

At this time, if the data is simply written back to the cache, there is no related information or relationship between the next program command content and the data. Therefore, the effectiveness of the cache is not always used to guarantee the consistency. In addition, the data may be written back to the memory and then reloaded to the cache again.

As described above, the program command and the data are managed in different dimensions, and the program command itself manages or designates the data, so that a large number of timings elapse for one processing process and the bus is processed. I / O processing is performed by reciprocating the data.

[0006]

In the prior art, only the sequential processing method in the single processor configuration is taken into consideration, and the program instruction and the data are separately loaded into the processor at a plurality of timings to complete the processing. Was there. In that mechanism, a processing wait time until the program instruction is loaded into the processor, a load wait time until the data is loaded into the register after the program instruction is loaded into the processor, and both of them take the bus right. There is a problem that a waiting time for securing the bus use right occurs because it cannot be secured immediately, and thus the time required for the transmission processing or the reception processing of I / O data or the like becomes long.

An object of the present invention is, in a first aspect, to provide a method and apparatus for dividing a program instruction into primitives, transferring the program instruction and data to a processor and a cache or a register at the same time, and minimizing the processing time. To do.

In a second aspect, in a multiprocessor system, it is possible to distribute the processing for each processor and realize parallelization of I / O data processing,
A method and apparatus for improving data processing speed are provided.

Another object of the present invention is to provide a method in which the I / O processing capacity can be selected according to the number of processors even if the number of processors is increased or decreased according to the scale of the communication system. is there.

Still another object of the present invention is to separate the header processing, the data transfer management processing, and the acknowledgment processing, which are specified by the processing contents peculiar to the communication system, from the other program processing, and temporarily set the processor to the virtual communication system. It is changed to a dedicated processing device to guarantee high-speed communication processing.

[0011]

In order to solve the above problems, the present invention provides an I / O corresponding to a data unit from an information storage means capable of holding I / O information such as a memory or a cache from the I / O. By linking with the O processing program instruction, the program instruction and I / O data are virtually managed in the shared storage means as a unit, and a vacancy occurs in the processor, the register, or the device of the input cache,
When it becomes possible to use the device, program instructions and data are simultaneously transferred to the device to perform I / O processing.

Further, in a system in which a plurality of the devices are mounted, a device distribution management means for monitoring the devices secures the vacant device and arranges I / O processing wait data and program instructions in an optimum order. While loading.

Furthermore, a processing program instruction code is attached to one or a plurality of processors in a data unit and stored in an input cache and a register file of the processor, and consistent processing is performed inside the processor independently of the bus usage right. Data input / output on a processor-by-processor basis until all the data in the input cache is processed, or until the right to use the bus is secured to transfer the processed data to the user program command or the storage means. It manages.

[0014]

First, I / O is used by virtually managing the I / O use data or the data from the I / O and the corresponding I / O processing program instruction on the correspondence table in the shared storage means. It is possible to link each I / O processing program instruction to the data to be processed or the data from the I / O.

Second, the program instruction and the data are integrated and loaded into the cache or the register, so that the consistency of the data and the program instruction is guaranteed, and the processing is collectively performed without causing a cache mishit. It will be possible to do.

Thirdly, the processing can be performed in data units by one or a plurality of processors, and the processing time in transaction units can be shortened.

Fourthly, by providing the processor with an input / output cache, it becomes possible to perform I / O processing in data units independently of the bus usage right, and the processing time can be shortened.

Fifth, by providing a cache data transfer management unit for each processor, it is possible to flexibly deal with an increase or decrease in the number of processors and to provide a processing capacity according to the number of processors when the system is changed. .

[0019]

EXAMPLE An example of the present invention will be described in detail below.

FIG. 1 is a flow chart showing an embodiment of a processing procedure when the present invention is applied to a communication system using an I / O processor, and FIG. 2 is a communication processing apparatus according to the present invention. 3 is a block diagram showing a configuration of a device inside the device. FIG. Further, FIG. 3 is a flowchart showing the flow of processing by adding the control relationship from each device to the flowchart of FIG. FIG. 4 is a block diagram showing a logical management space of a storage means for storing data using I / O. FIG. 5 is a block diagram showing the structure of the data structure optimizing processing means for transfer to the processor in the storage means and the data in the storage means according to the present invention. FIG. 6 is a block diagram showing the internal configuration of the I / O processing optimization processor according to the present invention. FIG. 7 shows that the I / O processing system of the present invention is used as a single high-speed I / O information processing system with a plurality of I / O ports mounted and equipped with standard input / output devices such as a display device, a disk device, and a keyboard. The block diagram of the application example of the client WS corresponding to the communication system in the case of performing is shown. FIG. 8 shows the I / O of the present invention.
The block diagram of the application example of the communication system compatible server WS in the case of connecting the processing system to WS and using it as a high-speed I / O information processing system LAN adapter is shown.

In FIG. 2, reference numeral 1 is an I / O port for inputting / outputting data to / from an external system, and 2 is a storage means for storing data and programs exchanged with the I / O port or the processor. And 4 are child processors that process the data in the storage means by the program instructions in the storage means, and 5 is a parent processor that further processes the output result of the child processor as necessary. Also, 5 can control the entire system. Furthermore, 5 can also be used when processing a normal system program other than I / O input / output.

In FIG. 4, reference numeral 6 denotes the entire logical system space in the storage means, which includes a system program 10 for I / O processing and a buffer 11 for the system, and 7 denotes the storage. The whole logical user space in the means is shown, and includes a user program 12 for I / O processing and a buffer 13 for the user program.
Is the buffer 11 of the system space 6 or the user space 7
9 is a shared management table space for optimally arranging the instruction code of the system program 10 or the user program 12 in the data existing in the buffer 13 of FIG.
Is a processor (child processor 3 or 4 shown in FIG. 2)
Is a virtual shared storage space for managing optimization information in which the code and data co-located with the program instruction code optimized for transfer to the processor, and 14 is a free state of the processor and the optimization information in the storage means. Is a storage unit management unit for managing the state of and the transfer of the optimization information to the processor.

In FIG. 5, reference numeral 29 denotes a storage means management section, which is a constituent element of the storage means 30 and holds the program instruction code 22 of the system space 17 or the program instruction code 21 of the user space 18. Is distributed to the data in the buffer 19 of the system space 17 or the buffer 21 of the user space 18, and the data in the buffer and the instruction code are optimally arranged in the virtual shared storage space. In order to control the system space and the user space, the virtual shared memory space pointer switching means 1 for virtually switching
6 and program distribution cache / register information management unit 2
Including 5. After the data fetched from the I / O bus 28 or the system bus 27 into the buffer (19 or 21) of the storage means 30 is processed by the storage means management unit 29,
The program instruction code (20 or 22) and data are stored in the virtual shared storage space 24 in order to manage the management information related to the processing in the shared management table 23 and transfer it to the processor (child processor 3 or 4 shown in FIG. 2). (19
Or 21 buffers) in the coexistence information, and
Of the data in the buffer (19 or 21), the data that has been processed by all the processors (child processors 3 or 4 shown in FIG. 2) or does not need to be processed is the buffer 19 in the system space 17 or the user space. In the buffer 21 of 18, from the I / O port (I / O port 1 shown in FIG. 2) to the host system device (server WS shown in FIG. 8) or an external device (for example, the display device or disk storage device shown in FIG. 7) Alternatively, it waits until the data is transferred to the LAN (the LAN transmission line shown in FIG. 7 or FIG. 8).

In FIG. 6, reference numeral 41 is a child processor (child processor 3 or 4 in FIG. 2), and its constituent elements are inputs that take in data from the data bus 31 and store and hold it until it is loaded into the register file 36. An output cache 40, a register 36, an ALU 38, an input / output cache 32, 40 that stores and holds the data saved in the register file 36 until all the operations in the cache 32 and the ALU 38 are completed and flowed to the system bus 31.
To the system bus 31 or to the register file 36, manages the states of the cache data transfer management unit 33, the input / output caches 32 and 40, and the register file 36 to transfer the cache data. The management unit 33, the ALU data load management unit 37, and the continuous program instruction code determination unit 39 for determining whether or not the program instruction codes associated with the data to be continuously processed in the register file 36 match continuously. Further, the cache data transfer management unit 33 exchanges control information with the storage unit management unit (the storage unit management unit 14 shown in FIG. 4) or the parent processor (parent processor 5 shown in FIG. 2) to synchronize the data transfer. Cash register management unit 35
Also notifies the storage means management unit 14 of the state of the cash register 32, 40 or 36.

Next, the operation of each part in FIG. 2, FIG. 5, FIG. 6, FIG. 7 or FIG. 8 will be described based on the flow charts in FIG. 1 and FIG.

Assume a processing operation when a data frame is received from the I / O port 1.

In FIG. 1, when a data frame is received from the I / O port, the FIFO stores the header information in the system buffer before detecting the end delimiter of the frame, and the message data used in the application layer is user space. Of the system bus or I / O port to transfer the data to a system such as the upper server WS.

Next, the data of the header information is analyzed, and the pointer of the data is recorded in the shared management table of program instructions / data (shared management table space 24 shown in FIG. 5) for each item of the header information or for each processing procedure. . Furthermore,
The pointer of the system program instruction code is placed at a fixed position in the structure for optimized storage. The structure data in which the elements of the data and the program instruction code are mixed in the virtual shared storage space (the virtual shared storage space 23 shown in FIG. 5) by the FIFO in the header information unit of the frame in which the processing is finished in the order in which the processing is finished. Is stored and waits for processing by the child processor (child processor 41 shown in FIG. 6).

When a transfer request from the child processor (child processor 41 shown in FIG. 6) is detected, the program instruction code and the data are transferred to the input cache 32 or the register file 36 all together. Then, the register file 36 is loaded. Set the program instruction code and data of the register file 36 to A
After the operation is performed on the LU (ALU 38 shown in FIG. 6) and the result is returned to the register file 36, if the operation is completed, the output cache (the output cache 40 shown in FIG. 6)
Transfer to. The data is transferred from the output cache 40 to the storage unit 30 or the parent processor 5, and the header processing of a series of received frame data is completed. It is desirable that this series of processing is performed by pipeline processing.

In FIG. 3, from I / O port 1 to I / O
Input is generated, and data is input to the storage means 2. When data is input to the storage unit 2, the virtual shared pointer switching unit 16 in the storage unit management unit (storage unit management unit 29 shown in FIG. 5) for optimally arranging the program instruction code.
Switches between the system space 17 and the user space 18, and the program instruction code distribution means 15 causes the shared management table 2
4, the data in the buffer 19 of the system space 17, or the pointer of the component of the data in the user space 18 and the program instruction code 20 in the system space 17, or
The pointer of the program instruction code 22 in the user space is arranged in the shared management table 24, and the program instruction code is distributed. When the distribution of the program instruction code is completed, the mixed structure data of the program instruction code and data components is stored in the virtual shared storage space 23. The program data distribution cache register management unit 25 in the storage unit management unit 29 uses the input cache 32 of the child processor 41.
And the register file 36 are monitored, and when a device availability notification and a synchronization signal are received from the cache data transfer management unit 33 and the cache register management unit 35 on the child processor 41 side, the virtual shared storage space 23 on the storage unit 30 side The data is transferred to the input cache 32, received by the cache data transfer management unit 33 on the child processor 41 side, and stored in the input cache 32. On the child processor 41 side, when the cache register management unit 35 loads the data stored in the input cache 32 into the register file 36, and the program instruction determination unit 39 further processes with the same instruction code first, Only the code used is provided to the ALU 38. When the ALU data load management unit 37 passes the data from the register file 36 to the ALU 38, the ALU 38 performs arithmetic operation on the contents of the register file 36, writes the result back to the register file 36, and when the arithmetic processing is completely completed, the register file 36 completes the operation. The cash register management unit 35 transfers the data to the output cache 40. Thereafter, the cache data transfer management unit 33 on the child processor 41 side inquires the storage unit management unit 29 and the storage unit 30 on the storage unit 30 side to transfer the processed data to the storage unit 30 or the parent processor 5. do it,
Further, the processing of the host system (server WS shown in FIG. 8) is enabled. When those processes are completed, other data is loaded and the process is continued.

In FIG. 5, storage means 3 at the time of data transmission
An example of the operation of 0 and the storage unit management unit 29 will be described.

When a transmission request is made from the upper system or the application layer in the user space, in the system of the present invention, the message data created by the user for transmission is stored in the buffer 21 of the user space 18 by pipeline processing. It is stored in the storage device of the host system. In response to a transmission request, the storage means management unit 29 of this system switches to the system space 17, and the program instruction code 20 of the processing required for transmission is set in the user space 1.
The pointer is arranged in the shared management table space 24 so as to correspond to the data components in the buffer 21 on the 8 side,
Allows you to create headers for communication systems. When creating this header, information processing that requires the entire frame is performed at the end of the process. For example, the calculation of the checksum information and the writing of the information value into the header structure are input to the storage means 30 or managed by the upper system side, and the information is notified of this system at the time of a transmission request.

In the case of this system (FIG. 2), when transmission data is created in the user space 18 or the host system, it is transferred to the user space 18 of the storage means 30 of the system of the present invention as a transmission buffer. At this time, the amount of moving data is being counted at the same time, which means that the information for the header creation processing is gathered. When the header creation process in the child processor 41 is completed, it is stored in the buffer 19 of the system space 17, and when the frame is sent to the LAN transmission line, the virtual shared pointer switching unit 16 of the storage means management unit 29 sets the system space 17 in the system space 17. While switching between the user space 18 and
According to the information in the shared management table space 24, the header data stored in the buffer 19 of the system space 17 and the message data in the buffer 21 of the user space 18 are combined to perform the transmission process.

As shown in FIGS. 7 and 8, the system of the present invention can be provided with a parent processor, so that another system can coexist at the same time, and by expanding the I / O port, it becomes a single WS. It can also be used as a processing LAN adapter dedicated to high-speed communication of the server WS. Particularly in the case of FIG. 8, communication processing is performed in parallel by the adapter, and the message data is directly sent to the server WS and processed with stable performance.

[0035]

As described above, according to the present invention, one or a plurality of processors can simultaneously perform data processing and I / O processing corresponding to the data independently of other processes. Therefore, high speed and stable cache miss-hit can be achieved. Performance is guaranteed.

[Brief description of drawings]

FIG. 1 is a flowchart showing an embodiment of a processing procedure of the present invention.

FIG. 2 is a block diagram of a device configuration inside a communication processing apparatus according to the present invention.

FIG. 3 is a flowchart in which a control relationship from each processing unit is added to a flowchart showing an embodiment of a processing procedure according to the present invention.

FIG. 4 is a block diagram of a logical management space of a storage unit that stores data using I / O.

FIG. 5 is a block diagram showing an internal configuration in a storage unit according to the present invention.

FIG. 6 is a block diagram showing an internal configuration of an I / O processing optimization processor according to the present invention.

FIG. 7 is a diagram illustrating an application example of a communication system compatible client WS.

FIG. 8 is a diagram showing an application example of a communication system compatible server WS when used as a LAN adapter.

[Explanation of symbols]

31 ... System bus (data bus, I / O bus, instruction bus), 32 ... Input cache, 33 ... Cache data transfer management unit, 34 ... Storage unit management unit, 35 ... Cache / register management unit, 36 ... Register file, 37 ... A
LU data load management unit, 38 ... ALU (arithmetic logical operation unit), 39 ... Program instruction code determination unit, 40
... output cache, 41 ... child processor, 42 ... control bus.

Claims (20)

[Claims] 1. A virtual shared storage system having a function of collectively managing data in a buffer or a memory used in a system and a buffer or a memory used by a user space to share a storage means. 2. A virtual shared storage switching system characterized by a function of switching between a user space and a system space by a storage management unit, a program instruction distribution unit, and a virtual sharing management table. 3. A virtual sharing switching means having a function of distributing a program instruction of a system to data in a user area by controlling a storage means management section, a program instruction distribution means, and a virtual sharing management table. . 4. A virtual sharing switching means having a function of controlling a storage means management unit, a program instruction distribution means, and a virtual sharing management table to distribute a system program instruction to system data. 5. A processing program / instruction coexistence data management system characterized by the function of coexisting data stored in a system space and a system program instruction or a user program instruction. 6. An in-processor storage means management system characterized in that the data stored in the storage means is associated with a processing program, stored in an input cache or register file, and designated as an ALU input cache or register. 7. A program instruction distributing means, wherein a function of attaching a processing program instruction to each data is provided. 8. A cache / register management unit provided with a function of notifying information of empty cache / empty register to a program instruction distribution management means in which a processing program instruction is attached to each processing data. 9. An ALU data load management means having a function of notifying the ALU of a storage register number of data associated with a processing program instruction. 10. A cache data transfer management means having a function of loading data and a program instruction from an input cache to a register. 11. A cache data transfer management means having a function of loading data and program instructions from an output cache to a storage means. 12. A continuous program instruction judging method characterized in that when the program instruction of the previously loaded data with the program instruction is the same, the existing program instruction of the register or ALU is used without reloading the program instruction. 13. A continuous program having a function of using an existing program instruction of a register or an ALU without reloading the program instruction when the program instruction of the previously loaded data with the program instruction is the same. Command decision means. 14. An input-only cache for storing data before being processed by an ALU. 15. An output-only cache for storing processed data in an ALU. 16. A cache data transfer management unit having a function of transferring data from an output cache to a storage means or transferring data from a storage unit to an input cache. 17. A processor with an input / output cache provided with a data storage cache before processing and a data storage cache after processing. 18. A parent processor having a function of managing a processor with an input / output, associating an output result of the processor with each other, and performing a process without flowing the result on a bus as needed. 19. A relation of a parent processor, characterized in that a processor with an input / output is managed, an output result of the processor is associated with the output result, and the output result is processed as needed by a program without flowing to a bus. Data hierarchy processing method. 20. An I / O data batch transfer processing method, which is realized by any one of claims 1 to 19.