JPH065088A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce a power consumption on standby or in a data retention in an LSI-chip internal circuit which is constituted of a nonvolatile memory. CONSTITUTION:In an LSI-chip internal circuit which is constituted of a nonvolatile memory, a voltage-drop circuit on standby is controlled by an external control signal, and the feed of a power supply to the LSI-chip internal circuit is stopped completely. Alternatively, when a data retention is taken into consideration, the time in which a data retention state is kept is set in advance by the voltage-drop circuit and the external control signal. When the external control signal is changed, the voltage-drop circuit judges that the state of the LSI internal circuit is the data retention state, and the feed of the power supply to the LSI-chip internal circuit is reduced to about 4/5 of a power supply voltage VCC. After the sad set time has elapsed, the voltage-drop circuit judges that the state of the LSI internal circuit has been changed to a standby state, and the feed of the power supply to the LGI-chip internal circuit is stopped completely.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory, and is particularly effective for reducing the power consumption of the non-volatile memory in a standby state or a data retention state.

[0002]

2. Description of the Related Art FIG. 2 schematically shows a method of supplying a voltage to an internal circuit of an LSI chip constituted by a conventional nonvolatile memory. The power supply voltage V _CC is applied as an input voltage, and the power supply voltage V _CC is stepped up or down to write / read or erase data in / from the nonvolatile memory. At the time of writing / reading data, in order to speed up the internal circuit of the LSI chip, the power supply and the LSI in the LSI chip 1 are used.
A booster circuit is provided between the chip internal circuit and the circuit. Then, the booster circuit amplifies the power supply voltage V _CC to form a high voltage, which is supplied to the internal circuit of the LSI chip. Further, a step-down circuit is provided between the LSI chip internal circuit in the LSI chip 1 and the power supply in order to apply a negative voltage to the LSI chip internal circuit in order to erase the written data. . Then, the step-down circuit attenuates the power supply voltage V _CC to form a negative voltage, which is supplied to the internal circuit of the LSI chip. Such a step-up circuit and step-down circuit use the write enable signal WE as an external control signal.
B, output enable signal OEB, and chip enable signal CEB. In this way, data writing / reading or data erasing operations are performed. As another conventional technique, a voltage converter having the functions of the step-up circuit and step-down circuit is used to increase and decrease the power supply voltage V _CC during data writing / reading or data erasing.

FIG. 3 shows a timing chart of an external control signal of an LSI chip internal circuit composed of a non-volatile memory and a voltage to be supplied to the LSI chip internal circuit. When the chip select signal CEB is between time t _{0 and} t ₁ ,
When latched at Low, the internal supply voltage Vi becomes the same level as the power supply voltage V _CC , so that the LSI chip internal circuit configured by the non-volatile memory is activated. Then, the chip enable signal CEB
While BUSY time t ₂ ~t _3, it is latched into High, although the internal supply voltage Vi is set to 0V, after a predetermined time set in the timer, at time t _3, the internal supply voltage Vi
Is at the power supply voltage V _CC level. However, the step-down circuit operates at the time of erasing data, and the internal supply voltage Vi in the standby state is not controlled. Therefore, when a current is applied to the LSI chip for a long time, heat is generated from the resistance in the internal circuit of the LSI chip. By this, Sub threshold
ld current flows and the chip enable signal CEB goes high.
The internal supply voltage Vi rises after time t ₃ even in the state of being latched by h and in the standby state.
There is a problem that the power consumption increases when I is not operating. Here, the Sub thresh
The old current refers to a minute current flowing through the transistor when the voltage applied to the gate does not exceed the threshold voltage.

[0004]

SUMMARY OF THE INVENTION The present invention relates to an internal circuit of an LSI chip composed of a non-volatile memory, in order to solve the above problems, a step-down circuit and an external control signal are used during standby and during data retention. By controlling the power supply to the LSI chip internal circuit,
The purpose is to reduce power consumption during standby or data retention.

[0005]

In an LSI chip internal circuit composed of a non-volatile memory, a step-down circuit is controlled by an external control signal during standby to completely cut off power supply to the LSI chip internal circuit. . Alternatively, when the data retention is taken into consideration, the time for maintaining the data retention state is set in advance by the step-down circuit and the external control signal, and the step-down circuit changes the state of the LSI internal circuit to the data by the change of the external control signal. The retention state is determined, and the power supply to the LSI chip internal circuit is set to about _4/5 of the power supply voltage V _CC . Then, after the lapse of the set time, the step-down circuit determines that the state of the LSI internal circuit has been switched to the standby state, and completely cuts off the power supply to the LSI chip internal circuit.

[0006]

By controlling the voltage supply to the internal circuit of the LSI chip constituted by the non-volatile memory at the time of standby or data retention by the external control signal, the internal supply voltage at the time of standby becomes completely 0V. As a result, since the LSI is composed of a non-volatile memory, even if the internal supply voltage is completely cut off, the operation is not hindered, and the power consumption during standby can be reduced. Further, when considering the data retention time, by controlling the voltage supply to the LSI chip internal circuit by an external control signal,
The internal supply voltage to the LSI chip is cut to about 4/5 of the power supply voltage. Then, after a certain period of time, it is determined that the internal circuit of the LSI chip has switched to the standby state,
By setting the voltage supply to the chip internal circuit of the LSI to 0 V, the power consumption during data retention and standby can be significantly reduced.

[0007]

【Example】

(Embodiment 1) FIG. 1 shows an outline of a method of supplying a voltage to an LSI chip internal circuit constituted by a nonvolatile memory of the present invention in which power consumption during standby is reduced.
As in the conventional case, the step-down circuit is arranged between the power source and the LSI chip internal circuit in the LSI chip 1. The LSI chip internal circuit is composed of a nonvolatile memory. The above step-down circuit is
In order to reduce the power consumption when the LSI is not in the operating state, the start-up of the step-down circuit is controlled with the change of the chip enable signal CEB, the write enable signal WEB, and the output enable signal OEB as the external control signals in the standby mode. ing. The control of the output voltage by the step-down circuit can be realized by increasing the impedance in the step-down circuit by controlling the resistor in the step-down circuit. Then, during standby, the LSI
In order to completely cut off the current and voltage supplied to the chip internal circuit, the impedance in the step-down circuit is increased. As a result, the internal supply voltage to the LSI chip internal circuit becomes 0V. At this time, since the LSI internal circuit is composed of a non-volatile memory, it is possible to reduce the power consumption during standby without erasing the held data and without affecting the LSI operation itself. Further, as in the conventional case, when the step-down circuit has a function of applying a negative voltage when erasing the held data, it is necessary to separately provide a step-down circuit and apply the negative voltage as the power supply voltage. The same applies when the voltage converter is used in the step-down circuit. Although the step-down circuit is shown in the LSI chip in the figure, it can be arranged outside the LSI chip without any problem.

FIG. 4 shows an example of the step-down circuit of the present invention. Binary counter circuit in step-down circuit B. C. CLOC
K signal is input, and the binary counter B. C. It is possible to set switching of each mode by arbitrarily setting the number of stages. The binary counter circuit B. C. Is reset every time the chip enable signal CEB goes low, and if the low level is long, the binary counter B. C. Is not working. The operation of the step-down circuit in each mode will be described below.

(I) Operation Mode The low level of the chip enable signal CEB is input to the inverter circuit INV1. The High level of the output signal of the inverter circuit INV1 is the binary counter circuit B. C. N together with the low level of the output signal of
It is input to each node of the OR circuit NOR1. Further, the low level of the output signal of the NOR circuit NOR1 is NO.
The R circuit NOR2 is input to each node together with the high level of the output signal of the inverter circuit INV1. Then, the low level of the output signal of the NOR circuit NOR1 is input to the inverter circuit INV2. Further, the high level of the output signal of the inverter circuit INV2 is PM.
It is applied to the gate of the OS transistor Q3. On the other hand, P
Since the power supply voltage V _CC is applied to the source of the MOS transistor Q1 and the Low level is applied to the gate thereof, the PMOS transistor Q1 is turned on. Further, a voltage is applied to the source of the PMOS transistor Q2, and the low level of the chip enable signal is applied to the gate. Therefore, the PMOS transistor Q2 is also turned on, and a voltage is applied to the gate of the NMOS transistor Q6. In addition, a low level is applied to the gate of the PMOS transistor Q4 to turn it on. In this way, the PMOS transistors Q4,
A current flows through the NMOS transistor Q6, and the power supply voltage V _CC
The level voltage is output as the output voltage VOUT of the step-down circuit. In addition, the binary counter circuit B. C. L
Since the output signal of the ow level is applied to the gate of the NMOS transistor Q7, the NMOS transistor Q7 becomes O
The state becomes FF.

(Ii) Data retention mode The high level of the chip enable signal CEB is input to the inverter circuit INV1. Then, the Low level of the output signal of the inverter circuit INV1 indicates that the binary counter circuit B. C. N together with the low level of the output signal of
It is input to each node of the OR circuit NOR1. Further, the high level of the output signal of the NOR circuit NOR1 is N
The OR circuit NOR2 is input to each node together with the low level of the output signal of the inverter circuit INV1. Then, the high level of the output signal of the NOR circuit NOR1 is input to the inverter circuit INV2. Further, the low level of the output signal of the inverter circuit INV2 is PM.
It is applied to the gate of the OS transistor Q3. On the other hand, P
Since the power supply voltage V _CC is applied to the source of the MOS transistor Q1 and the Low level is applied to the gate thereof, the PMOS transistor Q1 is turned on. Further, a voltage is applied to the source of the PMOS transistor Q2, and the high level of the chip enable signal is applied to the gate. Therefore, the PMOS
The transistor Q2 is turned off. Since the low level of the output of the inverter circuit INV2 is applied to the gate of the PMOS transistor Q3, the PMOS transistor Q3 is turned on. Also, the PMOS transistor Q
A low level is applied to the gate of No. 4 to turn it on. Here, in order to speed up the rise of the output voltage, the output voltage from the step-down circuit is set to about 4 / 5V _CC . Therefore, the resistance R2 is set to have a resistance value about four times that of the resistance R1. Therefore, the PM
A voltage of 4 / 5V _CC is applied to the source of the OS transistor Q3, and the NMOS transistor Q6 is turned on via the PMOS transistor. In this way, P
A current flows through the MOS transistor Q4 and the NMOS transistor Q6, and the output voltage VOUT of the step-down circuit is reduced to about 4 /
It can be 5V _CC .

(Iii) Standby Mode The high level of the chip enable signal CEB is input to the inverter circuit INV1. Then, the Low level of the output signal of the inverter circuit INV1 indicates that the binary counter circuit B. C. Is input to each node of the NOR circuit NOR1 together with the High level of the output signal of the. Further, the low level of the output signal of the NOR circuit NOR1 is N
The OR circuit NOR2 is input to each node together with the low level of the output signal of the inverter circuit INV1. Then, the low level of the output signal of the NOR circuit NOR1 is input to the inverter circuit INV2. Further, the high level of the output signal of the inverter circuit INV2 is PM.
It is applied to the gate of the OS transistor Q3 to turn off the PMOS transistor Q3. On the other hand, a high level is applied to the gates of the PMOS transistors Q1 and Q4, and the PMOS transistors Q1 and Q4 are turned off.
It is said that Furthermore, the PMOS transistor Q2 is also off
Therefore, no voltage is applied to the gate of the NMOS transistor Q6. In addition, the binary counter circuit B. C. The high level of the output signal of is applied to the gate of the NMOS transistor Q7 to turn on the NMOS transistor Q7. The PMOS transistors Q2 and Q3 are turned off at the gate of the NMOS transistor Q6,
Since the NMOS transistor Q5 is turned on, no voltage is applied. In this way, by fixing the output voltage VOUT of the step-down circuit to 0V, it is possible to completely cut it.

FIG. 5 shows the voltage V to be supplied to the LSI chip internal circuit constituted by the external control signal and the non-volatile memory in the standby state of the LSI chip internal circuit of the present invention.
The timing chart with i is shown. The chip enable signal CEB is latched at Low during the time t _{0 to} t ₁ , so that the internal supply voltage Vi becomes the same level as V _CC , so that the LSI configured by the non-volatile memory.
The internal circuit is put into operation. Then, the chip enable signal CEB is latched at High during the time t _{2 to} t ₃ , and the step-down circuit determines that the LSI internal circuit is in the standby state. Then, the power supply voltage V _CC that is the input voltage of the step-down circuit is attenuated and the output is reduced to 0.
The voltage is set to V and the voltage supply to the internal circuit of the LSI chip is stopped. As described above, when a current is passed through the LSI chip for a long time, heat is generated from the resistance or the like in the internal circuit of the LSI chip, and thus the Sub threshold.
d Current is reduced. Therefore, even if the LSI chip internal circuit is in a standby state, the internal supply voltage Vi is V _CC.
It does not rise to the level, and the power consumption in the inactive state can be cut significantly. Here, although the chip enable signal CEB is described in the present embodiment, there is no problem even if external control signals such as the write enable signal WEB and the output enable signal are used.

A method of supplying a voltage to the internal circuit of the LSI chip constituted by the non-volatile memory when the power consumption during data retention is reduced will be described with reference to FIG. In this case, the data retention state time is preset in the step-down circuit, and the chip enable signal CEB and the write enable signal W as external control signals are set.
It is controlled by EB, output enable signal OEB and the like. As a result, the step-down circuit determines that the internal circuit of the LSI chip is in data retention, and the impedance in the step-down circuit is increased by controlling the resistance in the step-down circuit. In order not to make the rise of the voltage Vi difficult, it is set to drive the power supply voltage V _{CC at} a level of about 4/5 for a fixed time. The internal supply voltage Vi at the time of data retention is 1 / the power supply voltage V _CC
If the level is 2 or more, the same effect can be obtained even if the level is not about 4 / 5V _CC level. After a lapse of a certain time, the step-down circuit determines that the LSI chip internal circuit is in the standby state, and as in the first embodiment, the power consumption is completely cut off in the standby state and the current to the LSI chip internal circuit is reduced. In order to completely cut the voltage, the impedance in the step-down circuit is increased to increase the L
The internal supply voltage to the SI chip internal circuit is set to approximately 0V. At this time, since the LSI internal circuit is composed of a non-volatile memory, it does not erase the held data and does not affect the LSI operation itself, and consumes data during data retention and standby. Power consumption can be significantly reduced.

FIG. 6 shows a timing chart of the external control signal in the data retention state of the LSI chip internal circuit of the present invention and the voltage Vi to be supplied to the LSI chip internal circuit constituted by the nonvolatile memory. The chip enable signal CEB is latched at Low during the time t _{0 to} t ₁ , so that the internal supply voltage Vi becomes the same level as V _CC, and the LSI internal circuit configured by the nonvolatile memory becomes in the operating state. To be done. The state of the LSI chip internal circuit is judged to be during data retention by latching the chip enable signal CEB for a certain time t _{2 to} t ₃ High, and the impedance is increased by controlling the resistance in the step-down circuit. The above LSI
The voltage Vi and current supplied to the chip internal circuit are set to about 4/5 of the power supply voltage V _CC . Furthermore, if the chip enable signal CEB is High after a certain period of time, it is determined that the LSI chip internal circuit is in the standby state, and the impedance of the step-down circuit is set high enough to be completely cut. Then, the internal supply voltage Vi is set to 0V, the power supply voltage V _CC as an input voltage is attenuated to set the output voltage to 0V, and the voltage supply to the LSI chip internal circuit is stopped. Therefore, by causing a current to flow through the LSI chip for a long time, the Sub threshold current is reduced when heat is generated from the resistance in the internal circuit of the LSI chip or when the temperature outside the LSI chip is high, and the chip enable signal is reduced. CEB is no longer latched High. Therefore, the internal supply voltage Vi does not rise when the LSI internal circuit is in the standby state, and the power consumption in the non-operating state can be significantly reduced. Although the chip enable signal CEB is described in this embodiment, the write enable signal W
There is no problem even if external control signals such as EB and output enable signal are used.

[0015]

The LS constructed by the non-volatile memory
In I, the power consumption during standby or during data retention can be significantly reduced without damaging the data latched in the memory.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a method of supplying a voltage to an LSI chip internal circuit configured by a nonvolatile memory with reduced power consumption during standby according to the present invention.

FIG. 2 is an LS configured by a conventional nonvolatile memory
An outline of a method for supplying a voltage to an I-chip internal circuit.

FIG. 3 is a timing chart of an external control signal of an LSI chip internal circuit configured by a non-volatile memory and a voltage Vi to be supplied to the LSI chip internal circuit.

FIG. 4 shows an example of a step-down circuit according to the present invention.

FIG. 5 is a timing chart of an external control signal in a standby state of the LSI chip internal circuit of the present invention and a voltage Vi to be supplied to the LSI chip internal circuit configured by a nonvolatile memory.

FIG. 6 is a diagram showing a voltage Vi to be supplied to an LSI chip internal circuit configured by an external control signal and a non-volatile memory in a data retention state of the LSI chip internal circuit of the present invention.
And the timing chart.

[Explanation of symbols]

1 ... LSI chip, R1 to R2 ... Resistor, Q1 to Q
4 ... PMOS transistor, Q5-Q7 ... NMOS
Transistor, INV1 to INV3 ... Inverter circuit, NOR1 to NOR2 ... NOR circuit, NAND1 ...
..NAND circuits and B.I. C. .... Binary counter

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Sato 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (3)

[Claims] 1. A semiconductor integrated circuit having a step-down circuit and a non-volatile memory to which the output voltage of the step-down circuit is supplied. By supplying an external control signal to the step-down circuit during standby, the output voltage of the step-down circuit is reduced. A semiconductor integrated circuit having a voltage of 0V. 2. A semiconductor integrated circuit including a step-down circuit having a counter circuit for counting the time of an external control signal, and a non-volatile memory to which an output voltage of the step-down circuit is supplied. The signal is input,
After the level of the external control signal changes, the data retention mode is set for a predetermined time, the output voltage of the step-down circuit is set to a predetermined voltage larger than half the power supply voltage, and after the predetermined time, the step-down circuit is set to the standby mode. A semiconductor integrated circuit, wherein the output voltage is set to 0V. 3. The semiconductor integrated circuit according to claim 1, wherein the external control signal is a chip enable signal.