JPH0650842B2 - Wireless telemeter device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a wireless telemeter device, which is particularly suitable for transmitting DC signals.

The carrier wave drifts due to changes in the external environment such as temperature. For example, in the case of FM modulation or PM modulation, frequency or phase drift may occur, and in the case of pulse modulation, pulse duty, frequency or phase drift may occur. An offset is added to the DC signal reproduced by receiving and demodulating the carrier wave containing the modulated DC signal due to the above drift of the carrier wave, and the reference level of the original DC signal, for example, the zero potential level is accurately measured. It is difficult to reproduce.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a wireless telemeter device that correctly reproduces the original reference level of a DC signal after reception and demodulation, for example, zero potential level, without being affected by changes in the external environment.

A wireless telemeter device according to the present invention comprises a transmitting device and a receiving device. The transmitting device synthesizes a pulse generating circuit for generating a pulse signal, a signal to be transmitted and the pulse signal, and The receiving device includes a demodulation circuit that demodulates the received signal and a demodulation circuit that demodulates the received signal. Clamp circuit that shifts the level of the demodulated signal so that the peak value of the pulse signal included in the output signal matches the reference level, and a low-pass filter that removes the pulse signal from the output signal of the clamp circuit Is characterized by.

The reference level is preferably the ground level (zero potential). The peak value is the minimum or maximum level of the pulse signal.

FM modulation is preferable as the modulation method, but various methods such as PM modulation and analog pulse modulation can be adopted. Electromagnetic waves, light, and other media can be used for signal transmission.

According to the present invention, a pulse signal is combined with a signal to be transmitted in order to clarify a reference level of a signal to be transmitted, for example, a ground level, and after receiving and demodulating, the demodulated signal is clamped by a clamp circuit to obtain a reference level. Is reproduced, the reference level of the original signal to be transmitted can be reproduced correctly.

Description of Embodiments (1) Overview of optical wireless AE telemeter device Tool wear, breakage and other abnormalities in machine tools are monitored using acoustic emission (hereinafter referred to as AE) generated during cutting and breakage. ， There is a system to detect automatically. The optical wireless AE telemeter device
In such a system, the specific frequency component of the AE signal obtained from the AE sensor is modulated and transmitted in the form of an optical signal from the transmitter, and this is received and demodulated at the receiver side to obtain the original specific frequency component. Is to be reproduced.

FIG. 1 shows the outline of the electrical configuration of the optical wireless AE telemeter device, and FIG. 2 shows the waveform of the output signal of each block in FIG.

An AE sensor 11 is arranged near the tool or work of the machine tool. AE signal a output from the AE sensor 11
Is sent to the narrow band pass filter 12 having an amplifying function. A
In the power spectrum of the E signal, it is known from many experimental results that a peak appears around 50 KHz during normal cutting and a peak appears around 100 to 300 KHz during tool wear and breakage. Filter 12 is 100-300K
It has a center frequency near Hz. In this way, the frequency component b representing the presence or absence and the degree of abnormality of the tool passes through the filter 12 and is input to the envelope detection circuit 13. The detection circuit 13 rectifies and amplifies the signal b, and further takes the envelope thereof. The waveform of the output signal c of the detection circuit 13 contains all the information necessary for diagnosing the abnormality of the tool.

The pulse oscillating circuit 14 generates a pulse d having a low frequency (for example, about 100 Hz) so as not to destroy the information contained in the waveform of the signal c and having a pulse width similarly considered. This pulse d is combined with the signal c in the synthesis circuit 15.
To enter. The synthesis circuit 15 is turned on by the pulse signal d,
It is a kind of switching circuit controlled to be turned off, and the signal c
It functions to drop the envelope represented by to zero level during the pulse width of the pulse d. This clarifies the zero level of the signal c.

The output signal e of the synthesizing circuit 15 is frequency-modulated in the FM modulating circuit 16 using a carrier having an appropriate frequency, and is input to the light emitting diode and its driving circuit 17. An optical signal representing a carrier wave modulated by the signal e is emitted from the light emitting diode into the air.

The transmitter 10 is composed of the circuits 12 to 17 described above, and these circuits are powered by a battery, for example, a lithium battery.

When a plurality of AE sensors are provided, a transmitter 10 is prepared for each AE sensor 11. The frequencies of the carrier waves in the plurality of transmitters 10 are different from each other.

The device on the receiving side is composed of a plurality of receiving heads 21 and a receiver 20 which processes received signals from these receiving heads 21. The receiving head 21 includes a photodiode array 22 that receives an optical signal transmitted from the light emitting diode 17 and converts the optical signal into an electric signal, and an amplifier circuit 23 for the output signal of the photodiode array 22. The reception signals of the plurality of reception heads 21 are added by the addition circuit 24 of the receiver 20. When optical signals from a plurality of transmitters 10 using carrier waves having mutually different frequencies are simultaneously received, the output signals of the adder circuit 24 are converted to intermediate frequencies by the intermediate frequency conversion circuit 25, respectively. , The transmission signals of the plurality of transmitters 10 are separated from each other.

Each of the separated reception signals is demodulated by the frequency demodulation circuit 26. When the carrier frequency is drifting due to a temperature change or the like, an offset is added to the demodulated signal f, and its zero level may not always match the zero level of the signal c representing the envelope. The zero level of the signal c is clarified as the lowest peak value of the pulse component, as can be seen from the signal e. Therefore, the clamp circuit 27 clamps (level shifts) the signal f so that the peak (minimum level) of the pulse included in the demodulated signal f matches the zero level of the receiver 20. In this way, the zero level of the envelope signal is correctly reproduced. The low-pass filter 28 having an amplifying function removes the pulse component representing the zero level from the clamped signal g, and the envelope signal c is reproduced as the signal h.

As described above, the waveform of the envelope signal c contains all the information necessary for diagnosing the abnormality of the tool, and this waveform must be reproduced correctly on the receiver 20 side.
However, the DC component may be added to the demodulated signal f due to the frequency drift in the carrier wave. In the synthesizing circuit 15, the pulse signal d for clarifying the zero level is synthesized with the envelope signal c, and after demodulation, the signal f is clamped by the clamp circuit 27 to reproduce the zero level, so that the amplitude of the envelope signal is correct. Reproduced.

With this configuration, when demodulation is performed using a PLL (Phase Locked Loop) in FM modulation, for example, the frequency of the demodulated wave signal is deviated from the self-oscillation frequency of the voltage (current) control oscillator circuit. However, the adjustment is not necessary and the modulation / demodulation circuit does not need to be particularly precise.

(2) Arrangement of transmitter and receiving head When the AE sensor 11 and the transmitter 10 are attached to a moving object such as a robot arm, or when there is an obstacle in the optical path between the transmitter 10 and the receiving head 21. If there is a possibility of intrusion, the transmitter 10 and the receiving head 21 or the receiver
Optical communication with 20 is blocked. An arrangement for coping with this is shown in FIGS. 3 and 4.

FIG. 3 shows an example in which a plurality of receiving heads 21 are arranged to accommodate one moving transmitter 10 (including the AE sensor 11). The transmitter 10 moves from the position P ₁ to the positions P ₂ and P ₃ as shown by the broken line. A plurality of, for example, three receiving heads 21 are provided so that the optical signal from the moving transmitter 10 can be received at any position of the transmitter 10. These receiving heads 21 are receivers with coaxial cables
It is connected to 20 and the reception signal of the reception head 21 is the receiver
After being added by 20 adder circuits 24, they are sent to a demodulation circuit (not shown in FIG. 3).

The reception head 21 has a reception directivity of an appropriate angle.
Since the reception signals of the plurality of reception heads 21 are added by the addition circuit 24, if at least one reception head 21 receives the transmission optical signal with sufficient intensity (SN ratio), the reception signals are normally demodulated. It Transmitter 10 and either receiving head
Even if there is an obstacle 18 between it and 21, there is no problem because another receiving head 21 receives the transmitted optical signal. Transmitter 10
If the transmitter 10 moves linearly, it suffices to arrange a plurality of receiving heads 21 in a linear manner.
21 will be placed. Of course, the number of receiving heads 21 is selected as needed.

FIG. 4 shows a case where a plurality of transmitters 10 having different carrier frequencies for FM modulation are provided.
The plurality of receiving heads 21 are arranged so that at least one receiving head 21 can receive each of the optical signals transmitted from the plurality of transmitters 10. Transmitter 10 and receiving head
21 does not have to correspond to 1: 1, and three receiving heads 21 can receive optical signals from five transmitters 10 as shown in the figure. Similar to the receiver 20 shown in FIG. 1, a number of intermediate frequency conversion circuits 25 equal to the number of transmitters 10 are required.

When multiple transmitters 10 are moved, these transmitters
The receiving head 21 may be arranged so as to be able to receive the optical signals from each of the 10 moving ranges.

The adder circuit in FIGS. 3 and 4 may simply add a plurality of input signals, and is realized by, for example, a circuit including an operational amplifier, its feedback resistance, and an input resistance equal to the number of input signals.

(3) Envelope detection circuit (1) An example of a concrete configuration of the envelope detection circuit 13 is shown in FIG. A single output differential amplifier circuit is composed of two npn transistors T ₁₁ and T ₁₂ having the same characteristics, pnp transistors T ₁₃ and T ₁₄ forming a current mirror, and a constant current source 31. An input signal Vin (in charge of the signal b in FIG. 1) is input to one input terminal of this differential amplifier circuit. A resistor R ₁₁ is connected between this input terminal and ground. The output terminal of the differential amplifier circuit has an np for amplification.
The n-transistor T ₁₅ is connected, and its emitter is connected to the other input terminal of the differential amplifier circuit, thereby forming a negative feedback amplifier circuit. Resistor R ₁₃ between the collector and the supply voltage + V of the transistor T ₁₅ is, capacitor C ₁₁ between the same collector and ground are connected, respectively, and the resistors R ₁₃ and capacitor C ₁₁ is a low-pass filter ( Smoothing circuit). The voltage at the connection point P _d between the resistor R ₁₃ and the capacitor C ₁₁ becomes the output voltage V _out .
A resistor R ₁₂ is provided between the emitter of the transistor T ₁₅ and the ground.
Are connected.

FIG. 6 shows an equivalent circuit in which a part of the circuit shown in FIG. 5 is represented by using the h parameter. Points corresponding to the connection points P _{a to} P _d in FIG. 5 are shown in FIG. 6 using the same reference numerals. If the base potential of the transistor T ₁₂ (emitter potential of the transistor T ₁₅ ) (point P _b ) is V _b ,
The following equation holds. Ib is a base current.

V _in −V _b = 2h _ie · I _b ... (1) V _b = R ₁₂ · 2h _fe ² · I _b ... (2) Since the base current I _b is very small, the right side of the first equation is It can be considered to be almost zero, and V _in = V _b (3) holds.

FIG. 7 shows the input voltage signal V _in and the voltage V appearing at the point P _b.
The waveforms of _b and the output signal V _out are shown. When the input voltage V _in is positive with respect to the ground potential, the emitter potential V _b of the output stage transistor T ₁₅ is approximately equal to the input voltage V _in as described above. Since the emitter potential of the transistor T ₁₅ is pulled in the negative direction when the input voltage V _in is negative (the current in the direction flowing through a resistor R ₁₂ to the emitter of the transistor T ₁₅ is about to flow) transistor T ₁₅ It becomes cut off. Transistor T ₁₅ operates only when the input voltage V _in is positive, which results _in half-wave rectification. Since the resistor R ₁₃ and the capacitor C ₁₁ form a low pass filter, the envelope detection of the input signal Vin is performed by this circuit. Also the 6th
In the figure, it can be considered that 2h _fe ² · I _b >> I _b, and the resistance R
_The current flowing through ₁₂ is substantially equal to the current flowing through the parallel circuit (R ₁₃ // C ₁₁ ) of the resistor R ₁₃ and the capacitor C ₁₁ . In the low frequency band _{V out / V in ≒ V out} / V b = -R 13 / R 12 ··· (4) is satisfied, the envelope of the input signal V _in is -R ₁₃ / R ₁₂
Doubled.

In this way, the circuit of FIG. 5 has three functions of rectification, envelope detection and amplification.

FIG. 8 shows transistors T _{11 to} T in the circuit of FIG.
A modified example in which the differential amplification circuit consisting of ₁₄ is replaced by the operational amplification unit OP ₁ is shown. The operation of this circuit is the same as that described above.

(4) Envelope detection circuit (No. 2) In the circuit of FIG. 5, when the input voltage V _in is negative, the base potential V _b of the transistor T ₁₂ becomes negative. For the transistor T ₁₅ is cut off, it crowded current flows through the base resistor R12 of transistor T12, thereby the transistor T12 becomes saturated. Transistor T ₁₂
Saturation slows its operation. Therefore, it can not follow with respect to particularly high frequency of the input signal V _in, an envelope detection characteristics (linearity) is deteriorated.

As a countermeasure to this, when a current Komu flows through resistor R ₁₂ to the base of the transistor T _12, it is sufficient to flow accordingly also the collector current of transistor T _12. A circuit that realizes this concept is the circuit shown in FIG. 9, the same parts as those shown in FIG. 5 are designated by the same reference numerals.

In FIG. 9, two n's are placed between the power supply voltages + V and -V.
The pn transistors T ₁₇ and T ₂₀ are connected. Another transistor T ₁₆ is connected between the emitter of one transistor T _{17 and} the collector of the transistor T ₁₂ ,
The base of this transistor T ₁₆ is connected to its collector. Is constituted by the resistors R14 and the two transistors T _18, T ₁₉ is connected between the bias circuit + V supply and ground of the transistor T _17, the voltage drop at the two transistors T _18, T ₁₉ is the base of the transistor T ₁₇ Is being applied to. The transistor T ₂₀ constitutes a constant current source, and the voltage divided by the resistors R ₁₅ and R ₁₆ is applied to its base.

When the input voltage V _in is positive, the transistor T ₁₆ is in a cutoff state. Constant current flows through the transistor T _17, T _20.

When the input voltage V _in is negative and the collector potential of the transistor T ₁₂ decreases and approaches the ground level, the transistor T ₁₆ becomes conductive, a current flows through the transistors T ₁₇ and T ₁₆ and into the transistor T ₁₂ , and the transistor T ₁₂ is turned on. Saturation of T ₁₂ is prevented.

In this way, the high speed operation of the circuit of FIG. 9 is ensured.

Whether the transistor T ₁₂ is saturated also depends on the current capacity of the constant current source 31. If the current capacity of the constant current source 31 is large, it may be possible to flow the collector current to the input voltage V _in does not reach the transistor T ₁₂ is saturated even flows current to the base of the negative when the transistor T12. When the current capacity of the constant current source 31 is small, the transistor T ₁₂ is more likely to be saturated. However, even if that is the case, since the saturation of the transistor T ₁₂ is prevented by the function of the circuit including the transistors T _{16 to} T ₂₀ as described above, a circuit with low current consumption, high speed, and high stability can be obtained. Will be realized.

(5) Synthesizing Circuit FIG. 10 shows a specific example of the synthesizing circuit 15 in FIG. In this circuit, the output signal c of the envelope detection circuit 13 is given as the input signal I _i , and the output pulse signal d of the pulse oscillation circuit 14 is given as the voltage signal V _c . The output signal e is the output current I _o .

The two pnp transistors T ₂₁ and T _{22 form} a current mirror, and the input signal I _i is applied to one transistor T ₂₁ . A current equal to the input signal I _i flows through the other transistor T ₂₂ . The emitters of the two pnp transistors T ₂₃ and T ₂₄ are connected to the collector of the other transistor T22. The collector of the transistor T ₂₃ is connected to the output terminal. The base of the transistor T ₂₃ is grounded. The collector of the transistor T ₂₄ has a transistor T ₂₅ acting as a constant current source.
Are connected. The pulse signal V _c is applied to the base of the transistor T ₂₄ . Transistor T ₂₅ is fixedly biased by resistors R ₂₁ and R ₂₂ .

FIG. 11 shows the waveforms of the input current I _i , the pulse voltage V _c and the output current I _o .

When the pulse voltage signal V _c has a positive level, the transistor T ₂₄
Is off. Input current I _i flowing through transistor T ₂₂
A current equal to flows into the transistor T ₂₃ and becomes an output current. That is, I _i = I _o . When the signal V _c becomes negative, the transistor T ₂₄ turns on, and the current flowing through the transistor T ₂₂ flows through the transistors T ₂₄ and T ₂₅ , so that the transistor T ₂₃ turns off. Therefore, the output current is I _o = 0.

In this way, when the signal V _c is at the negative level, the output current I _o which becomes the zero level is obtained. In FIG. 2, the pulse signal d is a DC pulse, whereas the pulse signal V _{c in} FIG. 11 is an AC pulse, but there is no problem at all.
In short, it is sufficient that the combined signal e or I _o contains a pulse-shaped signal component indicating a reference level (zero level).

(6) Light emitting diode drive circuit FIG. 12 shows a light emitting diode drive circuit (corresponding to the circuit 17 in FIG. 1). The output signal of the modulation circuit 16 of FIG. ₁ is given by the input current I ₁ , and the drive current of the light emitting diode 33 is I ₂ .

The pnp transistors T ₃₁ and T _{32 form} a current mirror. When the input current I ₁ is applied to one transistor T ₃₁ , the current I of the same value is applied to the other transistor T _32.
1 flows.

Two npn transistors T ₃₃ and T ₃₄ having the same characteristics, and pnp transistors T ₃₅ and T forming a current mirror.
_A single output differential amplification circuit is constituted by ₃₆ and the current source 32. The collector of the transistor T ₃₂ is connected to the base of the transistor T ₃₃ . The base of the transistor T ₃₇ is connected to the output side of the differential amplification circuit, and the emitter of the transistor T ₃₇ is connected to the base of the transistor T ₃₄ . Furthermore, one end has transistors T ₃₃ and T _34.
The other ends of the resistors R ₃₁ and R ₃₂ , which are respectively connected to the bases of, are connected to the anode of the light emitting diode 33. These transistors T ₃₇ and resistors R ₃₁ and R ₃₂ are added to form a negative feedback amplification circuit.

When the current I ₁ flowing through the transistor T ₃₂ and the resistor R ₃₁ increases, the base potential of the transistor T ₃₃ increases, so that the current flowing through the transistor T ₃₃ increases. Due to the action of the current mirror composed of the transistors T ₃₅ and T ₃₆ , the current flowing through the transistor T ₃₆ also increases, the base current of the transistor T ₃₇ also increases, and the current I ₃ flowing through the transistor T ₃₇ also increases. However, since the increase of the current I ₃ increases the collector current of the transistor T ₃₄ , the base current of the transistor T 37 decreases and the current I ₃ increases.
Also decreases.

In the circuit of FIG. 12, the following equation holds.

R ₃₁ · I ₁ = R ₃₂ · I ₃ (5) I ₂ = I ₁ + I ₃ (6) Therefore, the current amplification rate is given by the following equation.

I ₂ / I ₁ = 1 + (R ₃₁ / R ₃₂ ) ... (7) As can be seen from the equation (7), the current amplification factor is the resistance R ₃₁ and R _32.
It is determined only by the value of and is hardly affected by the transistor characteristics. By using resistors R ₃₁ and R ₃₂ having a small temperature coefficient, it is possible to reduce the influence of changes in temperature and the like. The current amplification rate I ₂ / I ₁ is kept constant even if the transistor characteristics, operating point, etc. change due to temperature changes and power supply voltage changes.

Further, since it is a negative feedback circuit, even if noise is added to the current I ₃ , for example, the above-mentioned amplification circuit works so as to cancel the fluctuation due to the noise, so that the amplification with noise resistance is possible.

In this way, it is possible to suppress the influence on the brightness of the light emitting element such as the light emitting diode due to the disturbance such as the electric noise, the temperature and the fluctuation of the power supply voltage, and to improve the SN ratio in the optical communication.

Further, since the current amplification rate is determined by the two resistance values as described above, it is possible to easily perform the brightness setting according to the communication distance, that is, the adjustment of the drive current I ₂ so that the current consumption is reduced as much as possible. As mentioned above, the transmitter is battery powered. In order to extend the battery replacement period as long as possible, it is necessary to reduce the current consumption of the transmitter as much as possible. On the other hand, the brightness of the light emitting diode must be set according to the communication distance. If the drive current of the light emitting diode can be adjusted within a range that satisfies the required SN ratio, it is possible to prevent the consumption current from being wasted.

FIG. 13 shows a modification of the light emitting diode drive circuit. The differential amplifier circuit including the transistors T _{33 to} T ₃₆ shown in FIG. 12 is replaced by the operational amplifier OP ₂ . The operation is the same as that shown in FIG.

In FIG. 12 and FIG. 13, a plurality of light emitting diodes 33 connected in series are shown.
It may be one light emitting diode.

(7) Clamp Circuit (No. 1) FIG. 14 shows an example of a concrete configuration of the clamp circuit (FIG. 1, reference numeral 27). The input signal V _{in in} FIG. 14 corresponds to the signal f in FIG. 1, and the output signal V _out corresponds to the signal g. The voltage signal source 34 has a reference level ± V for clamping.
_R is given, and this reference level is set to zero in the embodiment of FIG. The waveforms of the input and output signals V _in and V _{out in} the circuit of FIG. 14 are shown in FIG.

This clamp circuit includes an operational amplifier OP ₃ . An input terminal is connected to the inverting input side of the operational amplifier OP ₃ via a clamp capacitor C _41, and the inverting input side is grounded via a resistor R ₄₁ . A reference voltage source 34 is connected to the non-inverting input side of the operational amplifier OP ₃ . The output of the operational amplifier OP ₃ is fed back to the inverting input side via the diode D _1, and the inverting input side is connected to the output terminal.

Charge stored in the capacitor C41 is zero, also the zero potential difference between both ends of the capacitor C _41. At this time V _out
= V _in . V _out> operation up because it is V _R width device OP
The output of ₃ becomes the voltage V _R or less, and no current flows through the diode D ₁ .

At time t ₁ , the input signal V _in falls below the voltage V _{R and} reaches its bottom peak. Since the potential difference between both ends of the capacitor C ₄₁ is zero, V _out = V _in <V _R , and the operational amplifier OP
The output voltage of ₃ becomes V _R or more and the diode D ₁ becomes conductive. The capacitor C ₄₁ is charged by the current flowing through the diode D ₁ , and the output V _out rapidly rises. V _out
= V _R , the output of the operational amplifier OP ₃ falls below the voltage V _R , so that the diode D ₁ is turned off and the charging of the capacitor C ₄₁ is stopped. Therefore, the output voltage V _out
It is clamped to the reference level V _R.

When the input voltage V _in rises from its bottom level to exceed the level V _R , the output voltage V _out rises following this, V
_out = V _in .

The input voltage Vin first falls to the bottom peak (time t ₁ ).
After that, from the time when the diode D ₁ changes from on to off to the time t _{2 when} it falls to the next bottom peak, the diode D ₁ is held in the off state, and the capacitor C
The charge on ₄₁ is slowly discharged through resistor R ₄₁ . The change in the potential difference between both ends of the capacitor C ₄₁ due to the discharge during this period is ΔV _q .

At time t _{2 when the} input signal V _in falls below the reference level V _R again, the potential of the capacitor C ₄₁ is Δ due to discharge.
Because they reduced by V _q, it becomes V _out = V _R -ΔV _q. Since V _out <V _R , the diode D ₁ becomes conductive again, and the capacitor C ₄₁ is charged until V _out = V _R.

In this way, the bottom peak of the input signal V _in is always clamped to the reference level V _R.

(8) Clamp circuit (2) In the circuit of FIG. 14, the difference (variation) between the lowest peak value of the input signal V _in at time t ₁ and the lowest peak value of the signal at time t ₂ is + ΔV _q. If: V _out = V
The clamping action of R is normally achieved.

In the normal use of the AE telemeter device, the above-mentioned normal clamping operation is surely performed.

However, if some kind of abnormality occurs and the minimum peak value of the input signal V _in rises, the clamp action may be hindered. For example, as shown in FIG. 15, it is assumed that the bottom peak value of the input signal V _in at time t ₃ has changed by + ΔV as compared with that at time t ₂ . If that is clamped to V _out = V _R when clamping the last (time t _2), the output at time t ₃ becomes _{V out = V R -ΔV q +} ΔV. If ΔV> ΔV _q , V _out > V _R , the diode D ₁ is kept in the off state, and V _out is no longer clamped to the reference level V _R.

As described above, the circuit shown in FIG. 14 may be out of the clamp state when the peak value of the input signal V _in fluctuates significantly. The purpose of the clamp circuit 27 shown in FIG. 1 is to reproduce the reference level of the DC signal by matching the peak value of the input signal with the reference level (for example, zero potential), so that the clamp circuit operates normally. If it does not operate, the reference level of the DC signal will be lost, and it is necessary to immediately return to the clamped state.

FIG. 16 shows a clamp circuit modified to overcome the above-mentioned problems. In this figure, the same parts as those shown in FIG. 14 are designated by the same reference numerals.

A voltage source 35 that generates a voltage V _L that determines the upper limit level, and an operational amplifier OP ₄ as a comparator in which the output terminals of the voltage source 35 and the output V _out are connected to the inverting input side and the non-inverting input side, respectively. And a resistor R ₄₁ connected in parallel with the operational amplifier OP
A switching transistor T _41, which is on / off controlled by the output signal of ₄ , is added. This added circuit, when the output V _out is equal to or higher than the level V _L to conduct the transistors T _41, by discharging the electric charge of the capacitor C ₄₁ through the transistor T _41, the output V
It works so that _out does not rise above the level V _L.

FIG. 17 shows input / output signals and diodes of FIG.
The state of the transistor is shown. The operations at times t ₁₁ and t ₁₂ are the same as those at times t ₁ and t ₂ in FIG.

Output voltage V at time t ₁₃ due to some abnormality
_{When out} exceeds the upper limit level V _L , this is an operational amplifier OP
Detected by ₄ , transistor T ₄₁ is turned on. This discharges the electric charge of the capacitor C ₄₁ , so that the output V _out is maintained at the level V _L. Input signal V _in
If the lowest peak appears at and the voltage drops, the output voltage _{Vout naturally} drops following this.

When the input voltage V _in starts to drop near time t ₁₄ , the output voltage V _out also drops accordingly. At this time, the transistor T ₄₁ is turned off, and the electric charge of the capacitor C ₄₁ returns to the original state of being slowly discharged through the resistor R ₄₁ .

At time t ₁₅ , when the bottom peak appears in the input signal V _in , the output voltage V _out becomes lower than the reference level VR following the bottom peak. At this time, the output of the arithmetic increase width unit OP ₃ is diode D ₁ is conducting rise, the output V _out capacitor C ₄₁ is charged is clamped to the reference level V _R.

As described above, even if the level of the input signal rises abnormally, the output signal can return to a state of being clamped to quickly level V _R. If, as in the case where the added circuit described above is not present is shown by a broken line in FIG. 17, the output signal V _out rises to follow the input signal V _in, the output also reached the time t ₁₅ V _out the reference level V _R is
That is all. The electric charge of the capacitor C ₄₁ is slowly discharged through the resistor R ₄₁ , and the output V _out becomes the level V _R.
It will remain unclamped until the following:

When the output signal V _out exceeds the upper limit level V _L , the output signal V _out is cut at the level V _L and the faithful signal waveform is not partially reproduced, but the output signal V _out
Exceeds the level V _L when some abnormality occurs, so that the wireless telemeter device is not adversely affected.

The circuit of FIG. 16 clamps the bottom peak of the input signal to the reference potential. In this type of circuit, it is detected that the output voltage exceeds the upper limit level (higher than the reference level), the clamp capacitor is forcibly discharged based on this detection, and the output voltage rises above the upper limit level. The charge of the clamp capacitor is controlled so as not to exceed the limit.

In the type of circuit that clamps the highest peak of the input signal to the reference level, it detects when the output voltage falls below the lower limit level (lower than the reference level) and clamps.
It suffices to forcibly charge the capacitor and control the charge of the clamp capacitor so that the output potential does not fall below the above lower limit level.

(9) Clamp circuit (3) FIG. 18 shows a modified example of the clamp circuit. The reference level of this circuit is set to the ground level.

In this figure, transistors T ₅₇ , T ₅₈ , T ₅₉ ,
The T ₆₀ , T ₆₃ and the current source 36 form a differential amplification circuit. A transistor T ₆₁ connected in series with the transistor T ₆₃ and another transistor T ₆₂ constitute a current mirror of the output stage, and an output resistor R ₅₃ is connected to the transistor T ₆₂ . The feedback element that supplies the clamp capacitor C ₅₁ with charge for clamping is transistor T ₅₄ . The transistor T ₅₄ is biased by a circuit composed of the transistor T ₅₁ and the resistor R _54, and the emitter of the transistor T ₅₄ is the transistor T _58.
Is connected to the collector (point Q _c ). The transistor T ₅₄ supplies the electric charge to the capacitor C ₅₁ via the current mirror composed of the transistors T ₅₂ and T ₅₃ . The transistor T ₅₆ is connected to the emitter of the transistor T ₅₄ . The switching element that controls to discharge the electric charge of the capacitor C ₅₁ when the input signal V _in rises abnormally is the transistor T ₅₅ . Voltage dividing resistors R ₅₁ and R ₅₂ are connected between the base of the transistor T ₅₈ (point Q _b ) and the ground, and the voltage at this connection point (point Qd) is applied to the transistors T ₅₅ and T ₅₆ .

FIG. 19 shows the voltage waveform at each point and the states of the transistors T ₅₄ and T ₅₅ in the circuit of FIG.

It is assumed that a certain amount of electric charge is stored in the capacitor C ₅₁ before time t ₂₁ . There is a potential difference between the input signal V _in and the base potential of the transistor T ₅₇ (point Q _a ) according to the amount of charge stored in the capacitor C ₅₁ . The charge on the capacitor C ₅₁ is slowly discharged as the base current of the transistor T ₅₇ . Transistors T _{57 to} T
_{Since 60} and T ₆₃ form the negative feedback amplification circuit as described above, the potentials at points Q _a and Q _b are equal. If the potential at the point Q _a is positive, a certain value of the current I ₁₁ is applied to the transistors T ₆₁ and T _63.
It flows through the transistors T _61, T ₆₂ transistors T ₆₂ to the resistor R ₅₃ by the action of the current mirror consisting of
Current I ₁₁ flows through the positive output voltage V _out = I ₁₁
R ₅₃ appears at the output terminal.

When the input voltage Vin becomes the bottommost peak value at time t21, the potential of the point Q _a is negative by the charge stored in the capacitor C _51. Since the potential at the point Q _c changes according to that at the point Q _a , the potential at the point Q _c also drops and the transistor T ₅₄ becomes conductive. At this time, the transistor T ₅₆ is off. As a result, the current I ₁₂ flows through the transistors T ₅₃ and T ₅₄ , and the capacitor C ₅₁ is charged through the transistor T ₅₂ by the current mirror composed of the transistors T ₅₂ and T ₅₃ . Thereby also increases the potential of the point Q potential of _a is increased Q _c, the transistor T ₅₄ is turned off when the potential of the point Q _a is zero potential (ground potential). Therefore, I ₁₂ = 0 and the charging of the capacitor C ₅₁ is stopped. The potentials at the points Q _a and Q _b are both zero potential, the transistor T ₆₃ is in a cutoff state, and the output voltage V _out is also held at zero potential.

Input voltage V _in is in the period from the bottommost peak next to the time t22 that the bottom-most peak is shifted visit After up standing, the output voltage V _out varies according to the input voltage V _in. Capacitor C51 during which supplies the base current of the transistor T _57, to discharge slowly. Therefore, when the input signal V _in reaches the bottom peak again at the time t ₂₂ , the potential at the point Q _a becomes a negative potential because it was clamped to the zero potential at the time t ₂₁ . As a result, the output voltage V _out is clamped to zero potential again.

When the potential at the point Q _a rises (time t ₂₃ ) due to the rapid level rise of the input voltage V _in , the potential at the point Q _b rises and the potential at the point Q _d also rises. The potential at the point Q _d is V of the transistor T ₅₅ .
_{When the} voltage rises above _BE , the transistor T ₅₅ becomes conductive and the charge of the capacitor C ₅₁ is discharged (current I ₁₃ ), so that the potential increase at the point Q _a is prevented. Therefore, the output voltage V _out does not exceed a certain constant potential V _L. Since the currents flowing through the transistors T ₆₁ (T ₆₃ ) and T ₆₂ are equal, this constant potential V _L is given by the following equation.

V _L = (R ₅₃ / R ₅₁ ) · V _BE (8) At time t ₂₄ , when the input voltage V _in begins to drop, point Q
_Since the potential of a also drops, the potentials of points Q _b and Q _c also drop, the transistor T55 is turned off, and the output voltage V _out becomes _VL or less.

Depending on the presence or absence of the above limiter action, the difference shown by the solid line and the broken line occurs in the output voltage V _out in FIG. When there is a limiter action, as indicated by the solid line, the output voltage V _out returns to the state of being clamped to the zero potential again at the time t ₂₅ after the time t ₂₄ . On the other hand, when there is no limiter action, the output voltage V _out becomes equal to or higher than the voltage V _L , as shown by the broken line, and the return to the clamp state is delayed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a wireless AE telemeter device, and FIG. 2 is a waveform diagram showing an output signal of the block. FIGS. 3 and 4 show the positional relationship between the transmitter and the receiving head. FIG. 3 shows the case where one transmitter moves, and FIG. 4 shows the case where a plurality of transmitters are provided. ing. FIG. 5 is a circuit diagram showing an envelope detection circuit, FIG. 6 is its equivalent circuit diagram, FIG. 7 is its waveform diagram, FIG. 8 is a circuit diagram showing a modified example, and FIG. 9 is an improved envelope detection circuit. It is a circuit diagram showing. FIG. 10 is a circuit diagram showing an example of the synthesis circuit, and FIG. 11 is its waveform diagram. FIG. 12 is a circuit diagram showing an example of a light emitting diode drive circuit, and FIG. 13 is a circuit diagram showing a modification thereof. 14 is a circuit diagram showing an example of a clamp circuit, FIG. 15 is a waveform diagram showing its input and output signals, FIG. 16 is a circuit diagram showing an improved clamp circuit, FIG. 17 is its waveform diagram, FIG. 18 is a circuit diagram showing another example of the clamp circuit, and FIG. 19 is its waveform diagram. 10 …… Transmitter ， 14 …… Pulse oscillator circuit ， 15 …… Synthesis circuit ， 16 …… FM modulation circuit, 20 …… Receiver, 26 …… Demodulation circuit, 27 …… Clamp circuit, 28 …… Low pass filter.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koichi Yaida 10 Tatedo-cho, Hanazono-cho, Ukyo-ku, Kyoto Prefecture, Kyoto Tateishi Electric Co., Ltd. -Kerwaf 4 (72) Inventor Ernst Her Nordholt Netherlands 2628 Säde, Delft, Märkelwaf 4

Claims (5)

[Claims] 1. A transmission device and a reception device, wherein the transmission device synthesizes a pulse generation circuit for generating a pulse signal, a signal to be transmitted and the pulse signal, and a pulse signal component in the synthesized signal. The receiving device includes a demodulator circuit that demodulates the received signal and a demodulator circuit that demodulates the received signal. Wireless telemeter device including a clamp circuit that shifts the level of the demodulated signal so that the peak value of the pulse signal that is generated matches the reference level, and a low-pass filter that removes the pulse signal from the output signal of the clamp circuit . 2. The wireless telemeter device according to claim 1, wherein the reference level is a ground level. 3. The wireless telemeter device according to claim 1, wherein the peak value is the minimum level of the pulse signal. 4. The wireless telemeter device according to claim 1, wherein the peak value is the highest level of the pulse signal. 5. A plurality of transmitters are provided, and when the frequencies of these carrier signals are different, the receiver is provided with a circuit for converting a signal transmitted from each transmitter into a common intermediate frequency signal. The wireless telemeter device according to claim (1).