JPH0646247A - Picture information processing unit and picture element data magnification circuit - Google Patents

Abstract

PURPOSE:To reduce the processing time by executing a series of processing such as decoding, insertion and coding of picture information within a unit without transfer of the picture information under processing onto a system bus. CONSTITUTION:An original picture set to a scanner is read one by one line each at a prescribed picture element density and the obtained raw picture information is transferred to a coding circuit 3a of a picture information conversion section 3. The coding circuit 3a compresses the raw picture information by a prescribed coding system such as the MMR system and stores the picture information subjected to data compression in a picture memory. Then the picture transmission is started. That is, the coded picture information stored in the picture memory is read and transferred sequentially to a decoding circuit 3d of the picture information conversion section 3. The decoding circuit 3d decodes the inputted coded picture information into the original raw information and the magnification circuit 3c magnifies the raw picture information as required.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to image information for performing various processes such as image information coding / decoding, image size scaling, and image information insertion processing for inserting other image information into one image information. The present invention relates to a processing device and a pixel data scaling circuit.

[0002]

2. Description of the Related Art In general, a facsimile apparatus, when the recording paper size on the receiving side is smaller than the size of the original image to be transmitted, such as A3 size to B4 size or B4 size to A4 size, Reduce the image and send.

Further, when a document image is temporarily stored in a memory and transmitted, the document image is read at the highest pixel density of the apparatus, the obtained image information is accumulated, and received at the time of transmission. The image is converted into image information having a pixel density suitable for the recording capability of the facsimile machine on the side and transmitted. Such a facsimile machine has, for example, 16 × 15.4 (dots / m
Scan the original image with m) and set the image information to 8 x 7.7.
When sending to the receiving side with (dot / mm) recording capability,
The number of pixels per line of image information and the number of lines per page are reduced to 1/2. This process is equivalent to the process of reducing the image size to 1/2.

On the other hand, in recent years, a G3 / G4 combined facsimile apparatus having two types of communication functions of a G3 mode and a G4 mode has been put into practical use. In the G3 mode, the pixel density of the image to be transmitted is, for example, 8 × 7.7 (dots / mm).
It is specified in millimeter system like. In the G4 mode, for example, 200 × 200 (dpi: dot pe)
r inch) is specified in inches.

Comparing the two types of pixel densities, 8 dots / mm is about 203 dpi, 7.7 dots / mm
Correspond to about 196 dpi, respectively. In the case of a G3 / G4 combined facsimile apparatus, the hardware of the image reading unit and the recording unit generally conforms to either the millimeter system or the inch system. For this reason, for example, when a facsimile device having a reading unit and a recording unit of 8 × 7.7 (dots / mm) communicates with a 200 × 200 (dpi) facsimile device, image information to be transmitted is 2
It is designed to be enlarged or reduced at a small ratio such as 03/200 and 196/200.

As described above, the facsimile apparatus needs to scale the image information to be transmitted at various ratios as needed.

By the way, as such a scaling method of image information, for example, as shown in Japanese Patent Publication No. 62-43589 or Japanese Patent Publication No. 61-45428, a bit string of binary image information is arranged at regular intervals. Something that thins out or interpolates is proposed.

According to these proposals, the scaling processing of image information can be performed with a relatively simple circuit. However, the scaling factor is fixedly set in advance in the circuit at a constant integer ratio such as 3/4, 2/3, 5/7 or 12/13.

Therefore, for example, when the A3 size is reduced to the A4 size, the dimensional ratio is "0.7071 ...", but an integer ratio of "5/7" is used as an approximate value. Then, in this case, 5/7 = 0.7142, and the scaling error was about 1%. In order to reduce the scaling error, it is necessary to form a circuit dedicated to the scaling ratio.

Further, when the image information is scaled at various ratios as in a facsimile machine, a plurality of circuits must be arranged corresponding to the respective scaling factors, and the circuit scale is increasing. It was

On the other hand, a TTI (Transmi
tter Terminal Identifier)
Facsimile machines that insert and transmit information are well known. This TTI information is usually information on the name of the transmission source and the transmission date and time, and is inserted at the upper end of the transmission image.

As described above, in the case of a facsimile apparatus which temporarily stores and transmits image information, the image information is usually encoded and stored. Then, when inserting the TTI information at the time of transmission, the accumulated encoded image information is transferred from the image memory to the encoding / decoding unit and is once decoded into the original image information. Then, the original image information is transferred to the buffer memory, and the TTI information is inserted in the memory. When the image is to be scaled, the original image information obtained by decoding is transferred to the scaling unit for predetermined scaling, and then transferred to the buffer memory. In this way, the image information added with the TTI information is re-encoded and transmitted.

By the way, in the conventional facsimile apparatus, the image memory, the encoding / decoding unit, the scaling unit, the buffer memory, etc. are independent from each other due to the hardware configuration, and as described above, the image information is transmitted between the respective units. If you want to transfer
Image information is transferred via the system bus.

Generally, the system bus has a limited data transfer capability. Therefore, as described above, it takes a long processing time to execute a series of various processes such as decoding of encoded image information, scaling, insertion of TTI information and encoding.

[0015]

As described above, conventionally, when the scaling processing of image information is performed at various ratios, the circuit scale increases, and the decoding, scaling, insertion of TTI information and encoding are performed. When performing a series of processing such as conversion, there is a problem that the processing time is long.

It is an object of the present invention to solve the above problems and provide an image information processing apparatus capable of shortening the processing time and a pixel data scaling circuit capable of arbitrarily setting the scaling factor. .

[0017]

To this end, the image information processing apparatus of the present invention has a decoding circuit for decoding encoded image information, and the image size of the raw image information obtained by the decoding is determined by the number of pixels. Various circuits such as a scaling circuit that scales by increase and decrease, an image information insertion circuit that inserts other image information into the scaled raw image information, and an encoding circuit that re-encodes the raw image information that has been subjected to various processes. Is arranged in one unit, and a series of processing such as decoding, scaling, insertion of image information, and encoding is executed in that unit without transferring the image information being processed to the system bus. I am trying to do it.

The pixel data scaling circuit of the present invention further comprises means for sequentially inputting pixel data line by line, means for generating first and second clock signals having the same basic period, and first clock signal. A means for sequentially extracting a fixed number of adjacent pixel data from the pixel data input in synchronism with the serial signal, a means for selectively outputting one of the fixed number of pixels based on a fixed condition, In the case where the set scaling ratio is greater than 1, a unit is provided which sequentially fetches the one pixel selected and output in synchronization with the clock signal and outputs it as scaling pixel data, and a unit which sets the scaling ratio of the image. In order to increase the number of pixels to be output with respect to the number of input pixels, the image is enlarged by stopping the pulse output of the first clock signal once at a fixed number of times based on the scaling ratio. If the set scaling ratio is less than 1, the pulse output of the second clock signal is stopped once at a fixed number of times based on the scaling ratio, thereby reducing the number of output pixels and displaying an image. I try to reduce it.

[0019]

In the above image processing apparatus, the image information is not transferred to the outside of the unit via the system bus when executing a series of processing, so that the processing time can be shortened. Further, in the pixel data scaling circuit, various scaling factors can be arbitrarily set only by changing the data value to be set.

[0020]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a facsimile apparatus according to an embodiment of the present invention. In the figure, a scanner 1 reads a document image, and a plotter 2 records the image on a recording sheet. The scanner 1 reads out image information line by line by known main scanning and sub-scanning with one pixel density defined by a G3 mode millimeter system or a G4 mode inch system. Similarly, the plotter 2 also records an image with one pixel density defined by the millimeter system or the inch system. The image information conversion unit 3 performs encoding / decoding of image information, scaling processing of image size, and the like. The image memory 4 temporarily stores image information.

The communication processing unit 5 uses a PSTN (Public).
Switched Telephone-hone Netw
ork) line and ISDN (Integrated S)
e-rvices Digital Network)
A line is connected and the image information is transmitted by one of the selected lines. The communication processing unit 5 includes a G3 / G4 mode transmission unit that transmits image information in two types of communication modes, a G3 mode and a G4 mode. Operation display section 6
Indicates that the operator performs various operations and the device displays an operating state and the like. The system control unit 7
It is a microcomputer for monitoring and controlling the above-mentioned respective parts. The system control unit 7 includes a buffer memory 7a for temporarily storing image information.

Each of the scanner 1, plotter 2, image information conversion unit 3, image memory 4, communication processing unit 5, operation display unit 6 and system control unit 7 is, for example, unitized and independent in terms of hardware. ing. System bus 8
Is a signal line for exchanging control signals, image information, and the like between these respective units.

FIG. 2 shows the configuration of the image information conversion unit 3, in which the encoding circuit 3a encodes image information by a known encoding method and compresses the data. Selector 3
In b, the image information output from the scaling circuit 3c or the image information transferred from the system bus 8 is selectively input to the encoding circuit 3a. The scaling circuit 3c scales the image size by thinning out or interpolating pixels from the image information of each line. The decoding circuit 3d is for decoding the encoded image information to restore the original image information.

FIG. 3 shows a circuit configuration diagram of the scaling circuit 3c. In the figure, a clock signal CLK generated by a circuit (not shown) corresponds to the AND circuit 101 and 102.
It is input to one of the inputs. AND circuit 10
The output of 1 is input to each clock signal terminal of the D-type flip-flop 103, the P / S (parallel / serial) conversion circuit 104, and the counter 105.

The P / S conversion circuit 104 includes a decoding circuit 3
Image information of a constant bit, which is input as a binary parallel signal from the d side, is input. The two signals output from the P / S conversion circuit 104 are input to the interpolation logic circuit 106, and one of them is further input to the D-type flip-flop 103. D-type flip-flop 10
The output signal of the output terminal Q of No. 3 is also input to the interpolation logic circuit 106. The output signal of the interpolation logic circuit 106 is S / P.
It is input to the (serial / parallel) conversion circuit 107. The output signal of the AND circuit 102 is the S / P conversion circuit 1
It is input to the clock signal terminal 07 and the load signal terminal of the register 108.

The counter 105 is a 4-bit binary counter, and its count output is input to the comparator 109. The register 108 is a 12-bit register,
The upper 4 bits are input to the comparator 109. The output signal of the comparator 109 is the AND circuits 110 and 11
1 and the interpolation logic circuit 106, respectively.
Further, a control signal C for switching between the enlargement operation and the reduction operation is input to the AND circuit 110, and the AND circuit 111
The inverted signal is input to. AND circuit 11
The output of 0 is inverted and input to the other input of the AND circuit 101, and the output of the AND circuit 111 is inverted and input to the other input of the AND circuit 102.

12-bit output of the register 108,
The control data R for setting the scaling factor is input to the adder 112, and the output signal of the adder 112 is the register 10
It is entered in 8. The 7th bit data signal # 7b of the register 108 is input to the interpolation logic circuit 106.

Next, a memory transmission operation in which the facsimile apparatus according to the present embodiment having the above-mentioned configuration temporarily stores and transmits image information will be described.

In this case, the operator sets the transmission document on the scanner 1 and performs a predetermined operation on the operation display unit 6 to
Select the line and communication mode to be used, enter the destination and start up. The line selection at this time is
Selection of the PSTN line and ISDN line, and selection of the communication mode is selection of the G3 mode and the G4 mode.

When the facsimile apparatus is started, as shown in FIG. 4, first, the original image storage operation is executed. That is, the original image set on the scanner 1 is sequentially read line by line with a predetermined pixel density. The obtained raw image information is transmitted via the buffer memory 7a as shown in FIG.
It is transferred to the encoding circuit 3a of the image information conversion unit 3. The encoding circuit 3a data-compresses the raw image information by a certain encoding method such as the MMR method. Then, the compressed image information is stored in the image memory 4 (above, processing 1001 in FIG. 4).

When the storage operation is completed, the facsimile machine calls the transmission destination (process 1002). Then, when the destination facsimile machine responds, a predetermined transmission procedure in the G3 mode or the G4 mode is executed. In the case of the G3 mode, the NSS signal is transmitted and the NSF signal is received from the other party to determine various functions of the receiving side device such as the recording paper size and the pixel density at the time of image recording. In the case of G4 mode, the C
By sending a DCL command and receiving an RDCLP response from the other party, the function of the receiving side device is similarly determined. Then, based on the determination result, transmission conditions such as the size and pixel density of the document image to be transmitted are determined (process 1003).

Then, image transmission is started. That is,
As shown in FIG. 6, the encoded image information stored in the image memory 4 is read out, and the decoding circuit 3d of the image information conversion unit 3 is read.
Sequentially transferred to. The decoding circuit 3d decodes the input encoded image information and restores the original raw image information. Magnification circuit 3c
Scales the raw image information as necessary.

As described above, in this scaling, when the size of the original image and the recording paper size on the receiving side are different, or the pixel density of the stored original image and the pixel density during recording on the receiving side are different. In addition, one of the scanner 1 and the recording unit on the receiving side conforms to the millimeter system standard,
If the pixel densities do not match, such as the other conforms to the inch-based standard, it is executed at various predetermined scaling factors.

Now, the scaling operation of the scaling circuit 3c will be described.

The scaling circuit 3c inputs image information of each line, that is, binary pixel data of a fixed number of bits in the main scanning direction,
The pixel is reduced by thinning out the number of pixels to reduce the number of pixels, or enlarged by interpolating the pixels to increase the number of pixels. Here, if the number of bits of the pixel data input per line is li and the number of bits after the above process is performed is lo, the scaling factor is lo / li.

When the image information conversion unit 3 operates, the system control unit 7 inputs the value of the reciprocal li / lo of the scaling factor as control data R into the adder 112, and at the same time, indicates whether to enlarge or reduce. Control signal C is applied to AND circuits 110 and 11
Enter 1.

In this embodiment, the scaling factor is "0.062".
It can be set in the range of "5" to "256". For example, when the scaling ratio is "0.0625", the 12 bits of the control data are "1", that is, "1111111111".
The value is 11 ”. If the scaling factor is 256,
Only the least significant bit is “1”, that is, “0000000000
The value will be "01". The control signal C is set to "H" (high level) when performing the expanding operation, and is set to "L" (low level) when performing the reducing operation.

Then, the clock signal CLK is input to the AND circuits 101 and 102, and each pixel data of the image information is input to the P / S conversion circuit 104 as a parallel signal by a fixed number of bits at a fixed cycle.

Here, as an example of the reducing operation, for example,
It is assumed that the scaling factor is set to "4/5", that is, "0.8". In this case, the control data R is set to "1.25" and the control signal C is set to "L" level.

FIG. 7 shows the operation of the scaling circuit 3c at this time. The horizontal axis of the graph shown in FIG.
It is a scale corresponding to each input pixel data, and the vertical axis is a scale corresponding to the output pixel data. In addition, the ○ mark on the diagonal line is each input pixel, and the * mark is
The sample position of the pixel to output is shown. It should be noted that the size of the inclination angle of this diagonal line is proportional to the scaling factor.

A clock signal CLK having a constant period is constantly input to the AND circuits 101 and 102. Now, the control signal C is "L", and the output of the AND circuit 110 is
It becomes "L". The AND circuit 101 inputs the clock signal CLK and outputs the clock signal CLK1 as shown in FIG. As a result, the P / S conversion circuit 104 converts the input pixel data into a serial signal and outputs the serial signal from the two output terminals. Now, assuming that a sequence number is given to each input pixel data, the nth pixel and the (n + 1) th pixel are simultaneously output from the two output terminals one pixel at a time. Further, the D-type flip-flop 103 is
The pixel data of the nth pixel is delayed by one cycle of the clock signal CLK1 and output, and the (n-1) th pixel is output pixel by pixel.

The counter 105 executes the counting operation of the clock signal CLK1 as shown in FIG. Further, in the initial state, the upper 4 bits of the counter 105 and the register 108 are both “0”. The comparator 109 compares the two. Since the two are now in agreement, the judgment signal D of "L" is output as shown in FIG.
As a result, the output of the AND circuit 111 becomes "L".
As a result, the AND circuit 102 receives the clock signal CLK.
Enter. As a result, the clock signal CLK2 is output as shown in FIG.

The adder 112 outputs the added value of the control data R which is the reciprocal of the scaling factor and the data value of the register 108. Then, the register 108 outputs the clock signal C
Each time LK2 is input and one pulse is input, the above added value is loaded. In this case, the integer part of the added value is loaded into the upper 4 bits, and the decimal part is loaded into the lower 8 bits. As a result, the value of the register 108 is synchronized with the clock signal CLK2 as shown in FIG.
25 "increments. In other words, this register 108
This means that it is acting as an accumulator for the arithmetic circuit.

By the way, as shown in FIG. 8, the interpolation logic circuit 106 outputs P / when the determination signal D is "L"("0") and the seventh bit # 7b of the register 108 is "L".
When the 7th bit # 7 of the pixel data of the nth pixel output from the S conversion circuit 104 is “H” (“0”), the pixel data of the (n + 1) th pixel is output as the pixel data X, respectively. On the other hand, when the determination signal D is “H”, the register 108
Pixel data of the (n-1) th pixel output from the D-type flip-flop 103 when the 7th bit # 7 is "L", and the nth pixel is the 7th bit # 7 is "H" The data is output as pixel data X, respectively.

The S / P conversion circuit 107 sequentially inputs the pixel data X thus output in synchronization with the clock signal CLK2. By the way, in the case of this example, the counter 10
When the count value of 5 becomes "4", the upper 4 bits of the register 108 become "5", the two do not match, and the determination signal D becomes "H". Therefore, the AND circuit 102
Then, the clock signal CLK is inhibited by one pulse,
Only one pixel of pixel data is thinned out without being input to the S / P conversion circuit 107.

At this time, the adding operation of the register 108 is stopped once. Then, the addition operation is continued from the next one pulse of the clock signal CLK1, the value of the register 108 and the value of the counter 105 match again, and the same operation is repeated.

When the count value of the counter 105 reaches "9", the image information is thinned out by one pixel as in the above.

By the way, in the case of the reduction operation, as indicated by the shaded area in FIG. 7A, from the input pixel data indicated by a circle,
Pixel data of a number smaller than the input pixel number is sampled and output as indicated by *. In this case, since the pitch of the output pixels is larger than the pitch of the input pixels, from the nth pixel of the input pixel data to (n +
1) There are cases where the output pixel is sampled and cases where it is not sampled until the pixel. Also, when sampling the output pixel, there are cases where the position to be sampled is near the n-th pixel and near the (n + 1) -th pixel.

In the above circuit operation, when the output pixel is sampled, the determination signal D becomes "L". If the position to be sampled is close to the nth pixel, the seventh bit # 7 of the register 108 becomes “L”, and (n + 1)
If it is close to the pixel eye, it becomes "H". Therefore, the interpolation logic circuit 106 samples and outputs a predetermined input pixel based on the determination signal D and the state of the seventh bit # 7b, and the pixel is set in the S / P conversion circuit 107. .

Further, the clock signal CL shown in FIG.
The broken line connecting each pulse of K2 and the * mark in FIG.
The timing at which each pixel data is input to the S / P conversion circuit 107 is shown. In this way, the input image information of 5
The image size is reduced in the main scanning direction by the scaling factor “0.8” by thinning out the pixels once for each pixel.

Next, as an example of the enlarging operation, it is assumed that the scaling factor is set to "5/4", that is, "1.25". In this case, the control data R is set to "0.8" and the control signal C is set to "H" level.

FIG. 9 shows the operation of the scaling circuit 3c at this time.

Since the control signal C is "H", the output of the AND circuit 111 is always "L", and the AND circuit 102
From the clock signal CLK2 as shown in FIG.
Is continuously output. Then, the value of the register 108 increases by "0.8" in synchronization with the clock signal CLK2.

The value of the counter 105 and the register 10
During the period in which the value of the higher 4 bits of 8 coincides, the determination signal D becomes “L” as shown in FIG. 7D, and the clock signal CLK1 becomes low as shown in FIG. Is output. As a result, similarly to the above, the input pixel data is sequentially input to the S / P conversion circuit 107.

On the other hand, in this case, the value of the counter 105 and the value of the upper 4 bits of the register 108 do not match,
When the determination signal D becomes "H", the clock signal CLK1 is inhibited by one pulse. As a result, the input of image information to the P / S conversion circuit 104 is temporarily stopped during the period of one cycle of the clock signal CLK1, and the counting operation of the counter 105 is temporarily stopped as shown in FIG.

However, also in this period, the interpolation logic circuit 106
Outputs pixel data X under the conditions shown in FIG. 8 and also outputs the clock signal CLK2, so the pixel data X is input to the S / P conversion circuit 107. Since this operation is executed once for every 4 pixels of the input pixel data, the number of pixels in one line is increased by 1.25 times.

In the case of the enlarging operation, the pitch of the output pixels becomes shorter than the pitch of the input pixels, as shown by the hatched area in FIG. Therefore, the input pixel data is always sampled and output as the output pixel. Then, in the case of sampling and outputting, input pixels at close positions are sampled, and one input pixel is sampled continuously at fixed pixels. In this way, the image size is enlarged in the main scanning direction by the set scaling ratio.

As described above, the reduced or enlarged image information is input to the encoding circuit 3a and is encoded again by the encoding method suitable for the receiving side device. Note that this processing is executed in units of one line of image information, but in the case of reduction, when reading image information from the image memory 4, one line is thinned out to a fixed number of lines in accordance with the reduction ratio. Reduce the image size in the scan direction. In the case of enlargement, the image size of the same line is enlarged twice in the sub-scanning direction by processing the image information of the same line once every fixed number of lines according to the enlargement ratio. The communication processing unit 5 transmits the image information encoded in this way (FIG. 4, process 1004).

As described above, in this embodiment, the encoding circuit 3a, the decoding circuit 3d, and the scaling circuit 3c are arranged in the image information converting section 3 which is one unit. As a result, when transmitting the image information stored in the image memory 4, a series of processes such as decoding, scaling, and encoding of the stored image information can be executed in one unit.

In this case, since it is not necessary to temporarily transfer the image information to the system bus 8 or the buffer memory 7a as in the conventional case, the time required to transfer the image information is shortened.
This makes it possible to shorten the series of processing times.

Further, in the scaling circuit 3c, the P / S conversion circuit 104 and the D-type flip-flop 103 respectively synchronize the pixel data of three adjacent pixels from the input pixel data in synchronization with the clock signal CLK1. The interpolation logic circuit 106 selects and outputs one pixel of the pixels sequentially based on a certain condition, and the S / P conversion circuit 107 sequentially acquires the selected and output one pixel in synchronization with the clock signal CLK2. , Is output as scaled pixel data. When the enlargement, that is, the scaling factor is greater than 1, the pulse output of the clock signal CLK1 is stopped once at a fixed number based on the scaling factor, so that the number of pixels captured by the S / P conversion circuit 107 is reduced. The number of images is increased to enlarge the image. When the reduction, that is, the scaling factor is smaller than 1, the pulse output of the clock signal CLK2 is stopped once at a fixed number based on the scaling factor, thereby reducing the number of pixels taken in by the S / P conversion circuit 107. Then, the image is reduced.

As a result, the scaling circuit 3c can arbitrarily set various scaling factors by changing the set value.

When selecting one pixel from the adjacent three pixels, the interpolation logic circuit 106 outputs the input pixel position and the output pixel to be sample-output on the time axis, as is apparent from FIGS. 7 and 9. When viewed in correspondence with the position, the input pixel close to the output pixel position is selectively output. As a result, the deterioration of the image quality due to the scaling of the image can be reduced.

In the above embodiment, the register 108 of the scaling circuit 3c uses a 12-bit register. However, if a register with a larger number of bits is used, the scaling accuracy can be improved. There is no end.

FIG. 10 is a block diagram of the image information converting section 3 according to another embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 2 indicate the same circuits or the same parts, and in the present embodiment, a selector 3e and a buffer memory 3f are further arranged. The selector 3e is for selecting the input data from the system bus 8 or the output of the scaling circuit 3c. The buffer memory 3f temporarily stores the selected data, and the stored data is input to one of the two inputs of the selector 3b.

With this configuration, when transmitting an image, the facsimile apparatus of this embodiment transmits the image information stored in the image memory 4 as in the above-described embodiment. In this case, the image size of the image information to be transmitted is scaled as needed and the TTI information is inserted.

FIG. 11 shows the processing of the image information conversion unit 3 of this embodiment. That is, when the facsimile information transmission operation is started, the facsimile device reads out one line of the image information stored in the image memory 4 and transfers it to the decoding circuit 3d. The decoding circuit 3d decodes the image information into the original raw image information (process 2001). The scaling circuit 3c scales the raw image information (processing 2002). At this time, the selector 3e selects the scaling circuit 3c side, and the scaled image information is stored in the buffer memory 3f (Processing 2
003).

Next, the facsimile machine determines the data amount of the image information stored in the buffer memory 3f (20
04). If the amount of data is less than the fixed number of lines corresponding to the capacity of the buffer memory 3f (N in process 2004), the above process is repeated (process 2001).
What).

When a predetermined number of lines of image information is stored in the buffer memory 3f (Y in step 2004), it is determined whether the line position of the image information just stored corresponds to the TTI information insertion position (step 2005). ). The TTI information is generally inserted at a fixed position at the upper end of the original image of one page. Therefore, each line corresponding to the fixed position becomes the insertion position.

Here, when the image information stored in the buffer memory 3f is the insertion position of the TTI information (process 200)
5 Y), and then the selector 3e is switched to the system bus 8 side input. Then, the system control unit 7 generates predetermined TTI information. This TTI information is pixel data in which character information indicating the name of the facsimile station registered in advance and the date and time at the time of operation is bitmap-developed. The generated TTI information is transferred to a predetermined area of the buffer memory 3f via the selector 3e. As a result, the TTI information is overwritten on the image information of the original image (process 2006). On the other hand, when the image information of the buffer memory 3f is not the insertion position of the TTI information (Processing 20
05 N), the insertion of the TTI information is not executed.

At this time, the selector 3b selects the buffer memory 3f side. The facsimile apparatus reads one line of image information from the buffer memory 3f and inputs it to the encoding circuit 3a via the selector 3b. The encoding circuit 3a encodes the image information (process 2007). The encoded image information will be transmitted to the other party.

Next, the facsimile machine determines whether or not other image information is still stored in the buffer memory 3f (process 2008). Then, when the image information is stored (N in process 2008), the same encoding process is repeated (to process 2007). And the buffer memory 3
When all the image information in f is read and the buffer memory 3f becomes empty (Y in process 2008), it is further determined whether the image information in the image memory 4 has been processed for all lines (process 2009).

If all lines have not been processed (N in process 2009), the above process is repeated for the next image information in the image memory 4 (to process 2001). When the image information in the image memory 4 has been processed for all lines (process 20
09 Y), the operation ends.

As described above, in the present embodiment, the selector 3e and the buffer memory 3f are further provided in the image information conversion unit 3 in addition to the above-described embodiment, while the scaled image information is selected. After being temporarily stored in 3e, the TTI information is overwritten in the selector 3e to insert the TTI information into the image information. That is, in this case, the selector 3e and the buffer memory 3f form a TTI information insertion circuit.

According to this configuration, as compared with the case of FIG.
The TTI information can be inserted into the transmission image by simply adding the two components of the selector 3e and the buffer memory 3f.

Further, in this case, similarly to the above-mentioned embodiment,
Since each processing described above is executed in one unit without temporarily transferring the image information to the system bus 8 or the buffer memory 7a, the processing time can be shortened.

FIG. 12 shows still another embodiment of the image information scaling section 3. In the figure, the same reference numerals as those in FIG. 10 indicate the same circuits or the same parts. In this embodiment, data is directly input to the buffer memory 3f from the system bus 8 and one of the output data of the buffer memory 3f, the output data of the scaling circuit 3c and the input data from the system bus 8 is input. Are selected by the selector 3g and input to the encoding circuit 3a.

In this embodiment, when the image information stored in the image memory 4 is transmitted, various processes are executed for each line. That is, as shown in FIG. 13, when the facsimile device starts the image information transmission operation, the facsimile device determines the line position of the image information read from the image memory 4 (process 300).
1). Now, assuming that the line position to be read is not the insertion line position of the TTI information (N in process 3001), one line of image information is read from the image memory 4 and decoded by the decoding circuit 3d (process 3002). Then, the scaling circuit 3c performs scaling (process 3003). Then, the scaled image information is input to the encoding circuit 3a via the selector 3g and encoded (process 3004).

Thereafter, it is determined whether or not all lines have been processed (process 3005), and when all lines have not been processed (N in process 3005), the same process is repeated (process 3001).
What).

Next, when the line position read from the image memory 4 becomes the insertion line position of the TTI information (Process 3
(Y of 001), one line of the TTI information that has undergone bitmap expansion is stored in the buffer memory 3f (process 300).
6). Then, the image information for one line is read from the image memory 4, decoded (process 3007), and further scaled (process 3008).

The scaled image information is sequentially output pixel by pixel from the scaling circuit 3c. At the same time that this image information is output, the TTI information stored in the buffer memory 3f is sequentially read pixel by pixel. At this time, the selector 3g first sequentially inputs the image information output from the scaling circuit 3c. Then, the image information output from the buffer memory 3f side is input only during the period corresponding to the pixel position where the TTI information should be inserted. As a result, the TTI information is inserted into one line of image information in the image memory 4 (process 300).
9). The image information input by the selector 3g is the encoding circuit 3
It is input to a and encoded (process 3004).

In this way, 1 is added to the predetermined position of the transmitted image.
TTI information is inserted line by line. The processed image information is transmitted to the other party. Then, when all the lines of the image information in the image memory 4 have been processed (Y in process 3005), this image process is completed.

As described above, in this embodiment, the TTI information is stored line by line in the buffer memory 3f, and when the scaled image information is transferred from the scaling circuit 3c to the encoding circuit 3a, it is predetermined. The TTI information is transferred instead of the image information at the pixel position. By performing such a transfer operation, the buffer memory 3f and the selector 3g are
And constitute a TTI information insertion circuit.

With this structure, the number of selectors can be reduced from two to one as compared with the above-described embodiment shown in FIG. 10, and the buffer memory 3f can have a capacity of one line.

In each of the above embodiments, the operation of inserting known information called TTI information into the image information to be transmitted has been described, but it goes without saying that arbitrary image information can be inserted in the same manner without being limited to TTI information.

Further, in each of the above embodiments, the image information converting section 3 is basically provided with the decoding circuit 3d, the scaling circuit 3c and the encoding circuit 3a, and further the TTI information insertion circuit. However, for example, when the scaling processing is unnecessary, the scaling circuit 3c may be deleted and only the necessary circuits may be provided. Even in that case, when a plurality of processes are sequentially executed, the processes can be performed in one unit, so that the processing speed is improved.

Further, the facsimile apparatus for transmitting image information has been described as an example. However, in other apparatuses such as an image filing apparatus, it is referred to as decoding, scaling, insertion and encoding of image information. The present invention can be similarly applied when executing such a series of various processes.

[0089]

As described above, according to the present invention, various circuits such as a decoding circuit, a scaling circuit, a circuit for inserting image information, and an encoding circuit are provided in one unit. ,
Since the series of processing by each of these circuits is executed without transferring the image information on the system bus, the processing time can be shortened.

When the image is scaled, one clock signal is used to input pixel data and the other clock signal is used to output pixel data, and either one of the clock signal pulse outputs is set. The number of pixels of the output pixel data is increased or decreased to stop the image once by stopping once at a fixed number based on the scaling ratio. The scaling factor can be set arbitrarily.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a facsimile apparatus according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram of an image information conversion unit.

FIG. 3 is a circuit configuration diagram of a scaling circuit.

FIG. 4 is an operation flowchart of a memory transmission process of the facsimile device.

FIG. 5 is an explanatory diagram showing a flow of image information during image storage.

FIG. 6 is an explanatory diagram showing a flow of image information when transmitting accumulated image information.

FIG. 7 is an explanatory diagram showing an image reducing operation of the magnification varying circuit.

FIG. 8 is an explanatory diagram of output pixel data of an interpolation logic circuit.

FIG. 9 is an explanatory diagram showing an image enlarging operation of the magnification varying circuit.

FIG. 10 is a block diagram showing another embodiment of the image information scaling unit.

FIG. 11 is an operation flowchart of the image information scaling unit in the embodiment.

FIG. 12 is a block diagram showing still another embodiment of the image information scaling unit.

FIG. 13 is an operation flowchart of the image information scaling unit in the embodiment.

[Explanation of symbols]

 1 Scanner 2 Plotter 3 Image Information Converter 3a, 3d Encoding Circuit 3b, 3e Selector 3c Variable Magnification Circuit 3f Buffer Memory 4 Image Memory 5 Communication Processor 6 Operation Display 7 System Control 7a Buffer Memory 8 System Bus 101, 102 , 110, 111 AND circuit 103 D-type flip-flop 104 P / S conversion circuit 105 Counter 106 Interpolation logic circuit 107 S / P conversion circuit 108 Register 109 Comparator 112 Adder

Claims (7)

[Claims] 1. A processing circuit for executing various processes is provided in each of the plurality of units, and while processing image information while transferring various data between the units via a system bus, encoded image information is processed. In the image information processing apparatus including a decoding circuit that decodes the image information into the raw image information, and a scaling circuit that scales the image size of the raw image information by increasing or decreasing the number of pixels, the decoding circuit and the scaling While the circuit and the circuit are provided in one unit, the image information being processed on the system bus for each processing of decoding the encoded image information and scaling of the raw image information obtained by the decoding. An image information processing apparatus comprising: a processing unit that is executed in the one unit without transferring the image. 2. An encoding circuit for encoding raw image information is further provided in the one unit, and decoding of the encoded image information and scaling of the raw image information obtained by the decoding are performed. And processing means for executing each processing of encoding the scaled raw image information in the one unit without transferring the image information being processed to the system bus. The image information processing apparatus according to claim 1. 3. The image information inserting circuit for inserting another image information into the raw image information is further provided in the one unit, and the encoded image information is decoded and the raw image obtained by the decoding is provided. Image information that is being processed on the system bus by performing scaling of information, insertion of the other image information into the scaled raw image information, and encoding of the inserted raw image information. 3. The image information processing apparatus according to claim 2, further comprising a processing unit that is executed in the one unit without transferring the data. 4. The image information inserting circuit temporarily stores the scaled raw image information in a buffer memory, and then stores the other image information in a certain area in the buffer memory. The image information processing apparatus according to claim 3, wherein the image information processing apparatus is means for executing the insertion processing of 5. The image information inserting circuit temporarily stores the other image information in a buffer memory, and then temporarily transfers the scaled raw image information to the encoding circuit. 4. The image information processing apparatus according to claim 3, wherein the image information processing apparatus is means for executing the insertion processing of the image information by transferring the image information in the memory instead. 6. Pixel data input means for sequentially inputting pixel data line by line, clock signal generating means for generating first and second clock signals having the same basic period, and synchronizing with the first clock signal. Input pixel data extraction means for sequentially extracting a fixed number of adjacent pixel data from serially input pixel data by serial signals, and interpolation logic means for sequentially selecting and outputting one pixel from the fixed number of pixels based on a certain condition. Pixel data output means for sequentially fetching the one pixel selected and output in synchronization with the second clock signal and outputting it as scaled pixel data, and setting means for setting a scale factor of an image are set. When the scaling factor is greater than 1, the pulse output of the first clock signal is stopped once at a fixed number of times based on the scaling factor, so that the number of input pixels is increased. Image enlarging means for enlarging the image by increasing the number of pixels taken in by the pixel data output means,
When the set scaling ratio is smaller than 1, the pulse output of the second clock signal is stopped once at a fixed number of times based on the scaling ratio, thereby reducing the number of pixels taken in by the pixel data output means. A pixel data scaling circuit, comprising: an image reducing means for reducing an image. 7. The input pixel data extraction means extracts pixel data of three adjacent pixels, while the interpolation logic means selects one pixel out of the three pixels that is close in timing to be sampled as an output pixel. The pixel data scaling circuit according to claim 5, wherein the pixel data scaling circuit outputs the pixel data scaling circuit.