JPH0646102A - Cd and rd phase modulating circuit in atm transmission - Google Patents

Abstract

PURPOSE:To make the difference of RS-CSdrlay small and to make the phases of CD and RD to coincide even when the time interval of cells are not fixed by providing a CD and RD phase modulating circuit. CONSTITUTION:A CD detection part 1 detects the ON and OFF state of CD from a received cell and holds it in a CD register 2, which sends a CD flag to a CD and RD phase modulating circuit 9 and an RS-CS timer 3. The timer 3 shows an RS-CS time by a flag. A cell writing controller 4 controls to write a reception data cell in a cell reception memory 5 and a cell number counter 6 counts the cell number written into the memory 5, constantly monitors a present cell storing state and outputs an ON signal as a cell flag at the time of the storing state. A cell reception memory reading controller 7 reads a cell from the memory 5 to successively read data based on cell assembling information. Read parallel data is P/S converted to the format of a HDLC procedure by HDLC processing part 8 and sent to the side of a terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an ATM (Asynchronous
Transfer Mode: Asynchronous transfer mode)
The present invention relates to an RS-CD transmission device that performs CD transmission, and particularly to a CD and RD phase adjustment circuit that adjusts the phase of a carrier and received data.

[0002]

2. Description of the Related Art RS-CD transmission is, as shown in FIGS. 4 and 5, a transmission request (RS: Request) from a transmission side terminal.
This is a transmission procedure in which a carrier is transmitted by "to Send", and the carrier is detected (CD: Carrier Detect) on the receiving side to enable reception.

In recent years, STM (Synchronous Transfer Mod)
The ATM network has been attracting attention in place of the e: Synchronous transmission mode network, and it is expected that data transmission using this ATM network will become active in the near future. In the ATM network, ST
Unlike the M network, a method of transmitting only valid data is generally used, and RS-CD transmission also involves RS ON / OF.
It is necessary to transmit F information (change point). In the RS-CD transmission in the STM network, the result of constantly monitoring the RS state separately from the data band in CH units is added and transmitted. For example, 7 bits out of 8 bits are assigned as data, and 1 bit is assigned as RS.

FIG. 6 is a block diagram showing a conventional ATM transmission device, and FIGS. 7 and 8 show R using the conventional ATM transmission device.
It is a time chart of each signal when S-CD transmission is performed. Hereinafter, RS (Request to Send) is a transmission request, C
S (Clear to Send) permits transmission, SD (Send Data) transmits data, CD (Carrier Detect) detects carrier,
RD (Receive Data) indicates a received data signal.

RS-CD transmission in conventional ATM transmission is
As shown in FIG. 7, when a change point of RS received from the terminal on the transmitting side is detected, the information of ON is made into cells when RS is ON (hereinafter referred to as RS ON cell), and when RS is OFF. The OFF information is made into cells (hereinafter referred to as RS OFF cells), these cells are assembled separately from the data cells and sent to the line. At this time, a transmission delay (CS: Clear to Send) is added to the sending terminal after adding a certain delay.
Tell. Here, the constant delay time (RS-CSdelay time) is a delay time that differs depending on the capability (processing speed) of the terminal.

On the receiving side, as shown in FIG.
By receiving the ON cell and the RS OFF cell, the CD is transmitted to the terminal on the receiving side. However, in the ATM network, normally, the transmitted cells arrive irregularly in time on the receiving side due to processing such as cell switching and transmission line delay. In other words, the time intervals of arriving cells are not constant, and “fluctuation” of cells occurs.

Therefore, when the received data cell (parallel data) is disassembled into cells and converted into serial data, in order to compensate the transmitted RS-CSdelay time, parallel / speed of 1/8 of the terminal speed is used. The RS-CSdelay timer was monitored at the serial conversion timing, and the phases of CD and RD were adjusted.

[0008]

As described above, the conventional A
In the RS-CD transmission using the TM transmission device, since the time intervals of the cells to be received are not constant, the RS-CSde
If an error occurs when compensating for the lay time, or if the cell is disassembled and the data is sent to the receiving terminal, RSOFF
Since the CD is turned off when the cell is received, there is a problem that the data is cut off.

The present invention has been made in consideration of such circumstances, and reduces the error of RS-CSdelay time,
CD and RD in ATM transmission in which the CD and RD phases are matched even if the cell reception interval is not constant
A phase adjustment circuit is provided.

[0010]

SUMMARY OF THE INVENTION According to the present invention, an ATM-based RS-transmits data by transmitting a carrier in response to a transmission request from a transmitting side and detecting the carrier on the receiving side to enable reception. In a CD transmission device, a carrier detection unit 1 that detects a carrier state from a received cell, a carrier register 2 that holds the carrier state detected by the carrier detection unit 1, and a storage timing of a carrier stored in the carrier register 2. A timer 3 that counts the time from the transmission request to the transmission permission based on the above, and a cell reception memory 5 that stores the received cell,
A cell number counter 6 for counting the number of cells stored in the cell reception memory 5, a carrier state output from the carrier register 2, a time output from the timer 3, and a cell number output from the cell number counter 6 are displayed. By reference, an ATM comprising a phase adjusting circuit 9 for adjusting the carrier state and the phase of the received data and creating a timing for parallel / serial conversion of the received data
It is a CD, RD phase adjustment circuit in transmission.

[0011]

According to the present invention, the carrier state is detected from the received cell and held in the carrier register 2, the time from the transmission request to the transmission permission is counted by the timer 3, and the received cell is further stored in the cell. The cell number is stored in the reception memory 5, and the stored cell number is counted by the cell number counter 6. Then, by referring to the carrier state output from the carrier register 2, the time output from the timer 3, and the received cell count number output from the cell number counter 6, the carrier state and the received data The phase is adjusted and the timing of parallel / serial conversion of received data is created.

Therefore, by referring to the carrier state and the memory state of the cell as the carrier OFF condition, it is possible to prevent the received data from being cut off on the way. Further, if the parallel / serial conversion timing of the received data is created based on the time from the transmission request stored in the timer 3 to the transmission permission, the RS-CSdelay time error can be made smaller than before.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. The present invention is not limited to this.

FIG. 1 shows a CD for ATM transmission according to the present invention.
FIG. 3 is a block diagram showing the configuration of an embodiment of an RD phase adjustment circuit, showing a receiving device for ATM transmission. In the following, RS (Request to Send) is a transmission request, CS (Clear to Send) is a transmission permission, and CD (Carri
er Detect) means carrier detection, SD (Send Data) means transmission data, and RD (Receive Data) means reception data.

In FIG. 1, 1 is a CD from the received cell.
CD detector for detecting the state of CD, 2 holds the state of the CD detected by the CD detector 1, and outputs a CD flag to a CD register, and 3 indicates RS (transmission request) based on the CD flag.
An RS-CS timer that counts CS (transmission permission) time and outputs an RS-CS flag, 4 is a cell write controller that writes a received data cell to a memory, 5 is a cell reception memory that stores the received cell, and 6 is A cell number counter for counting the number of cells stored in the cell reception memory 5.

Reference numeral 7 is a cell reception memory read controller for reading cells from the cell reception memory 5. Reference numeral 8 is parallel / serial conversion (hereinafter referred to as P / S conversion) of received data to perform an HDLC (high level data link control) procedure. This is an HDLC processing unit that converts to the format of and outputs to the terminal side as RD.

Reference numeral 9 denotes a CD / RD phase adjustment circuit, which is a CD
The CD flag (CD FLAG) is received from the register 2 and the RS-CS flag (RS-CS) is received from the RS-CS timer 3.
FLAG), a cell flag (Cell FLAG) indicating the presence / absence of a cell from the cell number counter 6, a clock from the terminal side to adjust the phases of CD and RD, and P / P in the HDLC processing unit 8. Create S conversion timing (PS TIM).

As the circuit operation, first, the ON / OFF state of the CD is detected from the cell received by the CD detecting section 1, and the state of the CD is held in the CD register 2. CD
From register 2, C corresponding to CD ON or OFF
The D flag is sent to the CD / RD phase adjustment circuit 9 and the RS-CS timer 3. The RS-CS timer 3 is an RS-CS.
The flag indicates the RS-CS time. The cell write controller 4 controls the writing of the received data cell in the cell reception memory 5, and the cell number counter 6 counts the number of cells written in the cell reception memory 5 to obtain the current cell reception memory 5 The cell storage state is constantly monitored, and if the cell is stored, it is turned on as a cell flag.
Output a signal.

Cell reception memory read controller 7
Reads a cell from the cell reception memory 5 according to the storage state of the cell, and sequentially reads data from the cell based on the read cell assembly information. Then, the read parallel data is subjected to P / S conversion in the HDLC processing unit 8, and HDL
It is converted to the format of C procedure and sent as RD to the terminal side.

FIG. 2 is a circuit block diagram showing the details of the CD / RD phase adjustment circuit 9. As shown in this figure, C
In the D / RD phase adjustment circuit 9, a CD flag indicating the state of the CD output from the CD register 2, an RS-CS flag indicating the RS-CS time output from the RS-CS timer 3, and a cell number counter 6 It receives the cell flag indicating the storage state of the cell output from the terminal and the terminal clock.

Then, the phases of CD and RD are adjusted based on the conditions of the CD state, RS-CS time, and cell storage state. In other words, the CD is turned on / off according to the received data.
Create a condition for F. Further, a timing signal (shown as PSTIM in the drawing) for P / S converting the data is created. Here, the condition for turning on / off the CD is C
The logic of the state of D and the storage state of the cell is taken. The RS-CS flag comes to start the timing of P / S conversion of data (timing of sending RD).

The operation in such a configuration is shown in the time chart of FIG. As shown in this time chart,
When the RS ON cell is received, the rise of the terminal clock (terminal CLK) is differentiated to make the condition for turning on the CD (J input of JKFF shown in FIG. 2). Also, CD
The conditions for turning off are: CD flag, cell flag,
And a negative logic OR with the ON condition of the CD (K input of JKFF shown in FIG. 2).

As can be seen from the figure, the CD ON /
OFF is synchronized with the terminal CLK. Regarding the timing of P / S conversion, the rising edge of the RS-CS flag is differentiated to create the timing of P / S conversion, whereby P / S conversion is started and RD is sent out at this timing. .

In this way, when a cell is stored in the cell reception memory 5 by adding the cell storage state to the CD detection state as a condition for turning on / off the CD (while sending RD). Even if the CD OFF information is received, the CD will not be turned OFF. Also, RS-
Since the P / S conversion timing is created for the first time after the CS time comes, an error does not occur in the RS-CS delay time as in the conventional case.

[0025]

As described above, according to the present invention, when the carrier is turned off, the carrier is turned off by referring to the state of the carrier and the count number of the receiving cell. It is possible to prevent cutting. Moreover, since the timing of P / S conversion is created by using the time from the transmission request to the transmission permission as a trigger, an error does not occur in the RS-CS delay time.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of an embodiment of a CD / RD phase adjustment circuit in ATM transmission of the present invention.

FIG. 2 is a circuit block diagram showing details of a CD / RD phase adjustment circuit of the present invention.

FIG. 3 is a time chart showing the operation of the embodiment.

FIG. 4 is an explanatory diagram showing a procedure of conventional RS-CD transmission.

FIG. 5 is an explanatory diagram showing a procedure of conventional RS-CD transmission.

FIG. 6 is a block diagram showing a conventional ATM transmission device.

FIG. 7 is a time chart of each signal when RS-CD transmission is performed using a conventional ATM transmission device.

FIG. 8 is a time chart of each signal when RS-CD transmission is performed using a conventional ATM transmission device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CD detection unit 2 CD register 3 RS-CS timer 4 Cell write controller 5 Cell reception memory 6 Cell number counter 7 Cell reception memory read controller 8 HDLC processing unit 9 CD, RD phase adjustment circuit

Claims (1)

[Claims] 1. An RS-CD transmission device for transmitting data by transmitting a carrier according to a transmission request from a transmitting side by the ATM transmission system, and detecting the carrier at the receiving side to make it receivable. Carrier detection unit (1) for detecting the carrier state from the carrier, carrier register (2) for holding the carrier state detected by the carrier detection unit (1), and storage timing of the carrier stored in the carrier register (2) A timer (3) that counts the time from the transmission request to the transmission permission based on, a cell reception memory (5) that stores the received cell, and a cell that counts the number of cells stored in the cell reception memory (5) Number counter (6), carrier status output from carrier register (2), time output from timer (3), and number of cells By referring to the number of cells output from the counter (6),
An AT including a phase adjusting circuit (9) for adjusting the carrier state and the phase of the received data and for creating a timing for parallel / serial conversion of the received data.
CD and RD phase adjustment circuit in M transmission.