JPH0645447A - Buffer circuit - Google Patents

Abstract

PURPOSE:To provide a semiconductor chip that includes a buffer divided into sub-buffers so that output characteristics may be changed without increases in chip area and manufacturing costs. CONSTITUTION:A semiconductor chip 2 on a board has a plurality of pads 3, in the preceding stage of which are provided sub-buffer circuits 4 that form output buffers, input buffers, or input/output buffers. The sub-buffer circuits 4 include basic components, such as transistors and resistors, for a desired buffer circuit, and these components can be combined by switching. The chip 2 includes a latch type control circuit 6 of a shift register structure. Accordingly, when program data DIN in serial form flow through a pad 3 to an input buffer 5, the data are sequentially transferred to the next stages in synchronism with clock pulses CLK so that the sub-buffer circuit 4 may have desired characteristics. Output buffers 51 connected pads serve to distribute the program data DIN to other circuits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer circuit device incorporated in a semiconductor chip and capable of changing the functions and characteristics of an input buffer circuit, an output buffer circuit, and an input / output buffer circuit for passing signals according to the intended use. .

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit chip, in order to realize a system specification requested by a user, an output buffer having an output characteristic satisfying the specification is designed.

FIG. 19 shows an output buffer satisfying the above specifications.
31 is a circuit diagram of an output circuit connected to each pad 32. FIG.
In this way, the signals D0,
D1 and D2 are connected only to the output buffer 31 having an output characteristic determined based on the specifications, and output from the pad 32.

Further, in a semi-custom integrated circuit represented by a standard cell or a gate array, a plurality of I / O cells (input / output buffers) having arbitrary output characteristics are prepared in advance, and I / O cells according to the specifications are prepared. The O cell is selected and connected to the pad.

FIG. 20 is a second conventional example and is a pattern plan view showing an example of the above semi-custom LSI. The signal line taken out from the customized internal circuit 33 is connected to the pad 35 via the input / output buffer 34.

FIG. 21 is a third conventional example and is a pattern plan view showing the configuration of a programmable logic device (PLD). The PLD has an array pattern 36 in which OR gates and AND gates are preliminarily arranged in an array. An I / O cell 38 having a predetermined output characteristic is connected to the pad 37 to input / output a predetermined signal in the array pattern 36.

After the LSI chip is manufactured, the specification is changed by the user and the function test of the chip is performed. As a result, for example, the load driving force of the output buffer connected to the pad is too large, so that noise is generated and the load driving force is Is too small to meet the speed specifications, which causes problems. In such a case, it becomes necessary to change the output characteristic.

When changing the above output characteristics, as shown in FIGS.
In the configuration of 0, the circuit constants are readjusted so that the predetermined output characteristics are satisfied, and the mask data in the output buffer 31 and the input / output buffer 34 are modified and replaced. This significantly increases the manufacturing cost and development period of the chip.

If the problem as described above occurs also in a semi-custom integrated circuit such as a gate array or a standard cell, another I / O cell which satisfies a predetermined output characteristic is provided.
Since the O cells must be replaced and the mask data needs to be changed, an increase in chip manufacturing cost and development period cannot be avoided.

In a device such as a PLD, I / I that satisfies a predetermined output characteristic near a pad around the chip is previously set.
Since the O circuit is fixedly connected, it is difficult to cope with various output characteristics required for one chip.

FIG. 22 shows a fourth conventional example, which is a circuit diagram prepared in advance by connecting three output buffers 41, 42, 43 in parallel to each output circuit section. Independent control signals are input to the output buffers 41, 42, and 43 from the pad 44 and are controlled from the outside. The signals D0, D1 and D2 given from the inside of the semiconductor chip are output from each pad 48 through the output buffers 45, 46 and 47 whose characteristics are set by the control of the output buffers 41, 42 and 43, respectively.

According to the above structure, even if the above-mentioned problem of changing the output buffer occurs after the chip is manufactured, the output characteristics can be changed to some extent. According to this method, an increase in the development period due to the change of the mask data is avoided, but a pad and an input circuit for receiving a control signal from the outside are individually required, so that the chip area is significantly increased. At the same time, the manufacturing cost is increased.

[0013]

As described above, in the conventional method, the change in the output characteristics caused after the semiconductor chip is manufactured is
There are drawbacks such as correction of mask data, time problem of replacement, large increase of chip area, and increase of manufacturing cost.

The present invention has been made in consideration of the above circumstances, and an object thereof is to easily change the output characteristics generated after the manufacture of a semiconductor chip without increasing the chip area and the manufacturing cost. , To provide a data output device capable of achieving a significant reduction in the development period of a semiconductor chip.

[0015]

A data output device according to the present invention comprises a pad for external connection provided on a semiconductor chip and a plurality of pads provided in the middle of a signal path connecting the pad to the inside of the semiconductor chip in parallel with each other. A sub-buffer circuit connected thereto, a control terminal for controlling the operation of the sub-buffer circuit derived from each of the sub-buffer circuits, a latch type control circuit in the semiconductor chip connected to the control terminal, Program means for controlling the output of the latch type control circuit by a signal external to the semiconductor chip, and controlling the operations of the plurality of sub-buffer circuits to function as one buffer circuit having desired characteristics and the pad and It is characterized by coupling with a signal path.

[0016]

According to the present invention, a plurality of sub-buffer circuits each having a control terminal capable of independently controlling the operation are preliminarily connected in parallel inside the semiconductor chip. By connecting the output of the latch-type control circuit to the control terminal of the sub-buffer circuit, the characteristics of the sub-buffer circuit are electrically programmed by an external signal.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. FIG. 1 is a circuit block diagram showing an outline of a buffer circuit according to an embodiment of the present invention. LSI board
LSI chip 2 is mounted on 1. A plurality of pads 3 for external connection are installed on this LSI chip. A sub-buffer circuit section 4 including an output buffer, an input buffer, or an input / output buffer is provided in the signal path connecting the pad 3 to the inside of the LSI chip 2. In order to prepare a desired sub-buffer circuit, the sub-buffer circuit unit 4 is configured such that a plurality of basic elements such as transistors and resistors are arranged and a combination of these elements can be switch-controlled.

A latch type control circuit 6 is provided in the LSI chip 2. The latch type control circuit 6 has a shift register structure in which individual latch circuits are serially connected. A program signal for determining buffer circuit characteristics is supplied from the latch type control circuit 6 to the sub buffer circuit section 4. Program data DIN is input to the latch type control circuit 6 in order to generate this program signal. Program data DI
N is serial data and is given from the pad 3 provided on the LSI chip 2 via the input buffer 5. The latch type control circuit 6 sequentially transfers the program data DIN to the latch circuit of the next stage in synchronization with the clock signal CLK. The output of the program data DIN to the outside may be transmitted to other circuits via the output buffer 51. At that time, the pad connected to the output buffer 51 becomes a signal extension terminal to another circuit.

Looking at the interface with other devices on the board 1, the TTL driver 211, the CMOS
Driver 212, multi-bit bus line 213, SRAM 214
Therefore, it is necessary to respond to various interface requirements such as function (input, output, input / output) input / output level difference (CMOS / TTL) load difference (driving force). For example, when the specification of the board 1 is changed after the LSI chip is manufactured and it is necessary to change the TTL driver 211 to the CMOS driver 212, as described above, the latch type control circuit 6 to the sub-buffer circuit section 4 is changed by the program data DIN and the clock signal CLK. A program signal for determining the buffer circuit characteristic is supplied to the buffer circuit, and the buffer circuit characteristic of the corresponding sub-buffer circuit section 4 is set to a desired circuit characteristic.

FIG. 2 is a sub-buffer circuit section according to the present invention.
4 is a circuit block diagram showing a main part of 4. FIG. The sub-buffer circuit section 4 is provided corresponding to each pad 3 on the LSI chip 2, and the connection relationship between the basic element grouping section 41 in which a plurality of basic elements such as transistors and resistors are arranged and the combination thereof are switched. The control switch collecting unit 42 is configured to be controllable by control. The control switch assembly 42 is provided with a plurality of program terminals 423 for supplying a program signal to the control switch assembly 42 together with a signal input terminal 421 and an output terminal 422 for chip internal connection. Program terminal 42
3 receives the program signal which is the parallel output from the above-mentioned latch type control circuit 6. This allows LS
It is possible to change the interface specifications after manufacturing the I-chip and set the characteristics of the buffer circuit against variations due to process, voltage, temperature, and the like. The above-mentioned program data DIN and clock signal CLK are input to the pads 3a and 3b, respectively.
Further, the pad 3c has the program data DIN as described above.
Is a pad connected to the output of the final latch circuit sequentially transferred in the latch type control circuit 6, and is used to serially connect the program data DIN to another chip having the same function as this embodiment on the same board. Is a pad provided as a signal extension terminal.

FIG. 3 is a circuit block diagram showing a main part of the latch type control circuit 6 (6-1, 6-2) according to the present invention. LSI chips 2-1 and 2-2 are provided on the same board 1. Latch type control circuit 6-
Each of 1 and 6-2 consists of multiple latch circuits. The parallel outputs of the latch-type control circuits 6-1 and 6-2 are connected to the program terminals of the sub-buffer circuit section 4, respectively. Thereby, the parallel output of the latch type control circuit 6-1 or 6-2 is operated by the program data DIN to electrically program the characteristic of the corresponding buffer circuit, for example, the output buffer. As a result, output buffer 4
Function as one output buffer having desired output characteristics. From the latch type control circuit 6-1
Supply of program data DIN to 6-2 is output buffer 5
1, via wiring 7 on board 1 and input buffer 5. The clock signal CLK is connected via the input buffer 5 to the clock terminals of the latch type control circuits 6-1 and 6-2.

FIG. 4 is a circuit block diagram showing a configuration in which the program data DIN is serially connected to another chip having the same function as this embodiment on the same board by using the signal extension terminal according to the present invention. . An input terminal 101 for the clock signal CLK and an input terminal 102 for the program data DIN are provided on the board 1. The program data DIN is sequentially shifted by the clock signal CLK, and the data held in all the latch type control circuits installed in the serially connected LSI chips 201 to 206 are programmed. As a result, the buffer circuit corresponding to these latch-type control circuits can be freely set to desired characteristics even after the chip is manufactured.

FIG. 5 is a circuit diagram showing a specific structure of the present invention. The programmable output buffer is divided into sub-buffers 4a, 4b, 4c in the sub-buffer circuit section 4. Three 3-bit latch circuits 6a are serially connected to form a latch type control circuit 6. The program data DIN and the clock signal CLK are commonly supplied to the respective latch circuits 6a via the pad 3 and the input buffer 5.

The parallel output of the latch type control circuit 6 is input to each program terminal of the sub-buffers 4a, 4b and 4c. The signals D0, D1 and D2 from the inside of the chip are input to the output buffers 4 whose characteristics are controlled, and the signals Z0, Z1 and Z2 are output via the pads 3.

6 to 11 are specific circuit examples of the output buffer 4 described above. Hereinafter, for convenience, the output buffer configured by the sub-buffer circuit unit 4 is simply referred to as the buffer 4.

First, the circuit example of FIG. 6 will be described. Three
Sub-buffers 4a-1 and 4b- that make up the state buffer
Signals E0, E1, and E2 are input to the independent program terminals of 1 and 4c-1, and the signal CD from the chip
N is input commonly to each subbuffer. The data output is output from the pad 3 since the output terminals of the sub-buffers are commonly connected to the pad 3.

The output current value of the circuit shown in FIG. 6 is determined as follows, for example. The output current value Io of each sub-buffer is 4 mA for 4a-1, 8 mA for 4b-1 and 12 mA for 4c-1.
And combining the signals E0, E1 and E2 with "0" and "1" respectively, the respective sub-buffers 4a-1 and 4b
The operations of -1, 4c-1 are controlled, and the output current value Iot as one buffer 4 can be changed.

FIG. 12 shows the signals E0, E1, and
It is a correspondence diagram showing the output current value Iot of the buffer 4 with respect to E2. For example, when E0 is set to "1", E1 is set to "0", and E2 is set to "1", the sub-buffers 4a-1 and 4c-1 are in the conductive state and 4b-1 is in the non-conductive state. Therefore, the output current value as one buffer 4 is 4 + 12 = 16mA
Becomes

Thus, in the example of FIG. 12, the combination of "0" and "1" of the signals E0, E1 and E2 gives
4mA, 8mA, 12mA, 16mA, 20mA, 24
Buffer in 7 steps of mA and HZ (high impedance)
The output current value Iot of 4 can be changed.

Next, the circuit example of FIG. 7 will be described. The sub-buffers 4a-2, 4b-2, and 4c-2 have a common signal input from the inside of the chip as the signal CDN, and each output is connected to the input side of the transmission gate TG1. The output of each TG1 is pad 3
It is connected to the. Here, EN0, EN1, and EN2 are input to the independent program terminals of each TG1.

In the circuit example of FIG. 7 as well, similar to the configuration of FIG. 6, the output current values of the sub-buffers 4a-2, 4b-2, 4c-2 are designed to be predetermined values and input to the transmission gate TG1. By combining "0" and "1" of the signals EN0, EN1 and EN2 to be output, the output current value as one buffer 4 can be changed.

Next, the circuit example of FIG. 8 will be described. Clocked inverter 4a-3 formed as a sub-buffer
Data input of 4b-3 and inverter 4c-3 are common signals
The CDN is supplied, and the outputs are commonly connected to form the front stage section 4P1, connected to the input of the final stage inverter 4m-1, and the output thereof is connected to the pad 3.

The circuit of FIG. 8 makes it possible to control the output slew rate of the final stage inverter 4m-1 by changing the value of the conductance gm of the front stage section 4P1. . gm value clocked inverter
Design 4a-3 to 3, 4b-3 to 2, and inverter 4c-3 to 1.
The operations of the clocked inverters 4a-3 and 4b-3 are controlled by the combination of "0" and "1" of the signals E0 and E1.

FIG. 13 is a diagram showing the values of gm of the preceding stage section 4P1 for the signals E0 and E1 in the above case. For example, E
When 0 is set to "0" and E1 is set to "1", the clocked inverters 4a-3 cannot be conducted and 4b-3 can be conducted. Therefore, the gm of the front stage section 4P1 which drives the final stage inverter 4m-1 is 2 + 1 = 3.

Thus, in the example of FIG. 13, 4c-3
Gm of 1 is set to 1 and the combination of signals E0 and E1 of "0" and "1" makes it possible to change the gm of the front stage portion 4P1 into four stages of 1, 3, 4 and 6, and thus, Stage inverter
The slew rate of 4m-1 can be controlled in 4 steps.

Next, the circuit example of FIG. 9 will be described. Final stage buffer 4m to which signal CDN from inside the chip is input
The output terminals of the three transfer gates TG1 are commonly connected to the -2 input terminal. Signals EN0, EN1 and EN2 are supplied to the program terminals of each of the three transfer gates TG1.
The input side of TG1 is connected to a capacitance C1 formed between it and the ground voltage GND.

If the capacitance C1 is designed to have a predetermined value, the pre-stage section 4P2 having the above-described configuration has signals EN0, EN1, EN.
With the combination of 2, the capacity of the input terminal of the final stage buffer 4m-2 can be changed. Therefore, similarly to FIG. 8, the output slew rate of the final stage buffer 4m-2 can be controlled according to the set capacity value.

Next, the circuit example of FIG. 10 will be described.
This circuit is a modification of the above-mentioned FIG. 6, and the sub-buffer 4a-
Signals E0, E1, and E2 are input to independent program terminals of 4, 4b-4, and 4c-4, respectively, and the signal TN is separately provided.
A commonly connected program terminal for inputting is provided.
This makes it possible to configure the buffer 4 as an input / output buffer circuit by adding the input buffer IB1. In this case, the signal TN causes all of the sub-buffers 4a-4, 4b-4, 4c-4 to be in a non-conductive state, and their outputs are set to a high impedance state. The input signal from pad 3 is output to the inside of the chip as signal INT via input buffer IB1.

Next, the circuit example of FIG. 11 will be described.
This circuit is a modification of the above-mentioned FIG.
By providing a program terminal on 4m-3, it is possible to configure buffer 4 as an input / output buffer circuit with input buffer IB1. Final stage inverter 4m
The signal TN input to the program terminal of -3 makes the final stage inverter 4m-3 in a non-conductive state and puts its output in a high impedance state. After that, the input signal from the pad 3 is output to the inside of the chip as the signal INT via the input buffer IB1.

14 to 16 are circuit diagrams showing a concrete structure of the latch type control circuit 6 in FIG. 5, respectively. First, the circuit example of FIG. 14 will be described.
Nine flip-flop circuits FF0 are connected in cascade,
It constitutes a 9-bit shift register. Each of these flip-flop circuits FF0 synchronizes with the program data DIN in synchronization with the clock signal CLK commonly input to the terminal CP.
Capture and hold. The 9-bit output is obtained from each independent output terminal Q.

FIG. 17 is a timing chart showing the operation of the circuit shown in FIG. Here, the flip-flop circuit FF0 in FIG. 11 is of a type that takes in data at the rising edge of the clock signal. The 9-bit output terminal at the end of the ninth rising edge of the clock signal CLK indicated by the arrow A has the program data DIN.
The values given by are sequentially transferred to obtain the held output value. The state diagram of FIG. 18 shows a sample of output values obtained according to this timing chart.

Here, the 3-bit unit output of the above-mentioned flip-flop circuit is, for example, the signals E0, E1, to the control terminals of the sub-buffers 4a-1, 4b-1, 4c-1 in FIG. If it is input as E2, the output current of the buffer 4 can be set to a predetermined value according to the combination of "1" and "0" of the signal as shown in FIG.

Next, the circuit example of FIG. 15 will be described.
This circuit is a modification of the circuit shown in FIG. 14, and is a flip-flop circuit FF provided with a preset function and a reset function.
It consists of 1. The signal PRA is commonly input to the preset terminal PR for each 9-bit preset input, and the signal CLA is also commonly input to the reset terminal CL for the reset input. When the signal PRA is "0", all 9-bit outputs are "1" regardless of the program data DIN, and when the signal CLA is "0", all 9-bit outputs are "0".

Next, the circuit example of FIG. 16 will be described.
This circuit has a configuration in which a preset / reset control circuit 11 is further provided in the circuit of FIG. This control circuit 11
Has the function of setting the level of the preset terminal PR and the reset terminal CL to "1" or "0". That is,
The reset terminal PR and the reset terminal CL are the output OU of the control circuit 11.
Pre-selectively connected to T1 and OUT2, controlled by signals ENF and SPC.

FIG. 19 is a state diagram of output setting of the circuit of FIG. The 9-bit output value in FIG. 16 is set according to the states of the signals ENF and SPC. When the signal ENF is "0", the signal DIN
The value input in will be sequentially transferred and set.

FIG. 20 is a circuit diagram in which the circuit configuration of FIG. 16 is applied to the circuit of FIG. An auto clear circuit 12 is provided as an input section of the signal SPC in the circuit of FIG. The auto clear circuit 12 functions so that its output becomes "0" level when the power is turned on.

Thus, when the output level of the flip-flop circuit is determined by the preset / reset input, in the configuration of FIG. 16, each time the power supply of the semiconductor chip is turned off, the signal SPC outputs "1" or "1" at the next turn-on. 0 "
Level input was required, but this is not necessary in the example of FIG. Here, the pull-up resistor Rup connected to the input signal line of the signal ENF to the V _DD level is a 2-input NAND.
The gates ND1 and ND2 are provided so that one input end of the gates is fixed at "1" level. As a result, when the power is turned on, the output from the auto clear circuit 12 can be transmitted to OUT1 and OUT2.

If it is desired to set the output of the latch circuit 6a by the input from the program data DIN, the input of the signal ENF is set to "0" level and OUT1 and OUT2 are fixed to "1" level. At this time, the potential of the signal ENF is sufficiently close to the ground potential, and the resistance value of the pull-up resistor Rup is set so that the current flowing through the pull-up resistor Rup is smaller than the V _DD level.

FIG. 21 is a circuit diagram showing the structure of another embodiment of the present invention, in which the buffer 4 can be set to a desired output characteristic by the ROM 21 in addition to the circuit shown in FIG. That is, the selector 22 is provided in front of each buffer 4. The selector 22 makes it possible to select either the signal of the ROM 21 in which data is programmed in advance by the signal SEL or the signal (output of the shift register) from the above-mentioned 3-bit latch circuit 6a.

In the circuit having the above configuration, the signal LE of the first 3-bit output of the shift register of the latch type control circuit 6 is output.
3 and the data output signal RE3 (3 bits) of the ROM 21 are input to the selector 22, and either one of the 3-bit data is selected by "1" or "0" of the signal SEL. The selected 3-bit data is input to the program terminal which controls the operation of the sub-buffer (not shown) which constitutes the buffer 4.

When the signal SEL is at "1" level, RO
The signal from M21 is selected, and when it is at "0" level, the signal from the shift register is selected. Pull-up resistor Rup to V _DD level connected to the input signal line of signal SEL
Are provided for selecting the signal RE3 of the data from the ROM 21 when the input of the signal SEL is floating. In the example of FIG. 18 as in the example of FIG. 20, when the power is turned on, the data signal RE3 from the ROM 21 is automatically input to the program terminal to the buffer 4. The resistance value of the pull-up resistor Rup is shown in FIG.
It is set to a predetermined value as in the case of the 0th embodiment, and when it is desired to set each output of the latch type control circuit 6 (output of each latch circuit 6a) by the input of the program data DIN, the signal SEL can be set to "0" level. Good.

If a nonvolatile memory such as an E ² PROM capable of erasing and writing data is used instead of the ROM 21, the buffer 4 is set to the output characteristics that meet the system requirements by the input setting of the program data DIN. After that, this setting data can be reset as ROM data.

According to each of the above embodiments, considering the area occupied by the circuit of the present invention, it is significantly smaller than the conventional configuration of FIG. According to the present invention, three output buffers are constructed in the same manner as in FIG. 25. In the present invention, the latch type control circuit 6 and two input pads for inputting a clock signal and program data and two input circuit areas are provided. Is only needed. Therefore, considering the development of the present invention on a chip, the input pad and the input circuit area do not increase, and the number of latch circuits connected to the program terminal for controlling the operation of the output buffer increases according to the number of sub-buffers. There is no significant increase in chip area. That is, the latch control circuit 6 and the sub-buffer circuit section 4 can be secured in an area sufficiently smaller than the pad area. Since the pad area is much larger than this, it is important to minimize the number of pads.

Further, according to FIG. 4, a plurality of LSs are used.
Even on a board system where I chips are configured, the shift registers of the latch type control circuit 6 are serially connected between the chips, so that the output characteristics of the buffers of all the chips on the board can be set as a set of clocks. It can be programmed by the signal CLK of, the signal DIN of the data input. This operation function is a very effective means for evaluating the I / O circuit.

Further, according to each of the above-described embodiments, if the sub-buffer and the latch type control circuit connected in parallel are prepared as independent cells in advance, the present invention can be applied to a standard cell or a semiconductor device such as a gate array. It can be easily implemented in a custom integrated circuit.

[0056]

As described above, by applying the data output device of the present invention, the output of the latch-type control circuit is connected to the control terminal of the sub-buffer provided in advance inside the semiconductor chip, and electrically controlled by an external signal. You can program the characteristics of the subbuffer. As a result, it is possible to meet the request for changing the output characteristic that has occurred after the semiconductor chip is manufactured, without modifying or replacing the mask data or significantly increasing the chip area.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a schematic configuration according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram showing a main part of a first part according to the present invention.

FIG. 3 is a circuit block diagram showing a main part of a second portion according to the present invention.

FIG. 4 is a circuit block diagram showing a configuration of an application example according to the present invention.

FIG. 5 is a circuit diagram showing a specific configuration of essential parts of the present invention.

FIG. 6 is a specific first circuit diagram showing the present invention by taking the configuration of an output buffer circuit as an example.

FIG. 7 is a specific second circuit diagram showing the present invention by taking the configuration of an output buffer circuit as an example.

FIG. 8 is a specific third circuit diagram showing the present invention by taking the configuration of an output buffer circuit as an example.

FIG. 9 is a specific fourth circuit diagram showing the present invention by taking the configuration of an output buffer circuit as an example.

FIG. 10 is a specific fifth circuit diagram showing the present invention by taking the configuration of an output buffer circuit as an example.

FIG. 11 is a specific sixth circuit diagram showing the present invention by taking the configuration of an output buffer circuit as an example.

12 is a signal correspondence diagram for determining an output current value of the circuit of FIG.

13 is a signal correspondence diagram for determining a conductance value of the circuit of FIG.

FIG. 14 is a specific first circuit diagram showing the configuration of the latch type control circuit according to the present invention.

FIG. 15 is a first circuit diagram showing a configuration of a modified example of the circuit of FIG.

16 is a second circuit diagram showing a configuration of a modified example of the circuit of FIG.

17 is a timing chart showing the operation of the circuit of FIG.

FIG. 18 is a signal state diagram obtained according to the timing chart of FIG.

19 is a state diagram of output setting of the circuit of FIG.

20 is a circuit diagram in which the circuit configuration of FIG. 16 is applied to the circuit of FIG.

FIG. 21 is a circuit diagram showing the configuration of another embodiment of the present invention.

FIG. 22 is a first circuit diagram showing a configuration of an output circuit in a semiconductor chip according to a conventional technique.

FIG. 23 is a pattern plan view showing an example of an LSI chip relating to a conventional technique.

FIG. 24 is a pattern plan view showing a configuration of a programmable logic device according to a conventional technique.

FIG. 25 is a second circuit diagram showing a configuration of an output circuit in a semiconductor chip according to a conventional technique.

[Explanation of symbols]

1 ... Board, 2, 2-1, 2-2 ... Semiconductor chip, 3 ... Pad, 4 ... Buffer, 4a, 4b, 4c ... Sub-buffer, 5 ... Input buffer, 6, 6-1, 6-2 ... Latch Mold control circuit, 6a ... Latch circuit.

Claims (9)

[Claims] 1. A pad for external connection provided on a semiconductor chip, a plurality of sub-buffer circuits connected in parallel with each other, provided in a signal path connecting the pad to the inside of the semiconductor chip, and the sub-buffer circuit. A control terminal for controlling the operation of the sub-buffer circuit derived from each, a latch type control circuit in the semiconductor chip connected to the control terminal, and an output of the latch type control circuit as a signal external to the semiconductor chip. And a programming means for controlling the operation of the sub-buffer circuits by controlling the operations of the plurality of sub-buffer circuits to function as one buffer circuit having a desired characteristic to couple the pad and the signal path. apparatus. 2. The shift control structure according to claim 1, wherein the latch type control circuit has a shift register structure having one data input terminal and one clock input terminal for sequentially transferring data in synchronization with a clock signal. Buffer circuit device. 3. The data between the latch type control circuits can be loaded in parallel from the memory data of another ROM or a non-volatile ROM, and at this time, can be selectively loaded directly from the outside. The buffer circuit device according to claim 1 or 2. 4. The buffer circuit device according to claim 1, wherein the latch type control circuit has a set terminal or a reset terminal. 5. The buffer circuit device according to claim 1, wherein the plurality of sub-buffer circuits connected in parallel with each other include transistors each of which can be set to an arbitrary size. 6. The buffer circuit device according to claim 1, wherein an output slew rate of each of the plurality of sub-buffer circuits connected in parallel is changeable. 7. A sub-buffer circuit and a latch-type control circuit, which are connected in parallel to each other, are prepared as independent cells in advance, and a desired circuit is arbitrarily configured by a master slice. Item 3. A buffer circuit device according to item 1 or 2. 8. The latch type control circuit has a shift register structure which operates in synchronization with a clock signal,
2. The buffer circuit device according to claim 1, further comprising one clock input terminal, one data input terminal for sequentially transferring data, and one data output terminal for outputting the transferred data. 9. The data output terminal is a signal expansion terminal for serially connecting to a data input terminal of a semiconductor chip other than the semiconductor chip and having a buffer circuit function equivalent to that of the semiconductor chip. The buffer circuit device according to claim 8, which is characterized in that: