JPH064491A - Data processing memory device - Google Patents

Abstract

PURPOSE:To provide the data processing memory device capable of concentrating on the data processing by shortening the processing time of data transmission by a CPU. CONSTITUTION:This device is composed of a triple-port RAM 1 provided with a first port for writing data, a second port for reading the data and a third port for writing or reading the data, a WC 3 for performing the output to the address bus of the first port, an RC 4 for performing the output to the address bus of the second port, the control for writing the data of the data bus of the first port to the RAM 1 corresponding to the address value of the address bus of the first port, the control for reading the data from the RAM 1 to the data bus of the second port corresponding to the address value of the address bus of the second port, and an RAF controller 2 for controlling the write of the data of the data bus of the port to the RAM 1 corresponding to the address value of the third port or the read of the data from the RAM 1 to the data bus of the port corresponding to the address value of the address bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing memory device, and more particularly to a random access memory having three ports.

[0002]

2. Description of the Related Art FIG. 14 is a diagram showing one form of conventional data parallel processing. In the figure, 1001, 1002, 1
00i is a processing module (1), a processing module (2), and a processing module (i), respectively, and each processing module can operate in parallel and simultaneously. In FIG. 14, when a data block is input to the processing module (1), the processing module (1) performs the processing to be performed by the module and sends the data block that needs to be sent to the next module to the processing module (2). The processing module (2) performs the processing to be performed by the module, and sends the data block that needs to be sent to the processing module (3). Repeat this. Such data processing systems are often found in network protocol processing recently. For example, in a LAN relay device or the like, the processing module (1) has a data link layer of the first network, the processing module (2) has a network layer of the first network, and the processing module (3) has a network of the second network. There is an example in which the layer and processing module (4) processes the data link layer of the second network. Then, a block of data called a data unit moves between these processing modules, and each processing module processes this data unit.

FIG. 15 is a diagram embodying FIG. In the figure, 120 to 122 are CPUs (N-
1) to (N + 1) and 130 to 132 are CPUs, instructions and data used by the CPUs, and Local Memory (N-1) to (N +) for work areas.
1) and 140 to 142 are direct storage access control devices (hereinafter abbreviated as DMA) (N-1) to (N +), respectively.
1) and 150 to 152 are bus transceivers.

The operation of FIG. 15 will be described. The CPU bus between each processing module is connected by a bus transceiver, and the bus transceiver becomes transparent when data is transferred between the processing modules. Now, the processing module (N) will be focused and described. When the data block to be transmitted to the processing module (N-1) is prepared by the processing module (N-1), the processing module (N-1) outputs C.
The PU (N) 121 is notified to the processing module (N) by interrupting the PU (N) 121. CPU (N)
Reference numeral 121 reads out the data from the Local Memory (N-1) 130, and reads the Local Memory.
(N) Write to 131 (DM like the dotted square in the figure
High-speed transfer may be performed using A). CPU (N) 121
While accessing the Local Memory (N-1) 130, the CPU (N-1) 120 is
-1) Bus cannot be accessed. CPU in general
(N) 121 asserts a bus request signal to the CPU (N-1) 120 and asserts CP
Ask U (N-1) to release the bus, read the data block, and then negate the bus request signal (n
A method is adopted in which the bus access right is returned to the CPU (N-1) 120 after erasing. Local
The data block written in the Memory (N) 131 is processed by the CPU (N), and when completed, the CPU
(N) informs the processing module (N + 1) by interrupting the CPU (N + 1).

FIG. 16 is a diagram for explaining the data processing steps of FIG. FIG. 16 will be described. The management of the data block uses a queue as shown in FIG. Further, it is general to mount a multitasking OS as the OS. When there is an interrupt from the processing module (N-1), the data receiving process S10 is activated. The CPU (N) 121 acquires a free buffer from the free buffer queue (S11). Next, the data block is read from the processing end queue of the processing module (N-1) and transferred to the acquired buffer (S12). When the transfer of the data block is completed, this buffer is queued in the processing queue (S13). Finally, the processing module (N-1) is notified of the end of the transfer, and the data receiving process is ended (S14).

When there is a buffer containing a data block in the processing queue, the data processing process S20 is started. The CPU (N) 121 processes the first data block in the processing waiting queue (S21). When the processing is completed, the buffer containing the data block is put in the processing completion queue (S22). Then, the CPU (N + 1) is interrupted to notify the completion of the transmission preparation (S23). Then, the data processing process ends. Processing module (N
When the end of the data block transfer is notified by the interrupt from +1), the data transmission end process S30 is activated. The CPU (N) puts the buffer containing the data block in the empty buffer queue and ends the data transmission end process (S31).

As a data processing memory in each conventional data processing apparatus, the above-mentioned Local Memory is used.
Is common, and in this case, the Local Me of each device is
Since the data transfer between the memories is performed via the CPU Bus, the CPU cannot perform other processing during the data transfer. As another example of the conventional technique, there is Japanese Patent Laid-Open No. 2-61741, which is a system in which a FIFO as a memory is bypassed, data is written in a register, and processing is performed with priority over the FIFO.

[0008]

However, when the data processing required time of the data processing device using the conventional data processing memory as described above is distinguished from the data processing required time, it is actually The time required for the data processing which the data processing device originally should execute is S in FIG.
21 is only the "data processing" time. The other processing time is a time related to data transfer, process switching, data block management, buffer management, and the like. That is, in the series of processing in FIG. 16, the movement of the data block among the empty buffer queue, the processing waiting queue, and the processing end queue is actually carried out by moving the pointer of the start address of the block, and the actual data block Will not be moved. However, as described in the description of FIG. 15, the movement of the data block between the (N-1) process end queue to the (N) process wait queue and the (N) process end queue to the (N + 1) process wait queue. Then the actual data block moves. This time is the overhead time. Further, in FIG. 16, the process is divided into three, and the processing time in the OS for the process switching caused by this is also the overhead time. Furthermore, the time consumed for managing queues and managing free buffers is also overhead time. As described above, the CPU of the data processing device has a problem in that it cannot take enough time to concentrate on the “data processing” that should be originally executed due to the overhead time related to data transmission.

The present invention has been made to solve the above problems, and the CPU of the data processing apparatus reduces the processing time for data transfer, process switching, data block management, buffer management, etc. as much as possible. It is an object of the present invention to obtain a data processing memory device which can concentrate on data processing which the CPU should originally execute.

[0010]

A data processing memory device according to a first aspect of the present invention is used for writing data.
, A second port used for reading data, a random access memory having a third port used for writing or reading data, and a write for outputting an address to the address bus of the first port. A counter, write control means for writing data of the data bus of the first port to the random access memory according to an address value of the address bus of the first port, and outputting an address to the address bus of the second port. Read counter, read control means for reading data from the random access memory to the data bus of the second port according to the address value of the address bus of the second port, and address of the address bus of the third port. The data bus of the port in the random access memory according to the value Or writing data, or from the address bus the random access memory in accordance with the address value of which was a write and read control means reads the data on the data bus of the port.

A data processing memory device according to a second aspect of the present invention is the data processing memory device according to the first aspect, wherein write address setting means for externally setting an arbitrary address value to the write counter is added. is there.

In the data processing memory device according to the third aspect of the present invention, an arbitrary address value of the random access memory is set from the outside based on a control command from the outside,
Alternatively, the pointer to which the address value output by the write counter is set is compared with the address value output by the pointer and the address value output by the read counter, and a match detection signal is output when both address values match. The address value coincidence detecting means is added to the data processing memory device according to claim 1 or 2.

[0013]

According to the first aspect of the invention, the random access memory has a first port used for writing data, a second port used for reading data, and a second port used for writing or reading data. 3 ports. The write counter outputs an address to the address bus of the first port, and the write control means writes the data of the data bus of the first port to the random access memory according to the address value of the address bus of the first port. Write. The read counter outputs an address to the address bus of the second port, and the read control means writes data from the random access memory to the data bus of the second port according to the address value of the address bus of the second port. read out. The write and read control means writes data of the data bus of the port to the random access memory according to the address value of the address bus of the third port, or writes data from the random access memory to the port of the random access memory according to the address value of the address bus. Read the data to the data bus.

In the invention according to claim 2, write address setting means is added to the invention according to claim 1, and the write address setting means externally sets an arbitrary address value to the write counter.

In the invention according to claim 3, a pointer and address value coincidence detecting means are added to the invention according to claim 1 or claim 2. An arbitrary address value of the random access memory is externally set or an address value output from the write counter is set to the pointer based on a control command from the outside. The address value coincidence detecting means compares the address value output by the pointer with the address value output by the read counter, and outputs a coincidence detection signal when both address values coincide.

[0016]

FIG. 2 is a diagram showing an example of connection of processing modules according to the present invention. Three processing modules (N-1),
The connections (N) and (N + 1) are shown. In the figure, 100 to 102 are RAF (Random), respectively.
Abbreviation for Accessible FIFO) (N-
1) to (N + 1) and 110 to 112 are IMCs, respectively.
(Abbreviation of Inter Module Controller) (N-1) to (N + 1), 120 to 112
Are CPUs (N-1) to (N + 1) and 130 to 1 respectively
Reference numeral 32 denotes a CPU, instructions and data used by the CPU, and a local memory for a work area.
(N-1) to (N + 1). Each processing module
The RAF, IMC, CPU and Local Memo
ry. FIG. 3 is a detailed view of the processing module (N) shown in FIG. 2, in which the processing module (N) is centered and the processing modules (N
The connection relationship of signals between −1) and (N + 1) is shown.

The RAF 101 has two features of RAM and FIFO. I have three ports,
The first port is a FIFO data input port, the second port is a FIFO data output port, and the third port is a randomly accessible port. The first port has a data input bus (input), a write signal (input), a FIF
There is an O Full signal (output). The second port has a data output bus (output), a read signal (input), a FIF
There is an O Empty signal (output). The third port has a data bus (input / output), an address bus (input), a write signal (input), and a read signal (input). R
The FIFO data output port of the AF 101 is connected to the FIFO data input port of the RAF 102 of the next processing module. The IMC 111 is a controller that transfers data between RAFs. The meanings of the omitted signal names in FIG. 3 are as follows. DW: Data write signal of Data Write Data Bus (N-1) is shown. DR: Indicates a data read signal to Data Read Data Bus (N). EMP: EMP is asserted when Empty CMP2 is asserted. That is, the processed FIFO is empty. FULL: FULL is asserted when the signal of Full CMP1 is asserted. That is, the FIFO is full.

FIG. 4 and FIG. 5 are diagrams for explaining the operating state of the RAF of FIG. 1, and in FIG. 4, [1] to [12].
12 operating states shown by are shown. Each RAF consists of two, a processing FIFO and a processed FIFO.
One data block can be stored in the IFO. The upper stage of FIGS. 4 and 5 shows the processing FIFO, and the lower stage shows the processed FIFO. The processing FIFO is
The data block read from the processing module (N-1) at the previous stage is transferred to the CPU (N) 12 of the processing module (N).
Access from the port that 1 can access at random,
It is a FIFO to process. The processed FIFO is a FIFO for the processing module (N + 1) in the subsequent stage to read the data block. The processing FIFO is WC
A signal from the (Write Counter) is input, and the processed FIFO receives REP (Read Enable).
e Pointer) and RC (Read Count)
er) is input to each signal. These operations will be described together with the operation of FIG.

FIG. 1 shows a RAF (Random) according to the present invention.
It is a figure which shows the structure of Accessible FIFO. In the figure, 1 is Triple-Port R
AM, 2 is RAF Controller, 3 is Wri
te Counter, 4 is Read Counter
r and 5 are Read Enable Pointers, 6
Is Comparer (1), 7 is Comparer
or (2) and 8 are Data Transceiver. The RAF is composed of 1 to 8 above.

Abbreviations of signal names used in FIG. 1 will be described below. DW: Data write signal of Data Write Data Bus (N-1) is shown. DR: Indicates a data read signal to Data Read Data Bus (N). EMP: EMP is asserted when Empty CMP2 is asserted. That is, the processed FIFO is empty. FULL: FULL is asserted when the signal of Full CMP1 is asserted. That is, the FIFO is full. CPR: CPU Read CPU to Triple-Port RAM and RA
The read request to the register and counter in F is shown. CPW: CPU Write CPU to Triple-Port RAM and RA
Indicates a write request to the register and counter in F. PAW: Port A Write Triple-indicates a write request to the port A of the RAM. PBW: Indicates a write request to the port B of the Port B Write Triple-Port RAM. PBR: Indicates a read request from the port B of the Port B Read Triple-Port RAM.

PCR: Port C Read Triple-Indicates a read request from the port C of the Port RAM. REPW: Read Enable Pointer
Indicates a write request to the Write Read Enable Pointer. REPR: Read Enable Pointer
Read Indicates a read request from the Read Enable Pointer. RCW: Indicates a write request to the Read Counter Write Read Counter. RCR: Read Counter Read Indicates a read request from the Read Counter. WCW: Write Counter Write Indicates a write request to the Write Counter. WCR: Indicates a read request from the Write Counter Read Write Counter. WCUP: Write Counter UP Write Counter is incremented by one. RCUP: Read Counter UP Increases the Read Counter by one. RMP1: Comparator (1) Write Counter + 1 = Read Coun
indicates ter. CMP2: Comparator (2) Read Counter = Read Enable
Indicates Pointer.

Triple-Port RAM 1 of FIG.
Is a RAM that can be accessed from three ports, and there are various ways to realize this, and an example is shown in FIG. FIG. 9 will be described later. This Triple-Port RA
M1 can be asynchronously accessed from three ports.
The Write Counter (abbreviated as WC) 3 is
Generate an address value to store the FIFO input data,
1 is added every time one word of data of the data bus (N-1) is written. That is, one is added at the rising edge of the clock when the WCUP signal is asserted. The value of WC3 can be written and read by the CPU Bus. RAF Controller
2 generates WCW and WCR signals from CPUAddress, CPW, and CPR signals, and thereby CPU1
Writing and reading of WC3 from 21. Read
The Counter (abbreviated as RC) 4 generates an address value for reading the data of the FIFO output, and
1 is added every time one word of data is read to Bus (N). That is, one is added at the rising edge of the clock when the RCUP signal is asserted. And RC4
The value of can be read and written by the CPU Bus. RAF Controller2 is CPU Ad
RCW and RCR signals are created from the address, CPW, and CPR signals, so that the CPU 121 to RC4
Write and read.

Read Enable Point of FIG.
ter (abbreviated as REP) 5 indicates the limit of addresses from which data can be read from the FIFO output port.
That is, the most processing FIFO of the processed FIFO of FIG.
Indicates an address closer to O. The address value stored in this REP5 can be written and read by the CPU Bus. That is, RAF Controller2 is C
R from PU Address, CPW, and CPR signals
Create EPW and REPR signals, which allows CPU1
From 21 to REP5, data writing or data reading is performed. By setting the desired address value in REP5 in this way, the processing FIFO and the processed F
Change the boundary with the IFO arbitrarily and read the Count
The range in which the value of er4 is smaller than or equal to the value of REP5 can be set as the readable range. C
Omparator (1) 6 is Write Count
The value of ter + 1 is compared with the value of Read Counter, and if they match, the CMP1 signal is asserted. This signal thus indicates that the processed FIFO and the processing FIFO are full. Comparator (2)
7 is the value of Read Counter and ReadEna
Compare the values of ble Counter and if they match, CM
Assert the P2 signal. This signal thus indicates that the processed FIFO has been emptied.

Data Transceiver of FIG.
Reference numeral 8 is an interface with the CPU Data Bus. The RAF Controller 2 is a state machine for realizing RAF, and Table 1 shows its state transition table.

[0025]

[Table 1]

When the DW signal is asserted, the RAF Controller 2 asserts PAW and Data.
Data on Bus (N-1) is triple-ported
Write to RAM1, assert WCUP and add 1 to WC3. When the DR signal is asserted, PCR is asserted, the data in the Triple-Port RAM1 is read onto the Data Bus (N), RCUP is asserted, and 1 is added to RC4. RAF Contro
ller2 is CPW, CPR, CPU Address
Decode Bus, assert PBW, PBR and C
Writing and reading from the PU 121 to the Triple-Port RAM 1 are performed. See also RAFControl
ler2 is CPW, CPR, CPU Address
Decode Bus, WCW, WCR, RCW, RC
R, REPW and REPR are asserted and WC3, RC4,
Writing to and reading from REP5 are performed. The signals CW and CR in Table 1 are the following logical product signals. CW = CPW
& RAFSEL, CR = CPR & RAFSEL, where RAFSEL is a signal that decodes the CPU Address Bus and indicates access to the RAF address area. Also, / means a signal inversion symbol, and T
Is true, F is false, & is a logical product symbol, and + is a logical sum signal. Further, when the signal is T, it is said that this signal is asserted, and when the signal is F, this signal is negated. RAF Controller 2 is shown in Table 1
State, Conditions and NEXT S
PA which is an output signal corresponding to each signal state of TATE
Determine the T (true) or F (false) status of W, PBW, PBR, PCR, WCUP and RCUP. Also FULL
The signal is true when the CMP1 signal is true, and the EMP signal is true when the CMP2 signal is true. It should be noted that the first port and the second port described in the claims correspond to PortA, PortC, and PortB, respectively.

The operation of the data processing memory device of the present invention will be described with reference to FIGS. Triple-Po of FIG.
When the data block is empty in the rt RAM1 (operation state [1] in FIG. 4), the WC3 is a processing FIFO.
Data of Input Address, RC4 and REP
5 is processed FIFO data Output Addr
ess is shown. And since the processing FIFO is empty, these Addresses are all equal.
At this time, the signals CMP2 and EMP are asserted (ass
ert) has been done. The CPU 121 knows the value of WC3. N-1 of the processing module (N-1) While EMP is asserted, the processing module (N-
There is no data block to transfer from 1) to processing module (N). N-1 IMC1 when EMP is negated
11 is N-1 DR and DW are asserted, and the data block is transferred from the processing module (N-1) to the processing module (N) (operation states [2] and [3] in FIG. 4).
When the IMC 111 starts the transfer, it sends Int to the CPU 121.
It asserts the error signal and signals the start of transfer.
IMC111 is N-1 The transfer is repeated until EMP is asserted. N-1 When EMP is asserted, it means the end of the data block and IMC 111 ends the transfer.

When the transfer is completed, the IMC 111 sets Int
The error2 signal is asserted to signal the end of transfer.
When the CPU 121 receives the Interrupt2 signal, the CPU 121 receives the Triple-Port RAM from the third port.
1 to process the data block. CP
Since U121 knows the address of WC3 before transfer, it knows the start address of the data block. C
The PU 121 can also start processing of a data block by the Interrupt1 signal and process the data block in parallel with the transfer. This is the case where the CPU 121 can perform processing sequentially from the beginning of the data block, and there is a guarantee that the processing of the data for which the transfer has not yet been completed will not be processed. In this case, the processing is parallelized, which further improves the performance. For example, in the processing of data packets in packet communication, control information is often concentrated at the beginning of the packet, and such parallelization can be expected. When the CPU 121 finishes processing the data block, the CPU 121 writes the last address of the data block to REP5 (operation state [4] in FIG. 4). Then the CMP2 signal is negated and RAF
Controller2 detects this and negates the EMP signal. This signal causes the processing module (N +
1) starts reading this data block.

When the CPU 121 finishes the processing of the data block and the data block exists in the processed FIFO, the CPU 121 waits for writing the last +1 address of the data block to REP5. When all the data blocks have been read from the processed FIFO, the RAF 101 asserts the EMP signal and the IMC1
11 detects this and asserts the Interrupt3 signal. In response to this, the CPU 121 writes the address of the last +1 of the data block to REP5. This final +1 address is also the value of WC3, and the CPU
121 does not directly write this address value to REP5, but RAF Con is instructed by CPU 121.
The controller 2 may write the value of WC3 to REP5. The CPU 121 stores the value of WC3 which is the transfer start address of the next data block.
The IMC111 also detects the assertion of the EMP signal, and the CPU
The processed FI 121 has completed the processing of the data block.
It can be seen that the data has been moved to the FO. Therefore, N
-1 If EMP is asserted, the IMC 111 again processes the next data block in the FIFO for processing.
(Operation state [5] in FIG. 4). There is a case where the data block read from the processing module (N-1) is desired to be discarded by the processing module (N). In this case, after reading is completed, the CPU 121 writes the address before reading the data block into the WC3 (operation state [6] in FIG. 4). Then, the new data from the first port is written on the old data, and the old data is discarded.

There is a case where it is desired to newly create a data block in the processing module (N) and send it to the processing module (N + 1). In this case, the CPU 121 first sets the IMC 11
N-1 for 1 Even if the EMP negates, it is set so as not to be transferred, and the CPU 121 writes the data block from the address indicated by WC3. When the writing is completed, the value of the next address where the writing is completed is substituted into WC3. Next, the CPU 121 writes the last +1 address of the data block to REP5 and restores the IMC 111 to the original state (operation states [10] and [1 in FIG. 5].
1]). Then, the new data is inserted into the processing FIFO. N-1 of IMC111 The function to prevent transfer even if the EMP negates may be that the IMC 111 starts transfer at the same time when the CPU 121 sets it. Therefore, there is a function to confirm whether or not the CPU 121 can set after setting. is necessary.

When it is desired to add data to the rear part of the data block read from the processing module (N-1) by the processing module (N) to make a large data block, after reading the data block into the RAF 101,
WC3 is increased by the added amount. Also, when rewriting REP5, the amount is similarly increased. When it is desired to add data to the beginning of the data block read from the processing module (N-1) by the processing module (N) to make a large data block, the value of WC5 is increased in advance in advance and the processing module (N- Read the data block from 1).

When the hardware RAF is used in this manner, the contents that the CPU needs to process are dramatically reduced. Therefore, the processing time is greatly shortened. This CP
The processing content of U will be described with reference to FIG. FIG. 6 shows R according to the present invention.
6 is a flowchart showing processing steps of a CPU using AF. In FIG. 6, when the data block is written in the processing FIFO, the Interrupt from the IMC 111 is performed.
The processing module is activated by t1 or Interrupt2, accesses RAF2, and performs data processing (S1 in FIG. 6). When this process ends, the processed FIFO
If O is empty (S2 in FIG. 6), and if the result of the determination is YES, that is, if there is no data block in the processed FIFO, the value of the start address WP of the data is entered in REP5 and the processing ends (FIG. 6 S3). The determination result of S2 is NO
In the case of, that is, when there is a data block remaining in the processed FIFO, it waits, and when there are no data blocks in the processed FIFO, the IMC111 generates Interrupt3, so this process is started again, and the value of the start address WP of the data in REP5 To end the processing (S4 in FIG. 6).

In the above description, only one data block can exist in the processed FIFO. However, in general use, it is desirable to use a method capable of queuing a plurality of data blocks in a processed FIFO. FIG. 7 is a block diagram of a processing module (N) capable of queuing a plurality of data blocks. Reference numeral 101P in the figure is an RAF in which a plurality of data blocks can exist, and the IMC 111, the CPU 121, and the Local Memory 131 are the same as those in FIG. FIG. 8 is a diagram illustrating a queue operation state of the RAF of FIG.

The operation of FIG. 7 will be described. In FIG. 7,
1 bit of the data bus of the RAF 101P is assigned as an identifier indicating a delimiter between data blocks and N BND signal. This N The BND signal is "1" at the last word of the data block and "0" at other times. IMC111 is N-1 When EMP is negated, N-1 DR and DW are asserted to transfer the data block from processing module (N-1) to processing module (N). WC3 indicates the last address of the data block. When the IMC 111 starts the transfer, it asserts an Interrupt1 signal to the CPU 121 to notify the start of the transfer. IMC111 is N-1 BN
The transfer is repeated until D becomes "1". N-1 BND
Becomes "1", it means the last word of the data block, and the IMC 111 writes the word and ends the transfer.

When the transfer is completed, the IMC 111 sets Int
The error2 signal is asserted to signal the end of transfer.
When the CPU 121 receives the Interrupt2 signal, the CPU 121 receives the Triple-Port RAM from the third port.
1 to process the data block. CP
Since U121 knows the value of WC3 before data block transfer, it knows the start address of the data block. The CPU 121 can also start the processing of the data block by the Interrupt1 signal and process the data block in parallel with the transfer. This is the CPU 121
In this case, there is a guarantee that the data can be sequentially processed from the beginning of the data block, and that the data of the portion that has not been transferred yet is not processed. In this case, since the data processing is parallelized, the performance is further improved. For example, when processing data packets in packet communication, control information is often concentrated at the beginning of the packet,
Such parallelization can be expected. When the CPU 121 finishes processing the data block, the CPU 121 sends REP5
Write the last +1 address of the data block to.
Then, the CMP2 signal is negated, and the RAF Cont
Roller2 detects this and negates the EMP signal. This signal causes the processing module (N + 1) to start reading this data block.

As described above, the processed FIFO shown in FIG. 7 is allowed to have a plurality of data blocks.
1 can always write the last +1 address of the data block to REP5. In the operation state [5] of FIG. 8, two data blocks (1) and (2) circled in the processed FIFO exist to wait for reading from the next processing module, and a new data block ( 3) is input from the previous processing module (N-1). Other operations in FIG. 7 are shown in FIG.
8 and the operation state of FIG. 8 is the same as that of FIGS. 4 and 5.

FIG. 9 is a Triple-Por according to the present invention.
It is a figure which shows the structural example of tRAM. In the figure, 2
Reference numeral 1 denotes a multiplexer (abbreviated as MUX), which has three Port A, Port B, and Port C address buses, and a triple-port RAM Cont.
It is selected based on the selection signal SEL from the roller 27 and output to the RAM 22. 22 is a RAM; 23 is a data bus selector (abbreviated as Data Bus Sel)
And the data bus from the RAM 22 and the Port
Connection with one of the three data buses via A, Port B, and Port C and determination of its direction are performed based on external selection signals SEL and DIR. Two
4, 25 and 26 are bidirectional Latches, respectively
(A), Latch (B), Latch (C) (Bi-
Dir Latch (A), Bi-Dir Latch
(B) and Bi-Dir Latch (C) are abbreviated)
, And Port A, Port B, and Por, respectively.
Latches data from the t C data bus or data from RAM 22.

Reference numeral 27 in FIG. 9 indicates Triple-Port R.
AM Controller, which is an externally input control signal PAW, PAR, PBW, PBR, PCW, P
Control output signal SEL to MUX21 based on CR, RA
M Write to RAM22, SEL and DIR to D
ATA Bus Sel23, WALE, RAL
E, WBLE, RBLE, WCLE, RCLE, AO
E, BOE, and COE are respectively Bi-Dir Latc
h A24, Latch B25, Latch C26. This Triple-Port RAM Co
The state machine of the controller 27 is shown in Table 2 below.

[0039]

[Table 2]

In Table 2, "1" indicates a true state and "0" indicates a false state.

The meanings of the omitted signal names in FIG. 9 and Table 2 are as follows. CPR: CPU Read CPU to Triple-Port RAM and RA
The read request to the register and counter in F is shown. CPW: CPU Write CPU to Triple-Port RAM and RA
Indicates a write request to the register and counter in F. PAW: Port A Write Triple-indicates a write request to the port A of the RAM. PAR: A read request from the port A of the Port A Read Triple-Port RAM. PBW: Indicates a write request to the port B of the Port B Write Triple-Port RAM. PBR: Indicates a read request from the port B of the Port B Read Triple-Port RAM. PCW: Port C Write Triple-Indicates a write request to the port C of the RAM. PCR: Port C Read Triple-Indicates a read request from the port C of the Port RAM. WALE: Write data Latch Ena
ble for Port A WBLE: Write data Latch Ena
ble forPort B WCLE: Write data Latch Ena
ble forPort C RALE: Read data Latch Enab
le forPort A RBLE: Read data Latch Enab
le forPort B RCLE: Read data Latch Enab
le forPort C AOE: Output Enable for Po
rt A BOE: Output Enable for Po
rt B COE: Output Enable for Po
rt C

An application example in which the data processing memory device according to the present invention is applied to an actual device will be shown below. Application Example 1 FIG. 10 is a diagram showing an application example of the present data processing memory device to a two-port relay device between LANs (local area networks). In the figure, a LAN Controller (A) and a processing module (A) connected to the LAN (A), and a LAN connected to the LAN (B).
It has a Controller (B) and a processing module (B). Each processing module includes two RAFs and IMCs, because each processing module performs bidirectional data transmission / reception as a loop.

The operation of FIG. 10 will be described. Generally, for a packet (packet, a string of binary digits including data and control signals, which is transmitted as a unit of the entire string) flowing on a LAN, as shown in the lower part of FIG. There is a network layer header and data. In addition, the data link layer of the LAN is a medium access control (MA).
C) It has a sub-layer, which includes a MAC destination address, a MAC source address, a control field, a type field and the like. The network layer includes a protocol version number, a header length, a packet length, an upper protocol identifier, a hop number, a network layer destination address, a network layer source address, a header checksum and the like. The relay relays the packet to the other LAN based on these pieces of information. In the case of relaying in the data link layer (generally called Bridge), the relay destination is determined by the MAC destination address and the MAC transmission address. In this case, RAF (A1) 101
At A1, the packet to be relayed from the LAN (A) is passed to the RAF (B1) 101B1,
Those that should not be relayed are discarded.

Relay at the network layer (generally Ro
In this case, it is judged from the network layer destination address whether or not to relay, and RA
It is passed from F (A) 101A1 to RAF (B) 101B1. Items that should not be relayed are discarded. If the checksum calculation result or protocol version number does not match, it is also discarded. In the RAF (B) 101B1, the MA that is more appropriate than the network layer destination address
The C destination address is determined and written in that field, and the MAC address of this relay is written in the MAC source address. Also, the number of hops is increased by one, the checksum (check sum value) is recalculated, a new value is substituted, and the result is sent to the LAN controller (B) 200B.

Application Example 2 FIG. 11 is a diagram showing an application example in which the processing module (B) of FIG. 10 is omitted. Processing module (A) in FIG.
10 has two functions of the processing module (A) and the processing module (B) shown in FIG. 10, and simplifies the hardware.

Application Example 3 FIG. 12 is a diagram showing an example in which the data processing memory device is applied to a multi-port type inter-LAN relay device. In the figure, the processing module (A) receives Sys via a Bus interface (abbreviated as Bus I / F) 210.
It is connected to the tem Bus. And this Syst
From em Bus to processing modules (B), (C),
LAN through each processing module of (D), (E), ...
(B), LAN (C), LAN (D), LAN (E),
…It is connected to the. The processing in each processing module is almost the same as that in the first embodiment. The Bus I / F 210 has a function of arbitrating access to the System Bus from each processing module. Generally, one of the following two methods is adopted for the data block transfer between the processing modules via the System Bus. (1) When the processing module (A) determines that the packet coming from the LAN (A) should be relayed, Sy
All the processing modules other than (A) write it in their RAF, and then determine whether the packet should be sent to the corresponding LAN. (2) When the processing module (A) determines that the packet coming from the LAN (A) should be relayed, which processing module is to be relayed is checked, and the processing module to be relayed at the beginning of the data block. A data block is transferred with an identifier added. Bus I
The / F 210 needs a function of determining whether to receive a data block from the system bus based on the identifier.

Application Example 4 FIG. 13 is a diagram showing an example in which the data processing memory device is applied to a communication control device such as a workstation. In the figure, the Bus I / F 210 and the CPU Bus are matched. Through this CPU Bus, a CPU 220 such as a workstation, a Memory 22
1, Disk Controller 222, DMA2
23, etc. Other Application Examples In the above-mentioned embodiments, only the case of LAN connection is shown, but it can be similarly applied to other public communication networks. Also, ATM
It can also be applied to cells in (asynchronous transfer mode).

[0048]

As described above, according to the present invention, the RAM having the first, second and third ports is provided, and the data of the data bus of the first port is written to the RAM according to the value of the write counter. , The data is read from the RAM to the data bus of the second port according to the value of the read counter, and the third port is capable of writing or reading data to or from the RAM by an arbitrary external address. The processing time required by the CPU in FIG. 6 is shortened as shown in FIG. 6, and as a result, the data processing capacity when applied to a relay device such as a LAN is improved several times to several tens of times.

Further, according to the present invention, since it is possible to set an arbitrary address to the write counter from the outside, a part of the FIFO data in the RAM is discarded or a new data is inserted in the middle of the FIFO data. Has the effect of enabling the modification of the FIFO data.

Further, according to the present invention, an arbitrary address value or an output address value of the write counter is externally set to the pointer, and the value of the pointer is used to distinguish the processed FIFO data from the processed FIFO data. Since this is done, there is an effect that the CPU can protect the data being processed.

[Brief description of drawings]

FIG. 1 is a Random Access according to the present invention.
It is a figure which shows the structure of le FIFO.

FIG. 2 is a diagram showing an example of connection of processing modules according to the present invention.

FIG. 3 is a detailed view of the processing module (N) of FIG.

FIG. 4 is a diagram illustrating operating states [1] to [6] of the RAF of FIG.

5 is a diagram illustrating operating states [7] to [12] of the RAF of FIG.

FIG. 6 is a flowchart showing the processing steps of a CPU using RAF according to the present invention.

FIG. 7 is a configuration diagram of a processing module (N) capable of queuing a plurality of data blocks.

8 is a diagram illustrating a queue operation state of the RAF of FIG.

FIG. 9 is a Triple-Port RAM according to the present invention.
It is a figure which shows the structural example.

FIG. 10 is a diagram showing an example of application of the data processing memory device to a relay device having two ports between LANs.

11 is a diagram showing an application example in which the processing module (B) of FIG. 10 is omitted.

FIG. 12 is a diagram showing an example in which the present data processing memory device is applied to a multi-port type inter-LAN relay device.

FIG. 13 is a diagram showing an example in which the data processing memory device is applied to a communication control device such as a workstation.

FIG. 14 is a diagram showing one form of conventional data parallel processing.

FIG. 15 is a diagram embodying FIG.

16 is a diagram illustrating the data processing step of FIG.

[Explanation of symbols]

1 Triple-Port RAM 2 RAF Controller 3 Write Counter (WC) 4 Read Counter (RC) 5 Read Enable Pointer (RE)
P) 6 Comparator (1) 7 Comparator (2) 8 Data Transceiver 21 MUX 22 RAM 23 Data Bus Sel 24-26 Bi-Dir Latch (A) -Bi-
Dir Latch (C) 27 Triple-Port RAM Contro
ller 100-102 RAF (N-1) -RAF (N + 1) 110-112 IMC (N-1) -IMC (N + 1) 120-122 CPU (N-1) -CPU (N + 1) 130-132 Local Memory (N) -1)
~ Local Memory (N + 1)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location G11C 11/401

Claims (3)

[Claims] 1. A random access memory having a first port used for writing data, a second port used for reading data, and a third port used for writing or reading data, A write counter for outputting an address to the address bus of the first port, and an address value of the address bus of the first port,
Write control means for writing data on the data bus of the first port to the random access memory, a read counter for outputting an address to the address bus of the second port, and an address value of the address bus of the second port in accordance with,
Read control means for reading data from the random access memory to the data bus of the second port, and writing data of the data bus of the port to the random access memory according to an address value of the address bus of the third port, Alternatively, the data processing memory device is provided with a write / read control unit for reading data from the random access memory to the data bus of the port according to an address value of the address bus. 2. The data processing memory device according to claim 1, further comprising write address setting means for externally setting an arbitrary address value to said write counter. 3. A pointer to which an arbitrary address value of the random access memory is set from the outside or an address value output from the write counter is set based on a control command from the outside, and an output of the pointer. 3. The data according to claim 1, further comprising: an address value coincidence detecting means for comparing the address value to be output with the address value output from the read counter and outputting a coincidence detection signal when the both address values coincide. Processing memory device.