JPH0644750B2 - Digital data receiving method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field to which the Invention belongs) The present invention secures a good-quality line to provide one-to-one or one-to-n (n
Is an integer greater than or equal to 2) and is related to the data reception method when digital data transmission is performed between stations. The reception method of polarization plane incidence angle or space diversity and both of them (this is called polarization plane / space diversity) on the receiving side. The S / N of each receiving system is detected on a bit-by-bit basis so that a good S / N channel can be selected, and can be used in any modulation / demodulation system.

(Prior Art) Conventionally, in the data transmission between one fixed transmitting station of 1: 1 or 1: n and an arbitrary number of receiving stations, a shortwave (HF) line is particularly used to secure a large number of operating frequencies, When transmitting a wave, the receiver side uses constant frequency monitor reception and uses a frequency diversity reception method that selects a different optimum frequency depending on time and geographical position by manual or automatic operation, or A method of increasing the transmission power on the side to secure the S / N of the reception electric field is used.
However, with such a method, it is difficult to secure an operating (carrier) frequency, and it is difficult to configure an optimum system because the receiving equipment is complicated and the economic burden is large. Moreover, not only is there a limit to the increase in transmission power, but many effects cannot be expected, and the antenna construction cost is enormous. That is, for example, it is difficult for a plurality of mobile stations moving in a wide area to broadcast from a fixed station to continuously obtain good quality data, and an effective receiving method has been found for a receiving electric field that changes from moment to moment. Nakatsuta.

(Specific object of the invention) In the present invention, no matter how geographically the mobile stations on the receiving side are scattered, the optimum one wave among a plurality of waves is selected to receive the polarization plane incident angle and space diversity. Since it is possible to always compare the S / N bit by bit to receive data, and to perform bit synchronization tracking on a good reception channel side, HF
It is effective in preventing noise interference such as fading and multipaths that occur on the line, and that the noise can be generated even for a short time, and that it can be used with any modulation / demodulation method, improvement of bit error rate and synchronization. The purpose is to be effective in correction, and in particular to ensure that a good quality line is continuously provided to a plurality of mobile stations in a wide area for data reception.

(Structure and Action of the Invention) FIG. 1 shows two examples of a general communication system diagram. (1) in the figure shows a plurality of mobile stations A ₁ , A ₂ , A ₃ , from a fixed station A ₀ . …… A
Multiple operating frequencies assigned to _{n 1} , ₂ , ...
FIG. 1 is a system diagram of a broadcasting format in which digital data are simultaneously emitted simultaneously by _n , and a mobile station selects and receives an optimum frequency. In addition, (2) is full-duplex or half-duplex between two 1: 1 stations.
In the dual communication system diagram, the frequencies used are _m and _n . The data receiving method of the present invention can be applied to both (1) and (2).

FIG. 2 is a block diagram of the fixed station A ₀ of FIG. 1 (1). 2 in the figure
Reference numeral 1 denotes a transmitting terminal, which is a terminal such as a computer or a television typewriter, and outputs a binary coded digital signal to a modulator (MOD) 22. This modulator 22 is a modulator for transmitting a digital code input through a radio line, and particularly for long-distance data transmission by ionospheric propagation such as a shortwave line, frequency division multiplexing in which a plurality of subchannels are arranged in the transmission band. (FDM: Frequency Division Multiplex)
PSK (Phase Shift Keying) or FSK (Frequency Shift Keying) modulation scheme can be used. Further, the symbol rate per sub-channel is limited to 100 to 150 BPS in a short wave line, and when assuming the same line quality, the PSK modulation method is advantageous in consideration of the transmission capacity, but the present invention is not limited to PSK.
It can be used for diversity reception schemes using both FSK and FSK, and both schemes will be explained. However, details of the modulation method will be described later. Reference numeral 23 in FIG. 2 denotes a distributor for transmitting the same data at a plurality of radio frequencies at the same time.
The PSK or FSK analog modulation signal from 2 is distributed to each transmitter of TX _{1 to} TX _n . TX _{1 to} TX _n are transmitters set to 1 wave of ₁ to _n , respectively. A conical, inverted cone, rotating log peri-antenna, etc. are used as the transmitting antenna for each transmitter. (Receiving stations A _{1 to An} include, for example, ships, aircraft, land-based trains, vehicles, etc.) FIG. 3 is a block diagram of the receiving device of each of the mobile stations A _{1 to} A _{n in} FIG. is there. The details of the satellite receiver will be described later with reference to FIG. In Fig. 3, RX ₁ and RX ₂ are receivers, usually two receivers are used, and the antennas that supply the respective inputs are provided at a certain distance, and the propagation path of the input radio wave and the phase of the incident polarization plane are A dual-system diversity reception system is adopted, which utilizes a space that utilizes the difference and the incident angle of polarization. Reference numerals 31 and 32 are demodulators, which convert low-frequency signal outputs from the receivers RX ₁ and RX ₂ into binary digital signals and output them. In the present invention, a PSK or FSK demodulator is used,
Here, the case of PSK demodulation will be described. Now like this 2
The S / N (signal-to-noise ratio) of the system is always measured for the output of each demodulator with respect to the reception input of the system, and the better S / N is selected for each bit. That is, 35 is an S / N comparator that compares the S / N in bit units.While data is being received, the S / N of the demodulated outputs of both systems are constantly compared, and as a result, only the data output of the system with good S / N is obtained. Is sent to the receiving terminal 36 (for example, a puncher, a typewriter, a computer, etc.) by controlling the switch 34.

Fig. 4 shows the spectrum of the modulation signal used for the HF line, which is ₁₀ within the transmission band Δ (eg 3kHz).
Multiple sub-channels of ₁₁ , ₁₂ , ... _n-1 , _n are arranged on the frequency axis to generate PSK or FSK modulated waves with the same or different data for each sub-channel. The structure of these modulated waves and the method of receiving and demodulating will be described below.

[1] In the case of PSK modulation (Figs. 5 to 11) Fig. 5 is a time chart for creating a two-phase PSK modulation signal wave of one of the subchannels.
Is a carrier wave, and (2) is a digital code output from the transmitting terminal at the time of transmission. In this example, a binary code of 010110 ... In this modulation, when (2) is followed by the same code as before (for example, 11 or 00), the phase of the carrier wave does not change at the code change as shown in (3), but the code differs from the previous bit ( 0 → 1 or 1 → 0), the phase is advanced or delayed by π radians. In the waveform of (3) A, B,
The phase changes by π radians at each of the points C and E, and there is no phase change at the point D.

FIG. 6 shows a characteristic of the phase change θ of the receiving side demodulator (detector) vs. voltage output V. With such a characteristic, a digital signal (2) of 1,0 can be detected.

FIG. 7 is a diagram showing a configuration example of a 4-phase PSK modulation circuit. In the case of 2-phase PSK, the phase change with respect to the change of the modulation input code is 0 and π, but in 4-phase PSK, the phase changes in π / 2 steps. . 71 in the figure
Is a carrier wave oscillator, 72 is a two-way distributor of signals, and 73 is an attenuator for level adjustment, and its output L ₁ is the vector L _{1 in} FIG. 7 (2). 75 is a π / 2 phase shifter for delaying the phase by π / 2, and its output L ₂ is represented by the vector L ₂ in Fig. 7 (2), and the phase of L ₁ and L ₂ is π / 2. Only different. 74 and 76 are phase modulators, which perform the phase changes of 0 and π described in FIG. 5 according to the digital signals A and B from the terminal device, respectively. It will be explained below that 4-phase PSK waves are obtained by combining the 2-phase PSK wave outputs of the 74 and 76 with the mixer 77.
Since it is possible to perform modulation by a digital signal for each B channel, the transmission capacity is twice as large as that of the two-phase PSK. Therefore, FDM (Frequency Division Multiplexing) 4-phase P
In SK, the symbol rate per channel is 75 BPS, and if the number of subchannels is 16, the transmission rate is 75 × 2 ×
16 = 2400 BPS.

Here, generation of a 4-phase PSK modulation signal in the mixer 77 will be described with reference to FIGS. 7 (3) to 7 (6). For example, assuming that the modulated input signals to 74 and 76 are as follows: A channel 0101 ... B channel 0011 ... When both A and B are "0", the modulated wave vector of A channel is OP ₁ When the modulated wave vector of the B channel is OP ₂ and this is combined, it becomes OP _{01 in} FIG. 7 (3). Then A
When A is 1, and B is 0, only the A channel changes from 0 to 1, so that only P ₁ advances in phase by π and the combined vector becomes OP ₀₂ as shown in FIG. 7 (4). In Figure 7 (5), A is 0 and B
When is 1, P ₁ is the same as (3), and the phase of only P ₂ advances by π, so the combined modulated wave vector is OP ₀₃ . Similarly, FIG.
In (6), when both A and B are "1", compared with (5), only P ₁ advances the phase by π, so the combined modulated wave vector is OP ₀₄ . As shown in FIG.
A high-speed modulator for the HF line can be obtained by creating a 4-phase PSK wave using the circuit as in (1) and installing this for the number of sub-channels.

Next, the receiving side circuit for the 4-phase PSK wave will be described.
FIG. 8 is a diagram showing an example of the configuration of a receiving circuit for receiving a 4-phase PSK wave of FDM by a diversity system with two receiving systems and outputting data to a terminal device. In the figure, PX ₁ and PX ₂ are receivers of each receiving system, 81 and 82 are distributors, and each receiving system includes a band filter group for distributing the output from the receiver for each sub-channel, CH1 to CH for each receiving system
n, CH21 to CH2n demodulation circuit. One of these sub-channels will be described below. CH1
The part including 85 to 89 and 810 is a circuit forming a differential detection circuit for input data.

Now, the sub-channel of the four-phase PSK wave and the PSK wave of one channel are set as E = Acos (ωt + _i ) ... (1-1). In case of 4 phases Becomes However, n _i is a PC for modulation of both channels A and B
Determined by combining the i-th code of the M code 2
The value code, that is, n _i = 0,1,2,3. Therefore, (1
_I-1 in equation (2) is Therefore, PSK wave E and PSK delayed by one code (bit)
The wave ( _{let's call} it E _d ) become that way. The E _{d of} (1-5) corresponds to the output of the delay circuit 87 in FIG. 8, and the delay amount τ = T (T is a time of 1 bit), which is 1 bit. Furthermore, E is divided into two and one phase is π
When delayed by 1/2, its output E _p is expressed by the following equation {∵cos (θ
−π / 2) = sin θ} The waveform of the output of the π / 2 phase shifter 85 in FIG. 8 is represented by this equation. The waveform of the E _d [pi / 4 phase shifter 88 at [pi / 4 delay when the output E _'d is expressed by the following equation.

Then divide E ′ _d into two and divide them with E and E _p 89 and 81, respectively.
The DC components are extracted by inputting them to the product circuit of 0, and the outputs R ₁ and R ₂ of 89 and 810 are as follows.

Since n _i-1 and n _i are quaternary numbers (0, 1, 2, 3), n _i −n _i-1 is a value of -3, -2, -1, 0, 1, 2, 3. Take 86 is an attenuator for level adjustment, which has the same amount of attenuation as the π / 2 phase shifter 85. Phases n _i , n _i-1
The following table shows the calculation of R ₁ and R ₂ for each value of. However And (1-8) and (1-9) represent the phase and detection output in the case of differential detection.

Now, since n _i −n _i-1 is a quaternary number and takes the above values, −
3, -2, -1 can be read as 1, 2, 3 shown in parentheses. When R ₁ and R ₂ are -1, they are read as 0 when they are 1, and when read as 0, R ₁ and R ₂ are represented by the binary code of 0 and ₁ , and the differential detection is performed as the outputs of 89 and 810. Later output is obtained.

The circuits after 89 and 810 are the parts for performing the sign processing of the differential detection output, 811 and 814 are DC amplifiers, 812 and 815 are integrators,
Numerals 813 and 816 are sampling circuits, and numeral 817 is a switching circuit 1 for switching the sampling circuit outputs of the R ₁ and R ₂ systems and outputting them as one continuous signal.

FIG. 9 is a waveform diagram of each part of the circuits 811 to 817.
(2) shows the output waveform of the product circuit corresponding to one of the 89 subchannels received simultaneously by RX ₁ and RX ₂ of the two receiving systems, and if 1 bit length is T, the symbol per subchannel When the rate is 75 BPS, T = 1 / 7513.3 ms. (3) is the output waveform of the integrator 812 of RX ₁ , and (4) is the S / N circuit of 818. For example, S 1 + N of R ₁ from 89 and R ₂ from 810 are compared, and the high level S / N This is a waveform after the signal is taken out and integrated by the integrating circuit 819. Also, (7) and (8) are the output waveforms of the same integrators 812 and 819 in the RX ₂ system. This integration time and
According to the integration result of (3), it is an important matter of the present invention that the clock for sampling and triggering 1 and 0 of data is synchronized bit by bit for each reception system of RX ₁ and RX ₂ . That is, (5) is a quench pulse of a clock (abbreviated as CK) 1, which determines the integration time per bit, and (6) is a sample pulse of CK2, which determines 1, 0 or S / N for each bit. To do. In the RX ₂ system, CK1 corresponds to CK21 and CK2 corresponds to CK22.

For the S / N judgment of the receiving system, the channel used for the S / N judgment is the same as the signal channel when there is one sub-channel, but when there are multiple sub-channels, that one channel is used for the S / N judgment. Select and judge the overall S / N, and switch the diversity signal selection. In the example of FIG. 8, S / N determination is performed using CH1 and CH21, that is, one subchannel for each receiving system.
(9) is the R ₁ system taken out from the switching circuit 1 of 817, that is, 811
-812-813 system sample signal waveform, switching circuit 817 is R ₁
The system and R ₂ system sample signals are alternately switched and output. When the waveform of (9) is input to the differentiation circuit 821, its output is (1
The conversion point pulse 1 as shown in (0) is obtained.

With this conversion point pulse 1, the crystal oscillator 826 and the frequency divider 82 are
7. Operate the timing generation circuit 828 to generate clocks CK1 and C
Create the timing of K2, CK21, CK22. That is, the bit conversion points are extracted from the received detection output digital signal, and the phase correction of the quench pulse CK1 and sampling pulse CK2 in Fig. 9 (5) and (6) is always performed for each RX ₁ and RX ₂ receiving system. CK1, CK2, CK21, CK22 in FIG. 8 correspond to this. Which bit of RX ₁ or RX ₂ is used is determined by the S / N comparison circuit 830 of both reception systems, and the switching circuit 831 is operated for each bit by the switching selection signal of the result, and either of the reception signals is received. Output the system signal. This will be described in more detail below.

The level is output from the sampling circuit (820 in FIG. 8) at the timing of the sampling clock from the S / N integrated output of each reception system shown in (4) and (8) of FIG. 9, and the S / N comparison circuit 83
Compare and judge with 0, and switch the output of the receiving system with the better one.
A switching signal for outputting from 31 is sent to the switching device 831. Also, in the phase correction of the clock system by the conversion point pulse from the differentiating circuit (821), the switching circuit 829 has a good S / N system so that the bit synchronization is performed by the system having a good S / N for each bit. Signal (the output of 830).
Normally, when performing S / N judgment of 4-phase PSK wave, (3) in Fig. 7
~ As shown in (6), the signal vector is OP
_{Since 01} , OP ₀₂ , OP ₀₃ , and OP ₀₄ are different, if the S / N is good, as shown in FIG. Considering that, the others are noise components due to interference or external noise. Ie
The differential detection output of each system of R ₁ and R ₂ is extracted as the S / N component in the S / N circuit 818 by using the phase angle vs. voltage characteristic as shown in FIG. Integrator 8
Integrate one bit at a time in 19 as shown in (4) and (8) of Fig. 9 above.
The integrated output of the S / N signal is obtained.

Reference numerals 83 and 84 denote code processing circuits for inputting the received sub-channel signals of the receiving systems RX ₁ and RX _{2 in} parallel one bit at a time to perform character synchronization and error correction processing, and the output is a switch B831. It is possible to always output the digital signal by the diversity processing in bit units by the S / N determination signal from the comparison circuit 830.

[2] In the case of FSK modulation (Figs. 11 and 12) Fig. 11 shows the signal spectrum per channel of the FSK modulated wave, where the vertical axis represents the level height, where _01m is the mark frequency and _01s is the space. Frequency. The modulator switches to the mark and space frequencies according to the input binary digital signal to generate a modulated signal. ₀₁ is _01m and _01s
Is the center frequency of. If the S / N on the receiving side deteriorates, _{01m
The 01} component in the noise region common to _01s increases, and the spectrum changes from (1) to (2) in FIG. Therefore, on the receiving side, the difference between the component (S) of _01m and _{01s and} the component ₀₁ (N) is used as S / N for the determination of S / N.

FIG. 12 is a diagram showing an example of the configuration of an FSK-modulated wave receiving side device, which corresponds to FIG. 8 in the case of PSK. RX ₁ and RX ₂ and their respective antennas in the figure constitute two receiving systems similar to those in FIG. Reference numerals 121 and 122 denote distributors that distribute the sub-channel signals received and demodulated by each reception system for each channel, and are composed of band filters for each channel. This output is divided respectively into subchannels to CH2n from CH21 in subchannel, RX ₂ receive system from CH1 in RX ₁ receiving system to CHn, but first will be described of them for the channel CH1. 1
Reference numeral 25 is a common amplifier, and 126, 127 and 128 are bandpass filters for extracting the mark frequency, center frequency and space frequency, respectively. Normally, when arranging about 16 FSK sub-channels in a 3 kHz band, the center frequency is _{0 and} the shift width of ± 45.5 Hz is about 110 Hz with ₀ at the center.
Since sub-channel arrangement as shown in Fig. 4 is performed at intervals,
The bandwidth Δ of these bandpass filters is set to about ± 10 Hz. Reference numerals 129, 130, 131 denote amplifiers, and 132, 133, 134 denote diode detectors, the inputs of which are converted into DC components to obtain detection outputs of a mark signal, a center frequency component and a space signal, respectively. Reference numeral 135 denotes a differential amplifier, which sends mark and space signal components to an integrator 139 via an amplifier 138, where the signal components are integrated bit by bit. Reference numeral 140 denotes the sampling circuit 1, which has a role of extracting a signal from the integrator 139. Reference numeral 136 is an adder for both mark and space signals. The difference between this adder output (signal component) and the center frequency detection output (noise component) is taken by an adder 137, which is used as an S / N signal component for amplification. After amplification at 141, integrator 142
At S, the S / N signal of 1 bit is integrated, and the S / N component is taken out by the sampling circuit 2 of 143. A comparison circuit 145 compares the S / N component (of CH1) of the RX ₁ reception system from 143 with the S / N component of the RX ₂ reception system (for example of CH21) and selects the better reception system. . According to the result, 147 switch 2 is S
Outputting the signal of the receiving system with the better / N as the output signal is the same as in the case of FIG.

In this way, also in the case of FSK modulation, the code processing after diode detection is the same as in the case of PSK modulation, and the timing is exactly the same as in the time chart of FIG. That is, clocks CK1 and C
The phase timing for the quench pulse of K21 and the sampling circuit of CK2 and CK22 is (5) and (6) in the time chart of FIG.
Is the same as. Differentiate circuit 1 from the output of sampling circuit 143
The conversion point pulse 1 as an output is sent to the switching circuit 151. 148 is a crystal oscillator, 149 is a frequency divider, 150
Is a timing generation circuit, and these operations are exactly the same as in the case of FIG. The same applies to the switching circuit 151 for switching to the timing of the reception system with a good S / N in bit units. Reference numerals 123 and 124 denote code processing circuits for inputting the sampling outputs of the RX ₁ and RX ₂ receiving subchannels in parallel, respectively, and performing code processing such as parallel-serial conversion and error correction. The channel code is sent to the switching circuit 147 bit by bit, and if selected here, it is sent to the receiving terminal device.

FIG. 13 is a time chart of data transmission / reception when the present invention is implemented, and particularly shows the case of a broadcast format, (1) and (2) on the transmitting side, and (3) on the receiving side. (1) is the transmitter on-air (ON
-AIR) status, and (2) is transmission data. That is, a synchronization signal (SYNC) is transmitted at the start of transmission, and this synchronization signal is composed of 2 ⁿ -1 (n is an integer of 1 or more) M-series code, and subsequently data (DATA) is transmitted. . An end code (END) is transmitted at the end of the data, which is also composed of an M series code. (3) shows the received data output.
2, …… 11 of which 1 is RX ₁ , 2 is RX ₂ , 3 and 4 are data received from each receiving system of RX ₁
It is output by S / N selection. In this way, by using the received data of one channel in the sub-channel obtained by the polarization plane / space diversity reception method, the S / N is judged in the bit unit, and the one with the better S / N among the received outputs of the two systems. The method of the present invention for selectively outputting is capable of always maintaining good communication quality.

(Effects of the Invention) According to the present invention, particularly when a mobile body including an aircraft having a high moving speed or ships scattered over a long distance receives data transmitted from a fixed station continuously and unilaterally at a plurality of frequencies. It is possible to construct a good quality wireless transmission line with the minimum receiving equipment, and greatly improve the receiving quality of the wireless line where the communication state changed from time to time and continuous good reception was difficult. Improvements, simplification of transmission / reception equipment, improvement of transmission efficiency, etc. are remarkable effects of the present invention.

[Brief description of drawings]

FIG. 1 is a communication system diagram in which the present invention is implemented, FIG. 2 is a transmission system configuration example diagram of a fixed station in FIG. 1, FIG. 3 is a configuration example schematic diagram of a diversity receiving device of a mobile station, and FIG. Is an example of the modulation signal spectrum used in the HF line, FIG. 5 is a time chart for making one-phase two-phase PSK modulation signal wave in the sub-channel shown in FIG. 4, and FIG. 6 is a PSK demodulator Relationship between phase change and output voltage, FIG. 7 is a diagram showing a configuration example of a 4-phase PSK modulation wave generation circuit, and a relationship between a code for generating a PSK signal and a modulation vector, and FIG. Fig. 9 is a waveform diagram of each part of Fig. 8, Fig. 10 is a diagram showing a comparison of the signal component and noise component of a 4-phase PSK wave, and Fig. 11 is an FSK modulated wave. 2 is an example of the signal spectrum of Fig. 12, Fig. 12 is an example of the configuration of the FSK modulated wave receiving side device, Fig. 13
The figure is a time chart of data transmission / reception according to the present invention. A ₀ ... fixed station, A _{1 to} A _n ... mobile station, ₁ to _n ... transmission frequency, △ ... occupied bandwidth, ₁₀ to _{1 n} ... sub frequency, θ ... phase, RX ... receiver , TX …… Transmitter, 21 ……
Transmitter terminal, 22 ... Modulator, 23 ... Distributor, 33, 34 ... Demodulator, 35 ... S / N comparator, 36 ... Switching circuit, 37 ... Control circuit, 38 ... Reception terminal, 71 …… Carrier oscillator, 72 …… Distributor, 73 …… Attenuator, 74,76 …… Modulator, 75 …… π / 2 phase shifter, 77 …… Mixer, 81,82 …… Distributor, 83, 84 ... code processor, 85 ... π / 2 phase shifter, 86 ... attenuator, 87 ... delay circuit, 88 ... π / 4 phase shifter, 89, 810 ... product circuit, 81
1,814 …… DC amplifier, 812,815,819 …… Integrator, 81
3,816,820 …… Sampling circuit, 817 …… Switcher, 81
8 …… S / N synthesizer, 821 …… differentiator, 826 …… Crystal oscillator,
827 …… divider, 828 …… timing generator, 829 ……
Switching device, 830 ... S / N switching device, 831 ... switching device, 832 ... reception control unit, 121, 122 ... distributor, 123, 124 ... code processing device, 125, 129, 130, 131, 138,141 …… Amplifier, 126,1
27,128 …… Band wave detector, 132,133,134 …… Diode detector, 135 …… Differential amplifier, 136,137 …… Adder, 13
9,142 …… Integrator, 140,143 …… Sample circuit, 144,1
46 …… differential circuit, 145 …… comparator circuit, 148 …… crystal oscillator, 149 …… divider, 150 …… timing generator circuit, 151
...... Switch.

Claims (1)

[Claims] 1. Digital data transmission in a broadcast format is performed between a fixed transmission station and an arbitrary number of reception stations, and a plurality of subchannels are arranged within the transmission band of a transmission wave from the fixed transmission station side, and digital data is provided for each subchannel. When transmitting a signal modulated by data, each receiving station is equipped with two sets of antennas and receiving units based on the polarization plane incident angle and space diversity.
The signals are received by the system reception method, demodulated and detected for each sub-channel in each reception system, and each reception system outputs the detection output of one channel among the plurality of sub-channels in S bit units.
/ N signal, the S / N signals of both receiving systems are constantly compared and judged, and only the receiving system with the better S / N is selected and received at the same time. Data and S / N information are extracted by synchronizing the timing clock with the S / N judgment extraction clock,
A method for receiving a data signal, characterized in that a single timing circuit corrects the bit synchronization extraction of the reception to the phase timing with the better S / N and receives the data.