JPH0642120B2 - Encryption circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encryption circuit for maintaining confidentiality of information on a transmission line or a storage medium when transmitting or storing digital information.

(Prior Art) FIG. 8 shows the first document “Cryptography: a new dimension”.
in computer data security, 1982, Jahn Wiley & So
FIG. 3 is a block diagram showing a configuration of an encryption / decryption circuit shown in “issued by ns company”. In this circuit, 64-bit block cipher is used in 1-bit CFB (Cipher Feed Back) mode. The left side of the figure is the encryption circuit and the input terminal 8
Adder 802 modulo 01 and 2 shift register 80
3, 64-bit block encryption unit 804, register 80
It is composed of 5. On the other hand, the right part is a decryption circuit, and the adder 81 modulo the shift register 807, the 64-bit block encryption unit 808, and the registers 809 and 2.
0 and an output terminal 811. 806 is a transmission path.

A bit string of plaintext information is input from an input terminal 801 and encrypted by adding 2 to the leftmost bit of a register 805 modulo 2 in an adder 802 modulo 2. The encrypted bit string is sent to the encryption / decryption unit via the transmission path 806 and the shift register 80
Returned to 3 and accumulated for a certain period of time. The content of the 64-bit shift register 803 is input to the 64-bit block encryption unit 804 and converted into 64-bit data. The converted data is stored in the register 805. Of the 64 bits stored in the register 805, only the leftmost 1 bit is used to encrypt the next input information by the modulo 2 adder. The plaintext information input from the input terminal 801 by repeating the above operation is 1
The data is encrypted bit by bit and transmitted to the decryption circuit via the transmission path 806.

When the encrypted information is received by the decryption circuit via the transmission path 806, the encrypted information is accumulated in the shift register 807 for a certain period of time and is sent to the adder 810 modulo 2. In the adder 810 modulo 2, the encryption information and the leftmost 1 bit of the register 809 are modulo 2 added and encrypted. The encryption / decryption information is output to the output terminal 811. The shift register 807, the 64-bit block encryption unit 808, and the register 809 are the shift register 8
03, 64-bit block encryption unit 804, register 8
The same operation as 09 is performed. 64-bit encryption unit 80
Only when the encryption key set to 4 and the encryption key set to the 64-bit encryption unit 808 are the same, the contents of the registers of the encryption circuit and the decryption circuit match, and the information input from the input terminal 801. The same information as is output from the output terminal 811.

Figure 9 is the second document "A Study on Self-Synchronous Simple Cryptography, 3rd Information Theory and its Application Study Group, 1980".
It is a block diagram which shows the encryption circuit shown by "November". In this circuit, instead of 64-bit block cipher,
An encryption converter (ROM or the like) that incorporates a code pattern corresponding to each encryption key is used. In the figure, 821 is an input terminal, 822 is an adder modulo 2, 823 is a shift register, 824 is a code converter, 825 is a transmission line, and 826.
Is an adder modulo 2, 827 is a shift register, 82
Reference numeral 8 is a code converter, and 829 is an output terminal.

Both of the above circuits can reduce the correlation between plaintext and ciphertext, and even if a transmission line error or loss of synchronization occurs, the synchronization is automatically restored after a time proportional to the length of the shift register elapses. It has features.

(Problems to be Solved by the Invention) However, 64 used in the configuration shown in FIG.
Bit block ciphers (eg, DES) are originally designed with consideration of 64-bit unit encryption,
When it is realized by hardware, it is expensive, and when it is realized by software, there is a problem that a desired throughput cannot be obtained. Further, the configuration shown in FIG. 9 requires a code converter that incorporates a code pattern corresponding to each encryption key, and is practically unrealizable if the number of keys increases or the shift register length increases. There was a problem that it would be possible. For example, if the shift register length is 64 and the encryption key bit number is 64, the code converter is ROM
When configured with, the required storage capacity is 2 ⁶⁴ * 2 ⁶⁴ ≒ 3.4 * 10
It becomes ³⁸ bits.

The encryption / decryption circuit of the present invention solves the above-mentioned problems of the prior art, can be realized with a simple configuration, and does not require a converter incorporating a code pattern corresponding to many encryption keys. The purpose is to propose a digitalization circuit.

(Means for Solving Problems) FIG. 1 is a block diagram showing an outline of the encryption circuit of the present invention.

This encryption circuit includes a flip-flop 102 that stores 1 bit of plaintext information input from an input terminal 101, an output of the flip-flop 102, and a flip-flop 103.
Of the output of the adder 104, a flip-flop 105 storing the output of the adder 104, a feedback path 106 for returning the output of the adder 104 to the shift register 108, and an output of the flip-flop 105. An output terminal 107 for outputting as ciphertext information bits, a shift register 108 with a length of k bits, an encryption key register 109 for storing an encryption key of k bits, and a selector 110 for selecting m bits from the k-bit encryption key. , A selector 111 for selecting m bits from the contents of the k-bit shift register, and an output of m selectors 110 and m.
An adder 112 that adds the output of the selector 111 composed of bits modulo 2 for each bit, a register 113 that stores the output of the adder composed of m bits, and a register 11
A register 114 for storing the output of 3 and an output of the register 113 of m bits and a register 1 of m bits
Code conversion circuit 1 for outputting a 1-bit value from the output of 14
15, an adder 116 for adding the output of the code conversion circuit 115 and the output of the register 117 modulo 2, and an adder 1
Registers 117 and 10 for storing 1 bit of the output of 16
3 and 3.

FIG. 2 shows a block diagram of a decryption circuit corresponding to the encryption circuit of FIG.

This decryption circuit includes a register 202 for storing 1 bit of ciphertext information input from an input terminal 201, an adder 204 for adding the output of the register 202 and the output of the register 203 modulo 2, and an adder 204 A register 205 that stores the output, a feedback path 206 that returns the output of the register 202 to the shift register 208, and an output terminal 207 that outputs the output of the register 205 as a decoded text information bit
, A shift register 208 having a length of k bits, an encryption key register 209 for storing an encryption key of k bits, and a selector 210 for selecting m bits from the encryption key of k bits.
, A selector 211 for selecting m bits from the contents of the k-bit shift register, and a selector 2 consisting of m bits.
An adder 212 that adds the output of 10 and the output of the selector 211 having m bits by 2 modulo 2 and a register 213 that stores the output of the adder having m bits
And a register 214 for storing the output of the register 213
And a code conversion circuit 215 that outputs a 1-bit value from the output of the register 213 of m bits and the output of the register 214 of m bits, and the output of the code conversion circuit 215 and the output of the register 217 are added modulo 2. And an adder 216 for storing 1 bit of the output of the adder 216.

Here, k and m (m <k) are arbitrary integers.

(Operation) The current bit of the plaintext data is encrypted based on the past k bits of the plaintext data in the shift register and the k bits of the encryption key register.

The encryption of each bit of the plaintext data is performed by the selectors 110 and 111, the adder 112, and the registers 113 and 114 for each m bits divided into k / m times. Therefore, if the code conversion circuit for the k-bit encryption key is configured by ROM, ^{22 m} bits may be prepared.

(Embodiment) FIG. 3 and FIG. 4 are an encryption circuit diagram and a corresponding encryption / decryption circuit diagram in the first embodiment of the present invention, respectively. For convenience of explanation, in FIGS. 3 and 4, k = 32, m
However, k and m may be arbitrary integers.

The operation of the decoding circuit will be described below with reference to FIG.
Signals ESK, ES0, ES1, ES2, EC1, EC2, EC3, ERS in the figure
Is generated by an appropriate logic circuit so as to be generated at the timing shown in FIG. 5 from the timing signal ST of the plaintext data and ciphertext data supplied from the outside and the master clock CLK (not shown).

In FIG. 3, plaintext data SDI input from the input terminal 301 is stored in the flip-flop 302 at the rising edge of the timing signal ST. All flip-flops in the circuit diagram change state at the rising edge of the clock.
The output of the flip-flop 302 is added to the output of the flip-flop 317 in the EXOR gate 303, and ST
Is stored in the flip-flop 304 at the trailing edge of.
The output of the flip-flop 304 is output from the output terminal 305 as ciphertext data SDO. The contents of the shift registers 307-1 to 307-8 are shifted right by one bit at the ESK timing. Encryption key data is stored in advance in the key registers 309-1 to 309-8. The encryption for the current bit of the plaintext data SDI is performed by using the past 32 bits in the shift registers 307-1 to 30-8 and the key register 3
This is performed based on 32-bit encryption key data 09-1 to 09-8.

The selection signals ES0, ES1, and ES2 are input to the selectors 308 and 310 in FIG. 3 at the timings shown in FIG. 5, and the shift registers 307-1 to 8-8 and the key registers 309-1 to 309-1 are input.
The eight outputs are selected such that each of them has 4 bits and sequentially makes a cycle. The 4-bit outputs of the selectors 308 and 310 are the exclusive logic gates 311-1 to 31-4.
In, the bits are added bit by bit and stored in the flip-flop 312 at the timing of the signal EC1. The output of the flip-flop 312 is input to the code conversion circuit 314 and simultaneously stored in the flip-flop 313 at the timing of the signal EC1. The output of the flip-flop 313 is input to the code conversion circuit 314. This code conversion circuit is a ROM
Or, it is composed of random logic, and 1 or 0 for 2 ⁸ = 256 possible states of input 8 bits.
Is configured to uniquely output the value of.

The output of the code conversion circuit 314 is added to the output of the flip-flop 315 by the exclusive OR gate 316 and stored in the flip-flop 315 at the timing of the signal EC2.

ERS is a reset signal of the flip-flop 315. E
The output of the XOR gate 316 is also input to the flip-flop 317 and stored at the timing of the signal EC3. The output of the flip-flop 317 becomes the input of the EXOR gate 303.

The above operation is repeated for each bit of the plaintext data SDI, and the plaintext data sequentially input from the input terminal 301 is sequentially encrypted and output from the output terminal 305 as ciphertext data.

The circuit diagram of the decoding circuit is shown in FIG. The timing of each signal is shown in FIG. The operation of the decryption circuit is as follows: the operation of the encryption circuit and that the information input from the input terminal is ciphertext data, that the information output from the output terminal is ciphertext data, and the data returned to the shift register. However, since it is the same except that it is the output of the flip-flop 402 instead of the output of the flip-flop 404, detailed description of the operation is omitted.

That encryption transformation and decryption transformations of this embodiment, the plaintext P _t which is input to the encryption circuit at time t, the ciphertext is input to the decoding circuit R _t, encryption key register 309 and 40
The encryption keys stored in 9 are (e ₁ , e ₂ , ...
· · E ₃₂₎ and _{(d 1, d 2 ····· d} 32), when the transfer function of the code conversion circuit and is F, the output from the ciphertext C _t and decoding circuit is outputted from the encryption circuit Decrypted text P ′
_t can be written as follows.

C _t = P _t F (e ₂₉ C _t-29 , e ₃₀ C _t-30 , e ₃₁ C _t-31 , e ₃₂ C _t-32 , e
₁ C _t-1 ,, ・ ・ e ₄ C _t-4 ) F (e ₁ C _t-1 ,, e ₂ C _t-2 , e ₃ C _t-3 , e ₄ C _t-4 , e ₅ C _{t- 5} , ・ ・ e ₈ C _t-8 ) F (e ₅ C _t-5 , e ₆ C _t-6 , e ₇ C _t-7 , e ₈ C _t-8 , e ₉ C _t-9 , ・ ・e ₁₂ C _t-12 ) F (e ₉ C _t-9 , e ₁₀ C _t-10 , e ₁₁ C _t-11 , e ₁₂ C _t-12 , e ₁₃ C _t-13 , ・ ・ e ₁₆ C _{t -16} ) F (e ₁₃ C _t-13 , e ₁₄ C _t-14 , e ₁₅ C _t-15 , e ₁₆ C _t-16 , e ₁₇ C _t-17 , ・ ・ e ₂₀ C _t-20 ) F (e ₁₇ C _t-17 , e ₁₈ C _t-18 , e ₁₉ C _t-19 , e ₂₀ C _t-20 , e ₂₁ C _t-21 , ・ ・ e ₂₄ C _t-24 ) F (e ₂₁ C _{t t-21} , e ₂₂ C _t-22 , e ₂₃ C _t-23 , e ₂₄ C _t-24 , e ₂₅ C _t-25 , ・ ・ e ₂₈ C _t-28 ) F (e ₂₅ C _t-25 , e ₂₆ C _t-26 , e ₂₇ C _t-27 , e ₂₈ C _t-28 , e ₂₉ C _t-29 , ・ ・ e ₃₂ C _t-32 ) P ' _t = C _t F (d ₂₉ C _{t- 29} , d ₃₀ C _t-30 , d ₃₁ C _t-31 , d ₃₂ C _t-32 , d ₁ C _t-1 , ・ ・ d ₄ C _t-4 ) F (d ₁ C _t-1 , d ₂ C _t-2 , d ₃ C _t-3 , d ₄ C _t-4 , d ₅ C _t-5 , ・ ・ d ₈ C _t-8 ) F (d ₅ C _t-5 , d ₆ C _t-6 , d ₇ C _t-7 , d ₈ C _t-8 , d ₉ C _t-9 , ... d ₁₂ C _t-12 ) F (d ₉ C _t-9 , d ₁₀ C _t-10 , d ₁₁ C _t-11 , d ₁₂ C _t-12 , d ₁₃ C _t-13 , ... d ₁₆ C _t-16 ) F (d ₁₃ C _t-13 , d ₁₄ C _t-14 , d ₁₅ C _t-15 , d ₁₆ C _t-16 , d ₁₇ C _t-17 , ・ ・ d ₂₀ C _t-20 ) F (d ₁₇ C _t-17 , d ₁₈ C _{t -18} , d ₁₉ C _t-19 , d ₂₀ C _t-20 , d ₂₁ C _t-21 , ・ ・ d ₂₄ C _t-24 ) F (d ₂₁ C _t-21 , d ₂₂ C _t-22 , d ₂₃ C _t-23 , d ₂₄ C _t-24 , d ₂₅ C _t-25 , ・ ・ d ₂₈ C _t-28 ) F (d ₂₅ C _t-25 , d ₂₆ C _t-26 , d ₂₇ C _{t- 27} , d ₂₈ C _t-28 , d ₂₉ C _t-29 , ... D ₃₂ C _t-32 ) FIG. 7 is a circuit diagram showing a second embodiment of the present invention. The second embodiment is the key register 3 in the encryption circuit of the first embodiment.
09, the selector 310, the exclusive OR gate 311, the flip-flops 312 and 313, the code conversion circuit 314, the exclusive OR gate 316, and the flip-flop 315 are shared with the decoding circuit and are used for time division. .
The selector 701 selects the selector 308 or the selector 40 depending on whether the signal E / D is high level or low level.
The output of 8 is output to the exclusive OR gate 311. Further, the selector 702 outputs the signal C3 to the flip-flop 317 depending on whether the signal E / D is high level or low level.
Alternatively, it is output to the flip-flop 417. That is, the seventh
The circuit shown in the figure operates as an encryption circuit when the signal E / D is at a high level, and operates as a decryption circuit when the signal E / D is at a low level. Other operations are the same as those in the first embodiment.

(Effect of the Invention) As described in detail above, according to the present invention, the contents of the encryption key register and the contents of the shift register 307 or 407 are added by the EXOR gate 311 or 411, and the signal is input to the code conversion circuit. Therefore, only one code converter pattern is required regardless of the number of keys. Further, since the k-bit data is divided into m bits and input into the code converter every 2 m bits, the number of patterns of the code conversion circuit may be ^{22 m} . As described above, the present invention greatly contributes to simplification of the circuit scale of the code conversion circuit or reduction of the ROM capacity. For example, when the code conversion circuit is composed of a ROM, the ROM capacity may be 256 bits even when m = 4, k = 64 and the encryption key is 64 bits.

Furthermore, according to the present invention, even if complicated division processing and repeated processing bit operations such as 64-bit block cipher are not performed, a slight change in the encryption / decryption key and plaintext information can be performed using simple hardware. It is possible to realize an encryption circuit and a decryption circuit in which a minute change greatly expands to ciphertext information or ciphertext information.

[Brief description of drawings]

1 and 2 are block diagrams shown to explain the outline of the present invention, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a decoding corresponding to FIG. FIG. 5 is a block diagram showing an example of a circuit, FIG. 5 is a diagram showing a signal waveform of each part of FIG. 3, FIG. 6 is a diagram showing a signal waveform of each part of FIG. 4, and FIG. 7 is another embodiment of the present invention. Block diagrams showing examples, FIGS. 8 and 9
The figure is an explanatory view of a conventional technique. 102, 103 ... Flip-flop, 104 ... Adder, 105 ... Flip-flop, 106 ... Return path,
108 ... shift register, 109 ... encryption key register, 110, 111 ... selector, 112 ... adder,
113, 114 ... Flip-flop, 115 ... Code conversion circuit, 116 ... Adder, 117 ... Flip-flop.

Claims (3)

[Claims] 1. A shift register having a length k (k is an integer) and m of the outputs of the shift register having k bits.
A first selector that outputs (m is an integer m <k) bits; a first register that stores k bits of the encryption key; and a second register that outputs m bits of the outputs of the first register of k bits Second selector for storing the output of the first selector and the output of the first selector and the output of the second selector for each bit modulo 2 and the output of the first adder having m bits And the outputs of the second register and the third register for storing the outputs of the second register, and 1
A code conversion circuit that outputs a bit signal, a second adder that adds the 1-bit output of the code conversion circuit and the output of the fourth register modulo 2, and the first adder that stores the output of the second adder 4th register and the output of the 5th register which stores the output of the 2nd adder, and the output of the 5th register and the output of the 6th register are added from the 3rd adder and the input terminal which add the output of the 6th register modulo 2. An encryption characterized in that a sixth register for storing a signal, a seventh register for storing an output of a third adder, and a feedback path for returning the output of the third adder to the shift register are provided. circuit. 2. The encryption circuit according to claim 1, wherein the code conversion circuit is composed of a random logic. 3. The encryption circuit according to claim 1, wherein the code conversion circuit is composed of a ROM.