JPH0639361Y2 - Time axis error signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time axis error signal generation circuit, and more particularly to a time axis error signal generation circuit suitable for use in a servo control circuit for controlling the operation of a circuit or a rotating device in a constant state. Is.

In an information reading device that reads recorded information recorded on a recording medium, a servo circuit for correcting the time axis is provided in order to accurately correct the time axis of a reproduction signal. In particular, the servo circuit is indispensable for reproducing the color video information, but in this case, the phase of the color burst signal of the reproduction information and the phase of the signal to be the reference are compared for each 1H (1 horizontal scanning section) and sampled. Hold is performed, and the time axis of the reproduction signal is corrected by this hold output.

In such a time axis correction circuit, the phase error becomes inaccurate and extremely large due to the dropout of the burst signal due to dropout, the effect of noise in the synchronization signal due to dropout, etc., and this is held by the sample hold circuit. However, the time axis correction operation is disturbed because this is incorrect phase information.
Therefore, color unevenness occurs over several H in the reproduced image.

An object of the present invention is to provide a time axis error signal generation circuit which can hold and output only an appropriate sampling value and eliminate a malfunction of a servo circuit for time axis correction and the like.

A time axis error signal generating circuit according to the present invention is configured to generate a constant period ramp waveform signal and a sampling pulse supplied at a timing corresponding to a time axis information signal included in an input information signal. A time-axis error signal generation circuit for outputting a hold output of the sample-hold circuit as a time-axis error signal, comprising: A comparison voltage generating means (4) for setting a range determined by an upper limit and a lower limit centering on the instantaneous level of the hold output, and the instantaneous level of the constant frequency ramp waveform signal is outside the range, And a prohibiting unit that prohibits the sampling operation of the sample hold circuit.

The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block diagram showing an embodiment of the present invention. Reference numeral 1 is a trapezoidal wave generating circuit for generating a trapezoidal wave having a constant period, for example, 1H period, and a circuit for generating a rising slope portion of the trapezoidal wave. Only the configuration is shown, and the mechanism for generating the falling slope is well known and therefore not shown. Capacitor C ₁ to form the rising slope of the trapezoidal wave
And a current source I that charges the capacitor C ₁ with a constant current.
_{It has 0} and a switch S ₁ that controls ON / OFF of constant current charging, and the sampling pulse (B) has an inverter I ₁
It is applied as a control signal of the switch S ₁ via.
The generation timing, that is, the phase of this sampling pulse (B) corresponds to the phase error information, and the switch S ₁ is controlled to be off during the existence period of this sampling pulse (B) to temporarily charge the constant current to the capacitor C ₁ . Will be stopped. The charge stored in the capacitor C ₁ is discharged at a constant current by a reset pulse (not shown) having a 1H period, so that a falling slope portion of a trapezoidal wave is obtained.

Therefore, the relationship between the sampling pulse (B) and the output (A) of the capacitor C ₁ is as shown in FIGS. 2 (A) and 2 (B), respectively. The output (A) of this circuit 1 is input to the sample hold circuit 2. This sample-hold circuit 2 is composed of a sampling switch S ₂ and a hold capacitor C _2, and this hold output V ₁ passes through a buffer amplifier 3 and a comparison voltage V ₁ + ΔV _{a of a} window comparator 5 and
Input to the comparison voltage generator 4 to form V ₁ −ΔV _b .

The comparison voltage generator 4 outputs the output voltage of the buffer amplifier 3.
And V _1, which consists of the variable resistor VR ₁ and VR ₂ provided respectively between the circuit power source + V _cc and ground, the resistor VR ₁ and V
The voltage of the movable terminal of R ₂ is used as the upper / lower comparison voltage of the window comparator 5. Window comparator 5
Has two level comparators 51 and 52 as shown in the figure, and the sample and hold circuit 2 is used as a signal to be compared.
Input (A) is directly applied. Then, the hold output of the hold circuit 2 becomes the circuit output OUT.

The comparison output (c) of the comparator 5 is input to the gate circuit 6 that gates the sampling pulse (B).
That is, the sampling pulse (B) is the cathode of the diode D _2, also comparing the output (c) are respectively applied to the cathode of the diode D _1, the anode of both diodes D _1, D ₂ is commonly connected wired It constitutes the gate. This gate output is used as a sampling signal for performing on / off control of the sampling switch 2 of the sample hold circuit 2.

The circuit operation of FIG. 1 will be described with reference to the waveforms of FIGS. Now, assuming that the sample-hold circuit 2 holds the voltage level V ₁ at the center of the input trapezoidal wave (A), the upper and lower reference levels of the window comparator 5 are V ₁
+ ΔV _a and V ₁ −ΔV _b , and when the input (A) within the upper and lower limit level range corresponding to the hold output level V ₁ arrives, the high level comparison output is output as shown in FIG. 2 (c). When generated, the gate 6 is opened and the sampling pulse (B) passes through this gate 6 and becomes as shown in (D).
Therefore, the sample hold circuit 2 performs a sampling operation. On the other hand, if the input (A) is outside the upper and lower limit level range, the output (c) of the comparator 5 is at the low level. Therefore, when the phase of the sampling pulse (B) including the phase error information is greatly shifted and the level of the trapezoidal wave (A) at the timing of generation of this sampling pulse is out of the above level range, the gate 6 is closed. Since the sampling pulse (B) is not transmitted to the sample-hold circuit 2 (see FIG. (D)), the sample-hold circuit 2 prohibits the sampling operation and outputs the previous sampling value V ₁ while holding it as it is. Become.

That is, since the input that has changed significantly compared to the previous sampling value contains erroneous information due to dropout or other noise as described above, the input with large changes is not automatically sampled, and Since the value of is output as it is, erroneous information is not transmitted to the servo circuit of the next stage, and therefore, color unevenness of the color reproduction image due to malfunction of the servo circuit is prevented.

In the comparison voltage generator 4 in the circuit of FIG. ₁ , the upper and lower comparison levels are set according to the output level V ₁ of the sample hold circuit 2.
V ₁ + ΔV _a and V ₁ −ΔV _b are configured to change,
In the specific example of the figure, as shown in FIG. 3, when the output V ₁ of the sample and hold circuit 2 has a higher value V ₁ ′, the upper and lower comparison levels are V ₁ ′ + ΔV _a ′, V ₁ ′ − ΔV _b ′ and Δ
There is a relationship of V _a ′ <ΔV _b ′. On the other hand, if the sample and hold output V ₁ is at a lower value of V ₁ ″, the upper and lower comparison levels are V ₁ ″ + ΔV _a ″, V ₁ ″ −ΔV _b ″, and the relationship ΔV _a ′> ΔV _b ′ is established. I understand.

That is, if the sampling value in the normal case of the time axis of the reproduction information, which is the control target of the servo circuit, is the level V ₁ in FIG. 3, in the vicinity of the normal level V ₁ ,
The range of the upper and lower comparison levels has an approximately equal width ± Δ (ΔV _a = ΔV _b ) centered on this level V ₁ , and the input level in this range is regarded as correct information and held while sampling. However, when the hold output level V ₁ gradually shifts upward and downward, ΔV _a ′ and ΔV _a ″ change correspondingly to small and large, and ΔV _b ′ and ΔV _b ″ change to large and small, respectively. , Input information closer to the regular level V ₁ is sampled more. And the input information that is far from the normal level V ₁ is more sampled and blocked, which is convenient.

ΔV _a and ΔV _b that determine the range of the upper and lower comparison levels are
The sample-hold circuit can be set so as to change in various forms in accordance with the type of control target and operating state of the servo circuit in which the sample-hold circuit is used, and the comparison voltage generator 4 may be configured accordingly. .

For example, let us consider a case where the sample hold circuit according to the present invention is used in a so-called spindle servo circuit that controls the rotation of a video disc in the case of reproducing a CLV (constant linear velocity) video disc. In this case, it is necessary to control so that the disk rotation speed constantly changes. Therefore, it is general that the sample-hold level V ₁ sequentially changes from top to bottom (or bottom to top), which corresponds to the magnitude of the disc rotation speed. The fact that the change in the error information is smaller when the disk rotation speed is large and the change in the error information is larger when the disk rotation speed is small is based on the fact that the hold level V ₁
If ΔV _a and ΔV _b at the comparison level are changed to be small or large in accordance with the change of, it becomes possible to perform extremely accurate rotation speed servo.

As described above, the time-axis error signal generation circuit according to the present invention prevents the generation of erroneous time-axis error information with an extremely simple configuration, and therefore, when the time-axis servo control circuit is used, a malfunction occurs. No servo operation is possible. Also,
Since the upper and lower limit levels for level comparison are configured to change according to the previous sampling value, it is possible to operate in an optimum state for the target servo circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is an operation waveform diagram of the circuit of FIG. 1, and FIG. 3 is a diagram for explaining a change in comparison level of the circuit of FIG. Explanation of symbols of main parts 2 …… Sample hold circuit 4 …… Comparison voltage generator 5 …… Window comparator 6 …… Gate circuit

Claims (2)

[Scope of utility model registration request] 1. A waveform generating circuit (1) for generating a fixed period slope waveform signal, and the fixed period slope according to a sampling pulse supplied at a timing according to a time axis information signal included in an input information signal. A time-axis error signal generation circuit for outputting a hold output of the sample-hold circuit as a time-axis error signal, which comprises a sample-hold circuit (2) for sampling the waveform signal and sequentially holding the obtained sample values. A comparison voltage generating means (4) for setting a range determined by an upper limit and a lower limit centering on the instantaneous level of the hold output, and as long as the instantaneous level of the fixed period ramp waveform signal is outside the range. And a time axis error signal including a prohibiting means (5, 6) for prohibiting the sampling operation of the sample hold circuit. Generating circuit. 2. A window comparator (5) for issuing a discrimination signal by discriminating that the instantaneous level of the fixed period ramp waveform signal exists outside the range, and the sampling pulse according to the discrimination signal. The time axis error signal generating circuit according to claim 1, further comprising a gate circuit (6) for preventing the sampling and holding means from being supplied to the sampling and holding means.