JPH0638236B2 - Interrupt control method - Google Patents

Description

The present invention relates to a central processing unit in an information processing apparatus, and particularly to a native mode and an emulation mode.
An interrupt control method in an emulation mode in a central processing unit having two instruction execution states.

[Conventional technology]

With the development of computer systems, not only high-speed processing but also high-level processing is required for computers. Microprocessor (M
In the field of PU as well, very high-level processing is similarly required, and in particular, 32-bit MPU (for example, V6).
The tendency is remarkable also in the field called 0).

One of the advanced processes is an emulation mode (abbreviated as EM) that provides compatibility with conventional software.
This is because when introducing a new architecture, the software assets that have been developed on the old architecture are kept unchanged, and software assets are taken over.
It is an approach that tries to keep it alive. In contrast,
A mode for executing instructions in the new architecture is called a native mode (abbreviated as NM). This approach not only provides a smooth transition to the new architecture, but also allows the old software to continue to be used, allowing the new and old software environments to coexist, thus making the software investment more efficient. Can be utilized.

Not only so-called application programs (applications) but also management programs, that is, operating systems (OS)
There is also a case of itself. That is, it is a software group that provides an execution environment for old programs.

In particular, in an MPU equipped with an EM, it is important how the NM and EM share control of peripheral devices and provide software compatibility. Among them, interrupts that are the basis of peripheral device management are important. Management is the most important.

First, an MPU having an EM has a flag indicating in which execution mode it is currently executing. This is called a mode flag. The execution mode is controlled and displayed by the mode flag. In addition to this, a flag that controls whether the NM interrupt is enabled or disabled, and E
It has two flags that control whether interrupts in M can be enabled or disabled.
The former is called NM interrupt status (abbreviated as NM.IS), and the latter is EM interrupt status (abbreviated as EM.IS).
And They exist in so-called program status words (abbreviated as PSW) that can be referred to by NM and EM, respectively. Native PSW, EM for NM PSW
The PSW for use is called an emulation PSW. NM. I
The S is intended to control the interrupt enable / disable state of the MPU itself, while the EM. IS is intended to display the interrupt enable / disable status in EM.

In general, interrupts can be classified into two types: interrupts for NM and interrupts for EM, but interrupts for NM are EM. NM. I
It is processed according to S. This is because the NM OS is responsible for managing the system. On the other hand, E
The interrupt for M is of a nature that should be notified to EM, but if E
M. If the IS is interruptable, interrupt the execution of the EM instruction, and if the EM. If the IS is not interruptable, the fact that an interrupt has occurred is stored, and the EM. When the IS is in the interrupt enabled state, the interrupt is notified. This is a method generally used in the OS as an asynchronous event notification method.

At this time, the program running on the EM is EM. IS
When you try to control the, you have to emulate that movement in some way. There are three possible methods for this.

As a first method, EM. In conjunction with the interrupt enable / disable state of the IS, the NM. There is a method of setting the IS in the same state. EM. IS emulates the instruction to operate. In other words, if the EM disables interrupts, the NM unconditionally disables interrupts. With this method, however, important interrupt requests to the NM such as timer interrupts may be missed. Comes out. This leaves the control open to the EM, although the NM is responsible for managing operations that have the meaning of changing the execution environment of the system, such as controlling interrupts to the MPU. This is a problem that occurs because Therefore, NM. IS
EM. It cannot be changed in conjunction with IS.

As a second method, NM. The EM. Execute instructions in EM to operate IS. That is, EM. Although the state of IS changes depending on the instruction execution, NM. There is a way to keep the IS state unchanged. This method has a problem that the EM does not know when to accept an interrupt. Now, EM. IS
While the EM is moving in the interrupt state, the execution of the instruction causes the EM. Assume that the IS has been disabled. After this,
When an interrupt request to the EM is issued to the MPU, it is assumed that the EM is running in an interrupt-disabled state, so the NM OS does not interrupt the EM instruction execution sequence. , EM is recorded only when an interrupt request is generated, and control is returned to the EM instruction execution sequence. The problem is the subsequent movement. In EM, EM. The IS may return to the interrupt-enabled state, but it is not possible to notify the OS of the NM when it is returned. Because, in EM, EM. When the EM. This is because it is not possible to determine whether the IS has been enabled to interrupt, and therefore the NM OS cannot notify the EM that there is an interrupt request.

As a third method, EM. There is a method in which when an instruction is executed without emulating an instruction for operating the IS, a trap is generated in the NM and the instruction is returned. In this method, since the control of the interrupt can be controlled by the software of the NM, the above problem does not occur and the OS of the NM can be completely controlled.

In the conventional emulation, EM. The third method in which the execution of the instruction for operating the IS is regarded as privileged instruction processing without emulation and the processing is returned to the NM as an exception has been adopted.

[Problems to be solved by the invention]

In the conventional interrupt method in the emulation mode described above, if the program running on the EM is not so frequent E
M. If the IS is not controlled, it is not necessary to worry about the performance degradation of the emulation, but in processing such as keyboard input, the EM. In some cases, the IS is controlled and the interrupt enable / disable control is repeated. If you try to run such a program with EM,
Since exceptions occur frequently and many state transitions from EM to NM occur, there is a drawback that efficient emulation cannot be performed.

[Means for solving problems]

The interrupt control method of the present invention has two instruction execution states, a native mode and an emulation mode, a first flag indicating an interrupt enable / disable state in the native mode, and an interrupt enable / disable in the emulation mode. In the interrupt control method, which has a second flag indicating the state of, and accepts an interrupt in accordance with the first flag when an interrupt request occurs, the interrupt pending state of the emulation mode can be indicated and can be referred to from the emulation mode. If an interrupt request to the emulation mode is made when the second flag has a flag and the second flag indicates that interruption is not possible, the first flag
If the flag of interrupt is enabled, the step of accepting the interrupt, the step of setting the interrupt pending flag so that only the interrupt request in the actual emulation mode is held, and only this interrupt request is stored, and then If the interrupt pending flag is set when the program running in emulation mode operates the second flag to change from interrupt disabled to interrupt enabled, it means that an emulation mode interrupt request was issued. And a detecting step.

[Action]

Therefore, in EM, EM. When the instruction for controlling the IS is executed, it is possible to detect whether or not there is an interrupt request for the EM depending on whether or not the pending flag is set, so that it is not necessary to trap in the NM every time.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a main part of a central processing unit which is a first embodiment to which an interrupt control system in an emulation mode of the present invention is applied, and FIGS. 2 (a) and 2 (b) respectively show the first part. Native PSW 120 and emulation PSW 130 provided in the central processing unit 100 shown in the figure.
FIG. 3, FIG. 3 and FIG. 4 are flowcharts showing the operation of each part in response to an interrupt.

The central processing unit 100 has a bus interface 103 connected to a system bus 120 composed of an address bus and a data bus, and a microprogram sequencer 104 which starts an interrupt process according to an interrupt request when an interrupt request is input to an interrupt request terminal 101. And a microprogram memory 105 storing a microprogram executed by the microprogram sequencer 104.
And 32-bit native PSW120, emulation PSW130, register, ALU
The execution unit 106 is a data path including resources such as (not shown).

The native PSW 120 has a mode flag 110 for controlling a transition state between a native mode (hereinafter referred to as NM) and an emulation mode (hereinafter referred to as EM) as shown in FIG.
Native mode interrupt status 111 (hereinafter referred to as NM.IS) indicating a disabled state and being a flag for controlling interrupts.
The mode flag 110 is a bit 26 to a bit 31 of the native PSW 120 (hereinafter, the bit is referred to as B), an instruction execution pending flag IP, a single step trap pending flag TP, and an interrupt. Stack in-use flag I
S, emulation mode flag EM, asynchronous task trap processing flag ATA, and asynchronous system trap processing flag ASA, and B16 to B18 are NM.
IS111 has a single-step trap enable flag TE, an address trap enable flag AE, and an interrupt enable flag IE. B8 to B12 have floating point precision loss exception flag FRP, floating point underflow exception flag FUD, and floating point, respectively. An overflow exception flag FOV, a floating point division by zero exception flag FZD, and a floating point invalid operation exception flag FIV. B1 to B4 are a zero flag Z, a sine flag S, an overflow flag OV, and a carry flag CY, respectively. Bits are reserved fields.

In the emulation PSW 130, as shown in FIG. 2B, B8 to B10 of the emulation PSW 130 are emulation mode interrupt status 113 (hereinafter referred to as EM.IS113), and B8, B9, B10.
Are single step trap enable flags BRK,
These are an interrupt enable flag IE and a transfer direction control flag. B0, B2 and B4 are a carry flag CY, a parity flag P and a lower carry flag AC, respectively, and B6, B7 and B11 are a zero flag Z, a sign flag S and an overflow flag V, respectively. B25 is an interrupt pending flag IRP which plays an important role in this embodiment. Also, "-" is the native mode P
It is a reserved field as in SW200.

Next, the operation of this embodiment will be described with reference to FIGS.

When an interrupt request is input to the interrupt request terminal 101,
NM. It is checked whether the interrupt enable flag IE of IS111 is set or not and it is determined whether or not the interrupt is possible (step 11). If the interrupt enable flag IE is not set, the interrupt is not accepted. If the enable flag IE is set, the interrupt is accepted. (Step 12) Then, it is judged whether or not the instruction is being executed by the NM (Step 13).
When the NM determines that the instruction is being executed, the NM interrupt processing routine is executed (step 14) and the process returns to step 11. If it is determined in step 13 that the EM is executing the instruction,
EM. It is determined whether or not the interrupt enable flag IE of the IS 113 is set, and it is determined whether or not the interrupt is possible (step 15). If the interrupt is possible, preparation is made so that control can be passed to the interrupt processing routine in the EM (step 16), while the program of the EM is EM. The IS 113 is operated to make it in an interrupt-disabled state (step 17). Step 17
At, the EM program executes the instruction without trapping to the NM. When step 17 ends, N
The interrupt accepted by M is transferred to the control of the interrupt processing routine by EM (step 18), and the process returns to step 11. If the interrupt cannot be made in step 15, for example, if another interrupt request is generated after step 17, the NM follows the interrupt control state of the NM regardless of the interrupt control state of the EM.
The state transition of is performed and the interrupt is accepted. The NM interrupt processing routine is started. At this time, the mode flag 110
Is running on the NM. It is assumed that this interrupt is an interrupt request to the EM. However, since the EM executes the instruction in the interrupt-disabled state in step 17, the instruction execution of the EM cannot be interrupted and the control cannot be transferred to the interrupt processing routine of the EM.

Therefore, the interrupt pending flag IRP of the emulation mode PSW300 is set, the presence of an interrupt request to the EM is recorded, and the process returns to step 11. From NM, it returns to EM as it is. Mode flag 1
10 is being executed by EM. The EM resumes instruction execution from where it was interrupted.

After step 18, the EM executes the instruction and determines whether the EM is trying to enable interrupts (step 2
1), EM. IS1
Interruption is disabled for step 13 (step 22), and the process ends.

If the interruption is enabled in step 21, it is determined whether or not the interruption pending flag IRP is set (step 23). When it is determined in step 23 that the interrupt pending flag IRP is not set, the process proceeds to step 22 and ends, and the interrupt pending flag I
If it is determined that the RP is standing, the EM. The IS 113 is enabled for interruption (step 24) and is trapped in the NM (step 25). In step 25, the NM analyzes the interrupt request to the EM, and when there is an interrupt number and a plurality of interrupt requests, the NM performs an ordering process to find the interrupt processing routine of the EM to which control is to be transferred, and then the necessary information is provided. The stack is stored in the EM stack and the control is transferred to the EM interrupt processing routine (steps 26 to 28).

It should be noted here that the interrupt enable / disable state of the actual processor is NM. According to IS111. That is, the interrupt pending flags IRP and EM. IS113 represents the intention of the program operating in the EM without controlling the interrupt state of the processor.

FIG. 5 is a block diagram showing the main part of a central processing unit according to the second embodiment of the present invention, and FIGS. 6 (a) and 6 (b) are respectively the central processing unit 200 of FIG. Native PSW 220 and emulation PSW 23 provided
An explanatory diagram showing the contents of 0, FIG. 7 and FIG. 8 are flowcharts showing the operation of each part in response to an interrupt.

This embodiment is different from the first embodiment in that a field for holding a pending interrupt request level 114 (hereinafter referred to as IRL 114) is secured in B16 to B23 of the emulation PSW 230. IR
L114 is for instructing to which interrupt request level the interrupt when the pending flag IRP is set, that is, to which interrupt processing routine in EM the control is transferred. The rest of the configuration is similar to that of the first embodiment, and will be omitted.

Next, the operation of this embodiment will be described.

Steps 31, 32, ..., 39 are the same as steps 11, 12, ..., 19 of Fig. 3, respectively, and therefore their description is omitted. After step 39 is completed, the interrupt level is set in the IRL 114 and the process returns to step 31. Steps 41, 42, ..., 44 are step 2 of FIG. 4 respectively.
The description is omitted because it is the same as 1, 22 ,. When step 44 ends and the EM state becomes interrupt enabled, it is detected that the interrupt request is pending by referring to the interrupt pending flag IRP, and EM.
The IS 213 is disabled for interruption (step 45). When step 45 is completed, control is transferred to the corresponding interrupt processing routine according to the interrupt level indicated by the IRL 114 (step 46), and the process ends. In step 46, the NM is not trapped and the interrupt level indicated by the IRL 114 is followed.

As in the first embodiment, it should be noted that the actual processor interrupt enable / disable state is N.
M. According to IS211. That is, IRP and EM. IS213 does not control the interrupt state of the processor, but represents the intention of the program operating in EM.

〔The invention's effect〕

As described above, the present invention has the following effects by providing the interrupt pending flag and detecting whether or not there is an interrupt request in the emulation mode depending on whether or not the interrupt pending flag is set in the emulation mode.

(1) EM interrupt control flag EM. EM controlling IS
Since it is not necessary to trap the instruction execution in the NM every time, the emulation can be speeded up.

(2) An EM that has enabled interrupt requests to the EM
The overhead to notify to becomes small.

[Brief description of drawings]

FIG. 1 is a block diagram showing the main part of the central processing unit of the first embodiment to which the interrupt method in the emulation mode of the present invention is applied, and FIGS. 2 (a) and 2 (b) are respectively the center of FIG. Explanatory diagram showing the contents of the native PSW 120 and the emulation PSW 130 of the processing device 100, FIG.
FIG. 4 is a flow chart showing the operation of each part in response to the interruption in FIG. 1, FIG. 5 is a block diagram showing the main parts of the central processing unit of the second embodiment, and FIGS. 6 (a) and 6 (b) are respectively Explanatory drawing showing the contents of native PSW 220 and emulation PSW 230 of central processing unit 200 in FIG.
FIGS. 8 and 9 are flowcharts showing the operation of each part in response to the interruption shown in FIG. 100, 200 ... Central processing unit, 101 ... Interrupt request terminal, 102 ... System bus, 103, 203 ... Bus interface, 104, 204 ... Micro program sequencer, 105, 205 ... Micro program memory, 106, 206 ... Execution unit, 120, 220 ... Native PSW, 130, 230 ... Emulation PSW.

Claims (1)

[Claims] 1. A first flag which has two instruction execution states, a native mode and an emulation mode, and which indicates an interrupt enable / disable state in the native mode,
In an interrupt control method that has a second flag indicating an interrupt enable / disable state in the emulation mode, and that accepts an interrupt in accordance with the first flag when an interrupt request occurs, indicates an interrupt pending state in the emulation mode, A step of accepting an interrupt if the first flag has an interrupt request when there is an interrupt request to the emulation mode while having an interrupt pending flag that can be referred to from the emulation mode and the second flag indicates that interrupt is disabled; , Interrupt processing in the actual emulation mode is suspended,
At the step of setting the interrupt pending flag so that only this interrupt request is stored, and when the program running in emulation mode next manipulates the second flag to change from interrupt disabled to interrupt enabled And a step of detecting in the emulation mode that there is an interrupt request to the emulation mode when the interrupt pending flag is set.