JPH0637808A - X. 25/x. 75 layer 2 processor - Google Patents

Abstract

PURPOSE:To improve the date link processing reliability of a device which performs the termination processing of the X. 25 and X. 75 layers 2 by preventing the omission and the double feed of an I frame when a link is decided again after the occurrence of a fault. CONSTITUTION:A CPU 4 of a layer 2 processor 1 controls a layer 2 terminating circuit 3 to add the signal identification sequence numbers counted in a memory 5 for transmission of an I frame and to sample the signal identification sequence numbers added from a device of the opposite party for reception of the I frame. Then the CPU 4 receives a global address frame that designated a specific address from the device of the opposite party and then reads the signal identification sequence number out of an information field to sent again the I frame to which the read sequence number is assigned.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to packet switching processing, and more particularly to CCITT Recommendation X.264. 25 and X. 75 Layer 2 processor.

[0002]

2. Description of the Related Art Conventional CCITT Recommendation X. 25 and X.
The layer 2 processing device of 75 has no way to know how far the partner device is receiving after the link is disconnected and set again, and discards or retransmits the I frame whose partner device is unknown whether it is receiving or not. Was. Therefore, X.X. which requires particularly high reliability such as international communication. 25 and X. The 75 Layer 2 processor supported a multi-link procedure to control multiple links, allowing the data to be transferred exactly.

[0003]

In this conventional layer 2 processing device, even if the data link is restored after the data link was disconnected due to a temporary failure, etc. Regarding the I frame for which the response of No. has not been returned, data loss may occur if the frame is discarded, and double data transmission may occur if the frame is retransmitted. Therefore, there is a problem that the call is disconnected or the call setup fails.

In order to avoid this problem, when the multilink procedure is used, there is a drawback that the layer 2 processing device becomes complicated.

[0005]

SUMMARY OF THE INVENTION The X. 25 or X. 75 layer 2 device is based on CCITT Recommendation X.75. 25 and X. For the global address frame that performs the layer 2 termination processing of 75 and has a global address in the address field, which is pre-arranged with the communication partner device different from the unique address, the data following this address field is used as information. It has a layer 2 terminating circuit for transmitting and receiving information as a field and means for creating a signal identification sequence number indicating the transmission order of transmission frames, and controls the layer 2 terminating circuit based on the control of a host device. Information is transferred between the device and the layer 2 termination circuit, and the signal identification sequence number is added when transmitting an I frame, and the signal identification sequence number added by the partner device is extracted when receiving an I frame to ensure transparency of the information transfer. And at the end of the I-frame retransmission request When the global address frame having the signal identification sequence number of the I frame added by the partner device in the information field is transmitted, and when the global address frame is received, the I frame to which the designated signal identification sequence number is assigned is retransmitted. Central processing unit means.

[0006]

The present invention will be described below with reference to the drawings.

FIG. 1 shows an X. The block block diagram of a 25 layer 2 processing apparatus is shown. Here X. 25 layer 2 processing devices (hereinafter referred to as layer 2 processing devices) 1 and 11 form a pair to have a redundant configuration, and the layer 2 processing device 1 is in an active state and actually exchanges frames, and is in a standby state. The device 11 has a frame storage and control memory (hereinafter memory) 15 in which the same contents as the frame storage and control memory 5 in the act layer 2 processing device 1 are written. On the other hand, the layer 2 processing devices 21 and 31 have the same configuration as described above, and the device in the active state is the layer 2 processing device 21 and the device in the standby state is the layer 2 processing device 22. Central processing unit for controlling the layer 2 termination circuit in the layer 2 processing device 1 in the active state (hereinafter referred to as central processing unit)
4 adds “1” to the value of the 1-byte counter stored in the memory 5, and the value of the counter after this addition is added to the memory 5
It is added to the end of the area in which the information of layer 3 to be transmitted is written. Then, the I-frame transmission command containing the address in which the layer 2 information to be transmitted is written is issued to the layer 2 termination circuit 3. The layer 2 termination circuit 3 generates the header part of the layer 2 frame, reads the information field of the I frame from the memory 5 of the buffer according to the instruction, and sends it to the layer 1 termination circuit 2 as a frame. The layer 1 terminating circuit 2 receives the act / standby information of the partner device as received data, selects the line 41 connected to the layer 2 processing device 21 of the act, and selects the line 41 from the layer 2 terminating circuit 3. Send out the frame. The layer 1 termination circuit 22 of the layer 2 processing device 21 on the reception side sends the layer 2 information received from the act side to the layer 2 termination circuit 23, and the layer 2 termination circuit 23 writes only the information field in the memory 25, The I-frame reception report is sent to the central processing unit 24 for controlling the termination circuit. After this, the central processing unit 2 deletes the added counter and transfers it to the higher-level device (layer 3 control central processing unit). At this time, the information written in the memory 25 is simultaneously written in the standby memory 35. Further, in the opposite way, the I frame is similarly sent from the layer 2 processing device 21 to the layer 2 processing device 1.

FIG. 2A shows a newly defined field format of an I frame, and FIG. 2B shows a newly defined field format of a global address frame.

Now, assuming that the lines 41 and 42 have failed, the act layer 2 processing device 21 shifts the act state to the layer 2 processing device 31 that can normally communicate with the partner device. Thereafter, the central processing unit 34 for controlling the layer 2 termination circuit
Issues a command to the layer 2 termination circuit 33, and the line 43
A link is established with the layer 2 processing device 1 via. When the link is established, the central processing unit 34 has a global address, for example, "127", which is a common reception address newly defined between the mutual processing units and which means that the following field is used as an information field. A global address frame having "" in the address field and having in the information field the sequence number CKN for signal identification written in the last byte of the last received I frame and the identifier ID that needs or does not need retransmission .
When the frame having the address field value of "127" is received, the layer 2 termination circuit 3 writes the information field (ID and CKN) in the memory 5 and reports the reception to the central processing unit 4. The central processing unit 4 that has received the reception report
When resending is required by the received identifier ID, a frame transmitted with the sequence number CKN but no reception response from the partner device has the sequence number for signal identification of the last byte of the I field that matches the received CKN value. If there is, the next I frame is retransmitted, and the previous I frame is not received. If they do not match for all the frames, control is performed so as to perform retransmission processing.

In the same manner as the above, the central processing unit 34 for controlling the layer 2 termination circuit, which has newly entered the act state, is also the same.
Also performs transmission processing. At this time, the memory 35 has the same contents as the memory 25 in the act state before, so that the I-frame can be transmitted without error even in the case of the layer processing device 31.

X. The layer processing device for H.75 is also described in X. Two
Since the configuration and the function are the same as those of the layer 2 processing device for No. 5, the description thereof will be omitted.

[0012]

As described above, according to the present invention, when an I frame is transmitted, a signal identification sequence number is added by the layer 2 termination circuit controlling central processing unit at the transmission side and deleted at the reception side to identify the I frame. By establishing a link even after the data ring is disconnected once, and sending the signal identification sequence number as an information field to the partner device using the global address frame, an acknowledgment response is sent from the partner device. For I-frames that do not come, the data can be retransmitted without excess or deficiency without using a complicated multi-link procedure, and even if the operation is continued using the backup line when a failure occurs, the connected call It is possible to prevent the call from being disconnected or the call setup request from being disabled.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

2A and 2B are diagrams showing a format of a newly defined frame.

[Explanation of symbols]

1, 11, 21, 31 Layer 2 processing device 2, 12, 22, 32 Layer 1 termination circuit 3, 13, 23, 33 Layer 2 termination circuit 4, 14, 24, 34 Layer 2 termination circuit control central processing unit 5 , 15, 25, 35 Frame storage and control memory 41, 42, 43, 44 Communication line

Claims (1)

[Claims] 1. CCITT Recommendation X. 25 and X. For the global address frame that performs the layer 2 termination processing of 75 and has a global address in the address field, which is pre-arranged with the communication partner device different from the unique address, the data following this address field is used as information. It has a layer 2 terminating circuit for transmitting and receiving information as a field, and means for creating a signal identification sequence number representing the transmission order of transmission frames, and controls the layer 2 terminating circuit under the control of a host device. Information is transferred between the device and the layer 2 termination circuit, and the signal identification sequence number is added when transmitting an I frame, and the signal identification sequence number added by the partner device is extracted when receiving an I frame to ensure transparency of the information transfer. And
At the time of requesting retransmission of an I frame, the signal identification sequence designated to transmit the global address frame having the signal identification sequence number added by the partner device of the last received I frame in the information field and receive the global address frame Central processing unit means for retransmitting from an I frame to which a number is assigned, a layer 2 processing device.