JPH0637798A - Reserved ring mechanism of packet exchange - Google Patents

Abstract

PURPOSE: To provide a reservation ring mechanism adjusting contention in a wide band ISDN high speed packet exchange. CONSTITUTION: The reservation ring mechanism is provided with a means for circularly shifting a reservation vector in a top-to-down order during at least one arbitration cycle and permitting the contended inputs to access to the same output in the top-to-down order. When the maximum permission number of competitors are in a contention state on outputs, access to specified output is permitted to the maximum permission number of competitors during the respective arbitration cycles.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to high speed broadband communication networks, and more particularly to high performance local area networks (LANs).

[0002]

Research projects and system products will soon have bandwidth, responsiveness and / or real-time requirements that exceed the capacity of existing LANs. For example, there is an ongoing transition from paper to electronic formats for documents ranging from private documents to technical literature, and for this reason advanced electronic scanning and printing devices have been developed. The bandwidth requirements of these devices will continue to grow due to the increased speed and resolution of the devices as well as the increased color and grayscale capacity of the devices. Improved LAN
Another example of the demand for IoT is conceived by some emerging co-production technologies, such as Xerox Media Space, which uses live video links and conference aids based on wall-sized displays. You are focused on high quality video images. In addition, high performance computers are becoming available as computing resources, high performance file servers, visualization workstations, etc.
N does not have the necessary capacity to support these high performance computers.

[0003] Potential demanding scientific computing and visualization applications require data rates of gigabits per second (Gbps), while the vast majority of perceptual applications require between 10 and 100 megabits per second (Mbps). Bandwidth is sufficient. However, some perceptual applications, such as real-time video, put long continuous loads on the network, and in addition to point-to-point (unicast) links,
It will require one-to-many (multicast) transmission. Therefore, it is reasonable to assume that a LAN will soon require an aggregate bandwidth of 10-40 Gbps to simultaneously support the ordinary user community. Since different user communities generally have different needs, and the needs of all user communities generally grow over time, there is a need for a high performance LAN that scales to meet the needs of the user community gracefully and economically. Has been done.

[0004]

[Problems to be Solved by the Invention] Known FDDI (Fibe
r Distributed Data Interface) networks cannot meet the peak bandwidth requirements of the LAN as contemplated by the present invention or the aggregate bandwidth requirements. Also, many other recently developed technologies, such as those based on crossbar exchanges or high speed broadcast buses, are based on the proposed LA.
N multicast (muticast), broadcast (broadcas)
It seems that t) and / or affordability requirements cannot be met.

[0005]

According to the invention, a classification network is arranged next to said classification network,
A non-blocking self-routing switch with multiple routing networks that routes packets from multiple inputs to multiple outputs has a reservation ring mechanism that resolves conflicts between the inputs competing for access to the same output. There is. The reservation ring mechanism comprises means for circularly transferring the reservation vector in top-to-down order for at least one arbitration cycle to allow the competing inputs to access the same output in top-down order. Thus, whenever at least the maximum allowed number of competitors are competing for the same output, that number of competitors is granted access to that particular output during each said arbitration cycle.

[0006]

EXAMPLE I. Definitions The following terms, as used herein, have the following meanings.

"Channel rate" is the bit rate of a particular stream, channel, etc., eg, single television transmission, file transfer, database transaction.

"Link rate" means that devices in the network (hosts, routers, switches) can or must be maintained on individual links (pairs of wires, coaxial cables, optical fibers). It is a bit rate that cannot be achieved. This rate is the upper limit of the channel rate. In addition, this rate has a great influence on the cost of interface hardware and the cost of network protocol hardware and software.

"Aggregate rate" is the maximum aggregate network capacity expressed as the sum of link rates for the maximum number of links that can be transmitted simultaneously. For networks embodied as buses or rings, i.e. networks using single frequency wireless broadcast, the link rate is the same as the aggregate rate. Conversely, conventional telephone switching systems provide much higher aggregate rates than any link rate.

II. Basic Architecture The ATM LAN of the present invention can be implemented using a VLSI based "Batcher / banyan" network of the type developed by AT & T / Bellcore. As will be appreciated, this LAN supports unicast and multicast virtual circuits operating at a link rate of 115 Mbps and is prepared to increase the link rate to 600 Mbps. In the implementation disclosed herein, each switch would support 32 ports. However, it is likely that the Batcher / banyan network will scale for switches larger than 256 ports and for link rates of 1 gigabit / second and above (in part due to the advances disclosed herein). Also, these switches can be interconnected to create a larger hierarchical network to support a larger community of users.

One of the attractions of ATM switching is that it is fairly close to becoming a standard. The basic idea of this type of network is that all communication is done by sending and exchanging small fixed size data packets called "cells". Since the overhead of each packet is reduced by using the virtual circuit technique, the header of each cell identifies the route preset by all switches between the source and destination. As such, the information needed to identify a cell and its desired routing is significantly less than the header information for a normal XNS or TCP / IP datagram. Those who are interested in the ATM standard creation activities and their technical content are CC
ITT (International Telegraph and Telphone Consu
ltative Committee) Study Groups XI and XVIII
And ANSI (American National Standards Insti
tute) sub-committee See the article on the subject published by T1S1.

In accordance with the emerging ATM standard, cells are small fixed size (53 byte) packets. The header contains destination addressing information known as a destination virtual circuit index (abbreviated as VCI). In addition, the Virtual Path Index
x; abbreviated as VPI), but since the exchange on the virtual path is essentially equal to the exchange on the virtual circuit, details of the virtual path index are omitted. Before a cell enters the switched network, the source host transfers the cell from its source to its destination, a "Virtual Circuit".
rcuit) "to determine the fixed route. Each switched link (each inter-exchange link and each inter-exchange destination link) of this virtual circuit is uniquely identified by a switch-specific virtual circuit identifier (VCI '). Therefore, one virtual circuit has many names. Since cells cannot be reordered at any point along the virtual circuit, they should arrive in the order in which they were sent.

With the above in mind, looking at FIG.
Hierarchical LAN 21 includes one or more sources 3
It can be seen that it comprises a plurality of self-routing non-blocking switches 22-25 which transfer cells, eg ATM cells 27, from 1, 32 to one or more destinations 33. For example, in the case of LAN, the sources 31, 3
2 may be a workstation and destination 33 may be a file server. LAN as shown
21 has a two-level hierarchy, the hierarchy is Metropolitan
Area Networks (MANs) and Wide Area Networks
It will be apparent that it can be extended to transport and switch packets over fairly long paths, including (WANs).

Next, FIG. 2 will be described. Switchboard 22
~ 25 is for each batcher / banyan (batcher / ba
nyan) Network 41 is appropriately configured. As shown, in the case of switch 22, a single n-port batcher classification network 42 has a number k (typically 2 or 3) of Bayan routing networks 4
Providing cells to 3,44. Banyan routing networks 43, 44 are connected such that k cells can be routed to the same output port number without losing any cells during the same cell exchange cycle. To accommodate this parallel processing, the Banyan routing network 43,
A relatively large (thousands of cells) FIFO made to accept up to k cells per cycle from 44
A buffer 45 is provided at each output port. FIF
O-buffer 45 is a small two FIFO buffer (not shown), or hundreds of cells for rate-limited or reserved traffic, to handle both real-time and "best effort" traffic. FI
It is preferably composed of a FO buffer and a fairly large FIFO buffer for unreserved traffic.
The size of the small FIFO buffer is limited to approximately twice the period of the rate limited stream. For the rate in question, this means that the FIFO buffer for reserved traffic should be at least 200-300 cells in size. For "burst" traffic that is not limited by strict rate limits, the virtual circuit is queued in a larger FIFO buffer (best effort traffic). It can be seen that the Transmission Control Protocol (TCP) effectively executes if there is at least one full datagram buffering for each input port that is accessing the determined output port. Therefore, in the case of an N-port switch, where all N ports will send TCP packets to one output simultaneously, a larger output FIFO
It is necessary to buffer about 4 × 4 Kbytes in the buffer. FI of these sizes, as is known
The FO buffer is easily created from SRAM.

As will be appreciated, if more than k cells could be sent to the same output port number during a single switching cycle, the switch would predict rather than simply drop excess cells. Will fail to perform as done. Therefore, this situation should be avoided.
Therefore, in accordance with generally accepted practice, a reservation ring 46 is provided that imparts fairness to such conflicting cells between cells and at the same time provides at most k cells to the switch in any cycle. As will be described in more detail below, this reservation ring 46 is a shortened array (systol
It consists of a set of circuits (one circuit for each port) wired through all the ports to create an ic array).

Connected to the input side of the switching network 41 and the reservation ring 46 is an n × n copy network 48.
Is. The copy network 48 can be made using off-the-shelf or custom crossbar switch components. All cells are specially marked as point-to-point or multicast cells depending on the state of the multicast bit in the switch header. As can be seen, the ATM cells are pre-populated with switch headers for routing the ATM cells through the switching network 41 and enqueuing the appropriate output queues in the FIFO buffer 45. The incoming multicast cell is
Although it bypasses the copy network and is passed through the switching network 41, it is intercepted by the switching network 41 at that time and returned to the copying network 48 without being sent to the output line.

Specifically, the destination virtual circuit index (VCI) in the header of the multicast cell.
Identifies groups rather than individual destinations. Therefore,
The first pass of the multicast cell through the switching network 41 causes the cell to be routed to the input of the copy network 48. The copy network 48 makes a copy of the cell C
You can create one (or maybe more). Where C is the size of the group to which the cell is addressed. When it is necessary to handle a switch having a hierarchical structure such as the switches 22 to 25, it becomes complicated to some extent, but this complexity does not make the hardware complicated. When a copy of a cell exits the copy network 48 (but before entering the switching network 41), pre-programmed per-port mapping hardware (not shown) makes each copy different. Address to group number. To do this, a separate table at each output port of copy network 48 is typically indexed by group number. Since the table contains the output port number for the group number, any given input port of the copy network 48 can handle a large number of groups of similar size. Obviously, the copy network 48 described above can support a large number of multicast groups, but is most suitable for applications where the variation in the number of group members is relatively rare.

FIFO cell buffers 51, 52 are also provided at each input port of the switching network 41 for buffering incoming cells and cells provided by the copy network 48. These buffers 5
1, 52 keep cells arriving at their input ports until they can be routed through switching network 41 without conflicting them (if desired, to support multiple priority classes, One or both of these buffers 51, 52 can be split into sub-buffers).

The routing of cells through the switching network 41 is accomplished by the VCI translator 53 at the input port to the switch.
Controlled by. These translators 53
Using the VCI lookup table 54 maintained and updated by the host processor (not shown), the input port address and destination virtual circuit contained in the header of the cell at the head of the queue for the input port. Tree valued functio of index (VCI)
Calculate n). That is, [VCI ′, outputPORT, mut
icastFlag] ← Routing Function [i, VCI]. As will be appreciated, an interface to a conventional microprocessor or similar device (not shown) is required primarily to load various routing and mapping tables into the VCI lookup table 54 to control the switch 22. Is.

III. Detailed Description of the Components of the Switch A. A translator 53 provided at the input port of switching network 41 to perform virtual circuit translator address mapping selects an output port from switching network 41 on the route to the target destination (at the head of the input queue). Based on the destination VCI / VPI address in the header of the ATM cell); input VC
Rewrite the I / VPI address to a value suitable for the output link (VCI / VPI is end-to-end significance (end-
It has no to-end significance); and, as will be explained in more detail below, managing the mapping required for multicast transmission. These translators 53
In addition, a count of the number of ATM cells exchanged per virtual circuit can be maintained for billing and load monitoring, for example. FIG. 3 shows a typical ATM cell format, and FIG. 4 shows a typical switch header format for an ATM cell. Note that the Global Flow Control (GFC) field in the cell header usually contains a NULL value.

B. Batcher / Bany
an) Network A switching network is an arbitrary permutaton or partial permutaton of its inputs in every switching cycle.
l permutation), it is said to be "non-blocking". In other words, the non-blocking switch can generate all possible 1: 1 input / output mappings.

Switching networks are generally made up of cascaded networks or stages of single switches. The path through such a switching network is the path through the stages of the switch from a defined input to a defined output. The exchange network is
For each stage in the switching network, if the routing can be determined only by the information contained in the cells entering that stage, i.e. locally available information, it is classified as "self-routing". It

The Batcher / Banyan network is a known example of a non-blocking self-routing switching network. As is known, the Batcher Network
Generally depth log ₂ N (which means that the need for Nlog ₂ N pieces of classification elements) is parallel sorting network for classifying the N data streams in the network.
As shown in FIG. 5, each classification element 62 has two inputs (A
And B) and classify the inputs by calculating the minimum and maximum values. Therefore, if the input is initially in the form of a 2-bit serial data stream with the most significant bit, the classification element functions as the very simple finite state machine 64 shown in FIG. . For four inputs, eight inputs, and more, these classification elements 62 are typically recursively combined to form a classification network 65 or sorter (see FIG. 7).

As shown in FIG. 8, the standard Banyan routing network 71 is a multi-stage network of depth log ₂ N. Here, N is the number of inputs to the network. The Banyan routing network 71, like the Batcher classification network 65, is constructed by recursively combining basic switching elements 72 having two inputs and two outputs. Therefore, the Banyan network 71 has O (Nlog ₂ N) basic switching elements 72. As the data sequence flows through the Banyan network 71, the primitive 72 at each stage of the Banyan network 71 examines one bit of the output address and, according to the value of that bit, that bit and all subsequent bits in the data sequence. The bits of to one or the other output. By convention, the address bits change from stage to stage, so the first stage routes based on the value of the most significant address bits and the second stage routes based on the value of the second higher address bits. , Nth stage routes based on the value of the least significant address bit. After the N address bits have been processed, the rest of the sequence follows the established path to the switch output. This means that the end of one sequence and the start of the next sequence must be determined by external factors. Thus, in this example, recall that each sequence is a fixed size ATM cell + its fixed size switch header.

At any stage of the Banyan network 71, two inputs may select the same output. If that happens, Banyan Network 71
"Blocks", resulting in indeterminate results. In other words, Banyan network 71 is unable to compute an arbitrary permutation of its inputs. However, since the Banyan network 71 is "non-blocking", there is a permutation class. One of these classes is the class whose inputs are ordered by output address. Therefore, switching network 41 that is non-blocking self-routing
2, the batcher classification network 42 is a banyan routing network 43, 4 as shown in FIG.
In front of 4.

As shown in FIG. 2, multiple Banyan routing networks 43, 44 (typically 2 or 3) are preferably used to reduce output contention. For example, in the illustrated embodiment, k =
There are two Banyan routing networks 43, 44 behind the batcher classification network 42 to obtain a speedup rate of 2. Since each Banyan routing network 43, 44 uses only 1 / k of the inputs, the other inputs are blocked. The output of the Batcher classification network 42 is connected to the input of the Banyan routing network 43, 44 so that the kth output of the Batcher classification network 42 is connected to the kth input of the Banyan routing network 43 or 44. (This is as shown in the Banyan Routing Network 4
3 and 44 respectively route the odd and even numbered outputs of the batcher classification network 42). Thus, up to k individual cells addressed to the same output port can appear on successive k outputs of batcher classification network 42. The individual cells can then be routed to the target output port of switching network 41 through k separate Banyan routing networks 43,44.

C. Reservation Ring The reservation ring 46 (see FIG. 2) is an arbitrator (arbiter) that implements "fair" access to the output ports of the switching network 41 when the number of cells addressed to a single output is greater than or equal to k. Although many different definitions of "fairness" have been made, arbitrators who provide brute force (round robin) service to competing input ports of switching network 41 are preferred.

More specifically, the reservation ring 46 is made of Ar.
turo Cisneros, "Large Packet Switch and contention
Resolution Device, "Proc.XII International Switch
ingSymposium, Stockholm, Sweden, May / June, 1990. V3,
In accordance with the teaching of the published paper of pp.77-83, each of the finite state machines 76a, 76 communicates only with its neighbors.
b ,. ． ． 76i, 76 (i + 1) linear shortening array 7
5 (FIG. 9). A particular advantage of using a linear shortened array, such as array 75, is that all communications are local and the electrical load does not increase with array size. This allows linear scaling of the system.

By modifying the reservation ring mechanism of the above paper, a fair brute force conflict solution for switching networks, eg switching network 41, with multiple routing networks 43, 44 (ie networks with k ≧ 2) is obtained. I found out that During operation, finite state machines 76a-76
n is a set of spatially fixed evaluation elements associated with the input ports of the switching network 41.
nts), and the vector of state information is shifted so as to pass through these finite state machines, that is, the evaluators 76a to 76n in a ring shape. To do this, each evaluator 76a~76n internal address register RA _i,
External shifted address register SA _i , internal single-bit register FC _i for conflict flag bits, second internal single-bit register RC _i for conflict request flags, third internal for pending conflict request flags With a single bit register F _i , an external register SC _i for the shifted contention flag, a single bit register T _i for the scan vector, and an internal (k-1) bit log ₂ k mod k counter Cntr _i There is. Furthermore, each evaluator 76a-
Means are provided for switching 76n between the active (InSession = 0) and inactive (InSession = 1) states.

At system reset time, all evaluators 76a-76n are reset, resulting in the clearing of their address registers RA _i , SA _i , their counter Cntr _i and their flag bits and states RC _i , SC.
_i , FC _i , F _i , T _i and InSession _i are set to “0” or “false”. At the beginning of each arbitration cycle, the evaluators 76a-76n scan the active cells at the head of the input queue for the input ports of the switching network 41, and the addresses of the output ports to which these cells are addressed are stored in the internal address register RA. _i and the external address register SA _i . If the input port is inactive (ie its input queue is empty), the evaluator is in the inactive state (InSession = 0,
T _i = 0). After this initialization procedure is finished, a series of at least (n-1) shift and compare steps are started, which shift the address value SA _i and the conflict flag bit SC in the ring (ie port i). The values of those variables in the evaluator shift to the evaluator at port i + 1 and the values of the variables in the evaluator at the last port shift to the evaluator at the 0th port). T _i is shifted down but, T input of port 0 remains "1".

After each shift, the address registers RA _i ,
The contents of SA _i are compared by each evaluator. If, in the active evaluator, they are found to be identical, the evaluator determines whether the requested conflict flag RC _i and the shifted conflict flag SC _i are set to the same value. , Determine whether the identity comes from a legitimate arbitration session.

If the evaluator is a legitimate arbitration session participant, the evaluator examines the current state of the conflict vector T _i . If T _i is still false (“0”),
The i-th evaluator determines that the active cell at the i-th input port of the switching network 41 and the active cell at a certain input port above it compete for access to the same output port. In any switching cycle, up to k cells (but only k cells) can be switched to the same output port of switching network 41, so the i-th evaluator is in switching network 41. Discovering that it is conflicting with a port somewhere above that,
It simply increments the counter Cntr _i . But if the counter
If the i-th evaluator receives a true (“1”) contention vector value T _i before Cntr _i overflows, the i-th evaluator sends the current count in the counter Cntr _i + acknowledge signal to the input buffer. By returning, i of the switching network 41
Release the cell at the head of the input queue for the second input port and switch to the requested output port. On the other hand, if the counter Cntr _i overflows before receiving the true (“1”) conflict vector value T _i , the conflict flag bit FC _i and the pending conflict flag F _i are true (“1”) in the i-th evaluator. ) Set to the state, to allow all competitors access to the requested output ports of switching network 41 in a brute force top-down order when requested, for one or more additional switching cycles. Is extended.

D. Alternative Arbitration Process The present invention provides k Banyan routing networks 43,
It is essentially a departure from the Cisneros principle described above in order to provide another shortened array approach (k ≧ 2) with “fair” access to the 44 (FIG. 2) output ports. FIG. 10 schematically shows this technique. In this implementation, each evaluator 78a-78n functions as follows. Initialize for arbitration: counter: = 0; Grant: = 0; Arbitration step: lostLastTime-Out: = lostLastTime-In; resVec-Out: = resVec-In; lostThisTime-Out: = lostThisTime-In; IF couter = portRequested THEN { IF lostLastTime-In = 0 OR ISetLostLastTime THEN {IF resVec-In = 0 THEN {Grant: = 1; ISetLostLastTime: = 0 resVec-Out: = 1; lostThisTime-Out: = 0;} ELSE {lostThisTime-Out: = 1 ISetLostLastTime: = NOT lostThisTime-In;};};};

In this implementation of reservation ring 46, first evaluator 78a (not shown) has r bound to "0".
esVec input and lostThisTim on the last element of the reservation ring
Note that we have the lostLastTime input constrained to the e output. The stream of bits shifted through the resVec input represents a vector whose elements are the reservations of the corresponding output port. If there is more than one requester for a given output port, the first requestor who fails to access it has its associated "ISetL
Since the "ostLastTime" bit is set, the behavior of the ring is a round robin fair. When the arbitration cycle ends, the "ISetLostLastTime" set
There may be many reserved ring elements with "bits", but each of those bits points to a different output port.

As will be appreciated, this reservation ring mechanism of FIG. 10 can be extended to handle the case of allowing multiple input ports to access the same output port during one exchange cycle. This is the reservation vector r
This is accomplished by making esVec k bits wide. Where k is the number of input ports that can be sent to a single output port during one exchange cycle. At that time, the reservation ring operates as follows. Initialize for arbitration: counter: = 0; Grant: = 0; Arbitration step: lostLastTime-Out: = lostLastTime-In; resVec-Out: = resVec-In; lostThisTime-Out: = lostThisTime-In; IF couter = portRequested THEN { IF lostLastTime-In = 0 OR ISetLostLastTime THEN {IF resVec-In NEQ “all ones” = 0 THEN {Grant: = 1; ISetLostLastTime: = 0 resVec-Out [firstZero [resVec-In]]: = 1; lostThisTime-Out : = 0;} ELSE {lostThisTime-Out: = 1; ISetLostLastTime: = NOT lostThisTime-In;};};};

It may be desirable to divide a larger reservation ring of the type shown in FIG. 10 into two (or more) sections. The reservation vectors for the two rings are also k bits wide. However, for the first section some of the k bits are initialized to "1" and for the other second section the corresponding bits are initialized to "0". The remaining bits are initialized to "0" at the top and "1" at the bottom. Assuming that the load is evenly distributed across the inputs, the switch acts approximately as if there were only one reserved ring, but the two rings are of a single ring clock frequency. It can be run in half.

If the traffic is not evenly distributed over the two split half-rings, the bandwidth for any given output port can be reduced to two half by changing the bit initialization for the reservation vector. You can interact between the rings. There are two methods for calculating the traffic of each half of the reservation ring, but not limited to the following two methods. 1) Count the number of "lostThisTime" bits set to "1" at the output of the bottom or last evaluator of each half of the reservation ring. 2) Adding a vector of counters to the data stream that is shifted through the reserved ring element, so that each lost
g) Have the evaluator increment the counter associated with the target output port. Then, upon exiting the last evaluator, the sum of these counters is determined, and if this sum is above a predetermined threshold, the bandwidth is transferred between the split reservation rings.

E. Copy Network The N × N copy network 48 of FIG. 2 receives up to j ATM input cells I _j (j ≦ N) per exchange cycle and makes C _j exact copies of each cell. Each C
_{The j} copies are called a copy group. As will be appreciated, cell duplication is an important step in what is known as "multicast operation".

Underlying the approach to the copy network 48 are three viable assumptions about the use of the switching network 41. The first is that for each j, C _j changes very slowly. Second, the sum of all copy group sizes is ≤N. _Thirdly , C _j is j
It is only a function. Collectively, these conditions mean that the number of copies made by each copy group varies very slowly, which means that the number of members of the copy group is not a function of the cell contents. Therefore, a static routing strategy can select a particular value of j for any copy group, so that one input of copy network 48 and C _j.
Outputs are dedicated to each copy group.

In the case of a standard crossbar switch, each of the N inputs fan out to each of the N outputs. this is,
Turning on a crosspoint connecting one input to a subset of multiple outputs means that the input is copied to all these outputs. Conceptually, the copy network 48 has j inputs that are used as inputs to the copy group, not used (N
-J) consists of an input and an NxN crossbar with ΣC _j outputs used. However, as a practical matter, usually not all crossbars are needed. This is fortunate, as a large crossbar not only makes the chip expensive, but also causes difficult system implementation problems.

Fortunately, as shown in FIG. 2, an alternative scheme can be used for applications where the most common use of copy network 48 is small copy groups. That is, when a multi-node spanning tree is required to create the required number of cell copies C _j as a copy group, the switching network 41 itself is used to create a plurality of copy networks 48. It is possible to interconnect "virtual circuit layers". This preferred embodiment of copy network 48 is
A natural system implementation is used because it can be embodied using two types of boards (switch network 41 and N / p identical line cards, each with complete logic for every p lines). Compatible with that. As shown in FIG. 2, the logic of the line card is (for each of its p lines) an input link 84 and an output link 85, a VCI translator 53, a reservation ring evaluator (see FIGS. 9 and 10), and all inputs. And output buffering, and a pxp crossbar 86. When using such a copy network 48, groups larger than p (here, p =
8) multicast or broadcast (b
roadcast) is handled by multicasting to the group, so that the cell makes three trips through the switching network 41.

F. Input and Output Buffering-Queuing Strategy-Switching network 41 uses distributed queues (one or more dedicated queues for each input and output line) rather than shared queues. As is known, shared queues are a useful technique for dynamically reallocating buffer space across all lines, ie, for more efficient use of buffer memory. However, in this case the simplicity of the design is more important than optimizing the utilization of the buffers, so that the exchanges should be given fair service training while at the same time providing a means to separate the input and output lines from each other. Has been. Thus, if several inputs transmit at a rate that far exceeds the output's ability to carry traffic, cells will be lost by the switch either in the buffer for the input line or in the buffer for that particular output. .

The LAN 21 (FIG. 1) suitably uses simple flow control mechanisms to limit guaranteed traffic load. In particular, it limits the rate of guaranteed traffic depending on the network interface hardware / software (not shown) of the workstations, such as sources 31, 32, and other computers that are serviced by the LAN. By convention, to indicate a guaranteed traffic stream with pre-reserved resources,
The resTraf bit in the VCI lookup table (copied to the switch header) is used. Therefore, there is at least two input queues (one for guaranteed traffic and one for non-guaranteed traffic) for each input port of switches 22-25. If the non-guaranteed traffic queue is full, then non-guaranteed cells cannot be queued.

IV. System Operation A. Unicast Unicast transmission is the normal routing of cells from multiple sources to a specified single destination, as defined by a given virtual circuit address (VCI). In any given switch, such as switch 22 of FIG. 2, a unicast operation begins when a cell arrives at input link 84 for one input port of switching network 41. Logic (not shown) in the input link 84 examines the VCI field of the cell header to make sure it contains a non-zero value (ie, the cell is not empty). If the cell passes this test, the state of the input buffer 51 for the determined input port is checked to determine if it can accept the cell. When making this acceptance / rejection decision, it is preferable to take into account the state of the cell loss priority (CLP) bit in the header of the cell. For example,
A cell is shifted into the input buffer 51 only if (1) the buffer 51 is not full and the CLP bit is reset, or (2) the buffer 51 is half full.

The virtual line translator 53 at each input port of the switching network 41 takes out cells from both the input buffer 51 and the crossbar buffer 52. The priority is given to the crossbar buffer 52. As will be appreciated, the translator 53 is active only when there are no blocked cells on the reservation ring 46 due to output contention. If the above blocking condition does not exist, then at the beginning of each switching cycle, two input FIFOs
Buffers 51 and 52 are inspected, crossbar buffer 5
A cell is taken from either 2 (first selection) or the input buffer 51 (second selection). These FIFOs
If the buffers 51 and 52 are both empty, a NULL cell, that is, an empty cell having all zeros is generated.

In the virtual line translator 53,
The first 4 bytes of the header of the selected cell are shifted into a "4 bytes + 10 bits" delay buffer (not shown) and the rest of the cell (eg 49 bytes of information in the case of a standard ATM cell) is VCI converted. Shifted to a FIFO buffer (not shown). The VCI value included in this header is then indexed into the VCI conversion table 54 to obtain the switch header (swit
ch header: See Figure 4) used to obtain information. This switch header is written in the first 10 bits of the delay buffer. The VCI conversion table 53 also provides the cell with a new VPI / VCI value. Use this new VPI / VCI value to
The PI / VCI value is overwritten, after which the checksum or "HEC" field (see FIG. 3) of the ATM cell header is updated.

The switch header contains an active flag (1 bit) indicating whether the cell is empty, an output port address (6 bits for 64 ports provided by two parallel 32 port Banyans), and a stopper bit (dual). It is appropriately formatted to include one bit for the Banyan switching network 41, its source and function are described in detail below). In addition, the switch header typically has a multicast flag (1 bit) that indicates whether the output port should send cells to the copy network 48, a reserved traffic (RT) that distinguishes reserved traffic from unreserved traffic on the copy network. Bit (1 bit), Cell Loss Priority (CLP) flag (1 bit) indicating whether or not the cell is a suitable candidate to drop in case of overload (this bit is
Reserved bits (5 bits) to pad the switch header so that the length of the switch header is 2 bytes).
Is included.

In practice, the Batcher / Banyan exchange network 4
1 (FIG. 2) is preferably configured to provide a 1 byte wide (8 bit wide) data path between its input and output ports in accordance with known techniques. The first byte of the switch header (ie active bit,
The output port address, and the stopper bit) are transmitted in bit parallel mode on the above data path, while the remaining bytes of the switch header and all 53 bytes of the ATM cell utilize the parallel data path structure of switching network 41. Therefore, it is preferable to transmit in the byte parallel mode.

The cells processed by the virtual circuit translator 53 are subject to arbitration control of the reservation ring 46. To perform its arbitration function, the reservation ring 46 only examines the headers of cells at the head of the input queue to the switching network 41 to determine if there is a race condition between these cells, If so, resolve those conflicts. Actually, VCI conversion buffer (not shown)
Is of bounded depth.

As soon as the evaluator (see FIGS. 9 and 10) for a given input port of the switching network 41 (FIG. 2) wins the arbitration round, the input port is switched to the waiting cell. It is sent through the fabric 41. As shown in the figure, the basic structure of the exchange consists of two Banyan networks 43, 44 (k = 2), each network 4
3, 44 are connected to the output buffer 45 for the finally selected output port. If the cell is not active (ie, if the active bit in the switch header pre-attached to the cell is 0), the cell will not be queued by the output buffer 45. On the other hand, if the cell is active and the resTraf bit in its switch header is "ON", the cell will be queued in the section of the output buffer 45 reserved for guaranteed traffic. Alternatively, if the cell is active and its r
If the esTraf bit is “OFF”, the cell is an output buffer 4 reserved for non-guaranteed (unreserved) traffic.
Placed in section 5.

A cell in the guaranteed queue of any given output buffer 45 is always dequeued before any of the cells in the non-guaranteed queue. When the cell is unicast, the multicast bit in the switch header is turned "OFF"("0") so that when the unicast cell is dequeued, it is sent to the associated output buffer 45. The cells are labeled accordingly.

As will be recalled, the first byte of the switch header is duplicated over all 8 bits (ie across the entire parallel data path) and the other second byte is transmitted in byte parallel mode so that the switch The header adds 9 bytes to the cell length. Furthermore, in the output link, 2 bytes of framing information is added to the 53-byte long cell (by normal means not shown), so the byte rate in the output buffer 45 is the byte of the output link 85 to which it is connected. It is at least (53 + 9) / (53 + 2) times greater than the rate. To adjust for this imbalance, typically each output buffer 45
A short FIFO buffer (not shown) is provided to rate match each to its corresponding output link 85.

B. Multicast As noted earlier, a multicast group is a virtual circuit that addresses multiple network destinations. Therefore, each stage of the switch must know which switch output port it must access to send a copy of the input cell to all destinations in the group. From the perspective of a single switch, eg switch 22 (FIG. 1), a multicast group is a VCI / VPI pair that specifies the cells to be routed to a set of known destination VCIs. One of the features of the exchange of the invention is that it performs routing of multicast cells in two stages. That is, the correct number of copies is made by first routing the multicast cells through the correct input copy network 48, and then the copies of these multicast cells are individually rerouted to the intended destination through the switching network 41.

Multicast operations begin with the same steps as unicast operations. During the VCI conversion process,
The first difference occurs because the indexed entry VCI translation table 54 (FIG. 2) specifies whether the VCI in the header of the input cell indicates a unicast address or a multicast group address. Therefore, for cells with a multicast VCI, the multicast bit in the switch header is set. Next, the cell goes through the switching network 41, and the switching network 41 sees the named multicast VCI and connects the output buffer 45.
Go to the queue. Upon exiting that queue, the status of the multicast bit will be the associated output link 8
The hardware is instructed to return the cell to the copy network 48 via the input of the copy network 48 connected to the determined output buffer 45 instead of to 5. The copy network 48 then makes a certain number of identical copies of the cell, for example j copies. These copies are then individually routed to the j outputs of the copy network 48 dedicated to the defined copy groups. Then, each of the j outputs outputs the received copy to the switching network 4
1 into the crossbar or copynet FIFO buffer 52 for the input port. The active bit in the header of each copy distinguishes between empty and active cells, so that FIFO buffer 52 can queue active cells and discard empty cells.

After being queued in a set of copynet FIFO buffers 52 associated with a determined copy group, the cells are retrieved by virtual circuit translator 53 in the proper order, as previously described. . Each virtual circuit translator 53 has a separate VCI translation table 54 so that j copies of the cell receive j different VCI translations. Therefore, for each of the j cells, the subsequent processing steps are the same as the first pass of the unicast cell, ie the multicast cell through the switched network 41.

As will be appreciated, the routing of multicast cells through any of the exchanges' switched networks 41 depends on the rewriting of the VCI occurring in the virtual circuit translator 53. For example, let j be the size of the multicast group, and vci, vci'i, and vci "i be the VCI values taken by consecutive multicast cells during a multicast operation (0 <i <j). When entering 22 (Fig. 2), the VCI value is v
It is ci. Therefore, when the cell first passes through one of the virtual circuit translators 53, a switch header for the cell is generated based on said value vci, thereby rewriting the VCI value of the cell header to vci '.
As a result, on exiting copy network 48, there are j exact copies of the cell, each having a VCI value of vci '. Each copy is then translated in the corresponding translator 53 using j different VCI translation tables 54, each containing a different translation for the vci'th entry. Thus, the i-th copy of the j cells emanating from the copy network 48 receives its own switch header and its own VCI value of vci ″ i.

In some instances, it may be desirable to implement the copy network 48 on a single board or card (not shown) to reduce switch complexity. This is a viable option, because the switch itself can be used to connect successive layers of the copy network 48 to each other, even if copy groups larger than the size of the line card are allowed. Operationally, this is done by allowing multiple levels of multicast groups. In other words, at the translator 53, j coming out of the copy network 48
Copy VCIs can be converted to VCIs for subsequent multicast groups, and by setting the multicast flag bit in the switch headers for these copies, the switch can reroute the copy and copy It can be returned through the network 48. If this option is used, the i-th cell from the above example will be treated by the remaining switches as a unicast cell, depending on whether the multicast bit in the switch header of that cell was set to zero, or Will be treated again as a multicast cell. If the copies coming out of the copy network 48 are different multicast cells, when passing through the switching network 41 separately, vci ″, vc in the header of the cell are passed.
VCI values for i ″ ″, and vci ″ ″ ″ will be generated.

In short, one of the many notable features of copy network 48 is that copy network 48 can accommodate copy groups of various sizes.
Is easy to program. Since this programming is built into the VCI translation table 54, changes to the number of members in the copy group should be minimized as one or more translation tables 54 need to be reconfigured.

From the above description, the reservation ring mechanism of the present invention effectively solves the output conflict in a non-blocking self-routing exchange having a plurality of routing networks, and has a minimal effect on the throughput of the exchange. It will be understood that

[Brief description of drawings]

FIG. 1 is a hierarchical ATM LA constructed in accordance with the present invention.
3 is a schematic diagram showing N.

FIG. 2 is a schematic diagram showing an ATM switch constructed in accordance with the present invention.

FIG. 3 is a diagram showing a normal format of an ATM cell.

FIG. 4 shows an exemplary switch header for ATM cells.

FIG. 5 is a schematic diagram showing batcher classification elements.

FIG. 6 is a diagram of a finite state machine showing the operation of the Batcher classification element.

7 is a schematic diagram of a batcher classification network consisting of recursive combinations of classification elements of the type shown in FIG.

FIG. 8 is a schematic diagram showing a Banyan routing network.

FIG. 9 is a schematic diagram showing a reservation ring mechanism.

FIG. 10 is a schematic diagram showing a reservation ring mechanism constructed in accordance with the present invention.

[Explanation of symbols]

 21 Hierarchical LAN 22-25 Self-routing Non-blocking Switch 27 ATM Cell 31, 32 Source 33 Destination 41 Batcher / Banyan Network (Switching Network) 42 Batcher Classification Network 43, 44 Banyan Routing Network 45 FIFO Buffer 46 Reservation Ring 48 n × n copy network 51,52 FIFO cell buffer 53 VCI translator 54 VCI lookup table (VCI conversion table) 62 Classification element 64 Finite state machine 71 Standard Banyan routing network 72 Basic switching element 75 Linear shortening array 76 Finite state machine 84 Input link 85 Output link 86 pxp crossbar 100 Switch 101 Input line 102 Output line 103 Another input line 104 Another output line 106 Switching network

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 8529-5K H04L 11/20 102 Z

Claims (1)

[Claims] 1. A switch having a classification network and a plurality of routing networks arranged next to the classification network for routing packets from a plurality of inputs to a plurality of outputs, competing for access to the same output. A reservation ring mechanism that resolves conflicts between existing inputs by shifting the reservation vector in a ring in top-to-down order for at least one arbitration cycle to top-down access to the same output for competing inputs. Permitting access to the outputs during each of the arbitration cycles whenever at least the maximum allowed number of competitors are competing for the same output. Reservation ring mechanism characterized by.