JPH0637789A - Cell composition device for atm communication - Google Patents

Abstract

PURPOSE:To provide an efficient cell composition device for use of ATM communication by which a cell is composed at a high speed and in which the hardware quantity is considerably reduced concerning to the communication to which high speed and real time performance are required. CONSTITUTION:The cell composition device for use of ATM communication is a device, in which plural layer processing sections 11-15 are arranged hierarchically, signal lines 102,112 used to send a timing signal representing a head of a cell or a data unit are provided among the layer processing sections 11-15 and at least one layer processing section starts processing for each cell according to the timing signal on the signal line, cell processing is performed by a hardware sequencer to compose cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM communication system, and more particularly to an ATM communication cell assembling apparatus for converting information into cells.

[0002]

2. Description of the Related Art In recent years, various communication demands such as image communication and high-speed data communication have been increasing, and in order to provide efficient and flexible communication services, it is desired to integrate communication networks. B-ISDN (Integrated Broadband Service Integrated Digital Network) that realizes the above is being actively researched. B-IS
In DN, an exchange method (ATM exchange) using a transmission method called ATM (Asynchronous Transfer Mode) is considered promising. The ATM exchange is to realize a communication service by storing information in a fixed-length packet called a cell regardless of its attribute and using this cell as a unit of exchange.

In conventional communication systems, packetization of information is limited to communication information that does not require real-time property as represented by data communication. Even if the packet communication is applied to high-speed and real-time communication of image information and the like, the real-time property is lost because it takes time to packetize the information.

Further, in an ATM communication system using ATM exchange, it is necessary to assemble transmission information as ATM cells. When assembling this cell, it is necessary to perform speed conversion accompanying the addition of the header / trailer in the adaptation layer processing and ATM layer processing, and there is a problem that the buffer amount required for this purpose becomes large.

Further, in multimedia communication represented by image / voice communication, it is necessary to assemble cells in real time for transmission information having a plurality of attributes and multiplex them on the same transmission path. At this time, since cells are separately assembled for each transmission information and then these cells are multiplexed, a large buffer is required and a plurality of cells are required. As a result, the hardware scale becomes large.

[0006]

As described above, the conventional AT
In the M communication system, there is a problem that high-speed and real-time communication is required, and it is not possible to form a high-speed cell. In particular, the cell assembling apparatus has a problem that the hardware scale becomes large because a large buffer is required. there were.

The present invention makes it possible to assemble cells at high speed for communications that require high speed and real-time performance, and to reduce the amount of hardware to achieve efficient A
An object is to provide a cell assembling apparatus for TM communication.

[0008]

An ATM communication cell assembling apparatus of the present invention has a plurality of layer processing units arranged in a hierarchical manner and a timing signal indicating the head of a cell or a data unit between these layer processing units. Is provided, and at least one layer processing unit starts processing for each cell according to a timing signal on the signal line and performs cell processing by a sequencer.

The plurality of layer processing units include, for example, a physical layer processing unit, an ATM layer processing unit, an adaptation layer (hereinafter referred to as AAL), a segmentation and reassembling sublayer (hereinafter referred to as SAR sublayer) processing unit, An adaptation layer / convergence sublayer (hereinafter referred to as a CS sublayer) processing unit and a higher layer processing unit are included. Each of these layer processing units performs layer processing according to the protocol layer structure shown in the CCITT recommendation. Of these, the physical layer processing unit, the ATM layer processing unit, and the AAL / SA
The R sublayer processing unit has a structure for performing sequencer processing for each cell.

In this case, the signal lines are provided between the physical layer processing section and the ATM layer processing section, between the ATM layer processing section and the AAL / SAR sublayer processing section, and between the AAL / SAR sublayer processing section and the AAL / CS sublayer processing section. A signal line is provided for transmitting a timing signal indicating the beginning of the cell or data unit.

More specifically, the ATM communication cell assembling apparatus of the present invention more specifically forms a transmission information generating section, a buffer section for accumulating the generated transmission information, and transmission information from the buffer section into cells, that is, as cells. It is composed of a cell assembling unit to be assembled, a physical layer processing unit, and a control unit controlling each of these units. The transmission information generation unit and the buffer unit correspond to the above-described higher layer processing unit, the AAL / CS sublayer processing unit and the AAL / SAR sublayer processing unit, and the cell conversion unit corresponds to the ATM layer processing unit and the AAL / SAR sublayer processing unit, respectively.

Between the cell assembling unit and the buffer unit, a timing signal line indicating the timing of the cell from the cell assembling unit to the buffer unit and a data signal line for data transmission from the buffer unit to the cell assembling unit. , A significant / insignificant signal line indicating whether the transmission information from the buffer section toward the cellizing section is significant or meaningless. The timing signal line is used to transmit a signal indicating the timing at which the cell assembling unit should perform processing for each cell, and to convey this timing to the buffer unit. Since the buffer unit does not always have transmission information, significant information does not always flow in the data signal line, and unintentional information may flow in some cases. Therefore, the significant / insignificant signal line is used to inform the cell assembling unit whether the information flowing through the data signal line is significant or insignificant.

[0013]

In the ATM communication cell assembling apparatus of the present invention, each layer processing unit uses the timing signal transmitted by the signal line as a start signal for the sequencer processing.
The processing for each cell is performed by the sequencer. The sequence is composed of hardware. Therefore, since high-speed cell processing can be performed using the hardware sequencer, a configuration suitable for fixed-length packet communication processing such as ATM can be obtained. Further, since the processing is divided for each layer, it is possible to configure a flexible cell assembling apparatus suitable for changing the specification of a certain layer or coping with layers having different specifications.

As described above, if the ATM communication cell assembling apparatus comprises the transmission information generating section, the buffer section, the cell assembling section and the control section, the cell assembling section transmits the cell timing signal to the buffer section, Only when the section receives this timing signal from the cell assembling section, the sequencer operates the sequencer according to this timing to send the data signal and the significant / insignificant signal to the cell assembling section, and the cell assembling section sends this cell timing signal. Since the cell formation process can be started as a sequencer start signal, high-speed cell formation process can be performed by using the sequencer.

Further, the cell assembling unit is a signaling cell / OA.
When it is desired to suppress the transmission of user cells such as M (Operation and Maintenance) cell transmission, the transmission can be suppressed by not transmitting this cell timing signal to the buffer unit.
It is possible to adopt a configuration in which there is no cell collision in the cell assembling unit.

In ATM communication, generally, a virtual connection (hereinafter referred to as VC) is set prior to the transfer of information, and after the start of communication, the cell is transferred on the route in which this VC is set. When a VC is set, a parameter representing the traffic attribute of the VC is set, the communication quality such as the cell loss rate and the delay time is estimated based on this parameter, and only when the required quality is satisfied, the network is Make settings. Therefore, the user has to comply with the above parameters during the communication. As described above, performing the cell transmission on the user side so as to comply with the predetermined parameter is called shaping. To perform this shaping, in the present invention, of the cell timing signals sent from the cellizing unit to the buffer unit, the cell timing signal is sent as a transmission permission signal to the buffer only at the timing selected by a certain rule. Then, since the buffer can send the payload only at this timing, the cell sending can be shaped by such a mechanism in the buffer unit.

Even when a plurality of buffers are physically or logically provided in the buffer unit, the cell timing signal sent from the cell assembling unit to the buffer unit is selected to any one buffer and distributed to that buffer. By sending the payloads from these buffers to the same data signal line bus, the collision of the time slots on the data lines cannot be structurally generated, and the signals from the multiple buffers are buffered by the cell assembling unit. It is possible to efficiently form cells without providing the above, and it is possible to reduce the amount of hardware.

By transmitting the cell timing signal for granting the cell transmission permission to the plurality of buffers so as to comply with the parameters defined for each buffer, each connection having a plurality of attributes is connected. Shaping can be applied, and cell formation corresponding to a plurality of VCs can be performed by a single cell formation unit.

Considering the case where the information in the plurality of buffers are transmitted on different VCs, the buffer unit determines which VC the data transmitted to the cellifying unit belongs to. To notify. At this time, the information about which VC belongs to which the cell assembling unit is notified is not notified as it is in the form of a VC identifier (referred to as VCI), but a number corresponding to a VCI that is a channel number (referred to as a CH number) is previously set. It may be configured such that it is set, and this is notified to the cell assembling unit, and the cell assembling unit has a correspondence table of this CH number and VCI.

Data transmission on the data signal line from the buffer section to the cell assembling section is transmitted to the cell assembling section leaving an area for the AAL / SAR header / trailer and ATM header. By doing this, the cell assembling unit becomes AA
The ATM cell can be generated by inserting the L / SAR header / trailer and the ATM header into the data of the data transmission signal line, and the data transmission speed can be improved without temporarily storing the data after the cell assembling unit. An ATM cell can be generated without changing, and high-speed cell formation processing is possible.

When the above CH number is notified from the buffer section to the cell assembling section, the data on the data signal line is transmitted by leaving the ATM header or the area of the ATM header and the AAL / SAR header / trailer. It is possible to reduce the number of signal lines by adding the above-mentioned CH number to and transmitting.

If the cell timing signal in the direction from the cellizing section to the buffer section has a length that matches the lengths of the ATM header and AAL header trailer, the other party is notified of the timing of cell transmission or cell processing. In addition to the above, the buffer section can use it as an enable signal indicating where transmission information can be transmitted, and the cell assembling section can use it as a selection signal indicating at which position the header should be inserted.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an AT according to an embodiment of the present invention.
1 shows a configuration of an M communication cell assembling apparatus.

This ATM communication cell assembling apparatus comprises a physical layer processing section 11, an ATM layer processing section 12, and an AAL.S.
It is composed of an AR sublayer processing unit 13, an AAL / CS sublayer processing unit 14, and a higher layer processing unit 15.

The physical layer processing section 11 processes the physical layer according to the protocol layer structure shown in the CCITT recommendation. The ATM layer processing unit 12 similarly processes the ATM layer, and the AAL / SAR sublayer processing unit 13 performs the AAL / SAR sublayer process.
The CS sublayer processing unit 14 performs the processing of the AAL / CS sublayer, and the higher layer processing unit 15 performs the processing of the higher layers higher than the data link layer.

Each of the layer processing units 12 to 15 or the sub-layer processing unit 14 excluding the higher layer processing unit 11 has a sequencer structure, and the processing for each cell or each packet is performed using a hardware sequencer.

Between the physical layer processing unit 11 and the ATM layer processing unit 12, a clock signal line (referred to as BCK) 101 for indicating bit timing, and a cell timing signal line (for indicating the timing of cell processing to the other party ( CCK) 102, data signal line 103 for data transmission, and signal line for notifying the physical layer processing unit whether the data is significant or insignificant (called a significant / insignificant signal)
104 is provided.

Similarly, the ATM layer processing unit 12 and the A
A BCK signal line 111, a CCK signal line 112, a data signal line 113, and a significant / insignificant signal line 114 are provided between the AL / SAR sublayer processing units 13.
Between the R sublayer processing unit 13 and the AAL / CS sublayer processing unit 14, a BCK signal line 121, a packet timing signal line (referred to as PCK) 122 for indicating the packet processing timing to the other party, and a data signal line 123 are provided. The BCK signal line 131, the PCK signal line 132, and the data signal line 133 are provided between the AAL / CS sublayer processing unit 14 and the higher layer processing unit 15.

The higher layer processing section 15 carries out processing of the data link layer and above and passes the data to the AAL / CS sublayer 14 as an AAL service data unit (referred to as SDU). At that time, the higher layer processing unit 15 uses the AAL
-As a timing signal for sending AAL-SDU to the CS sublayer 14, a PCK signal indicating the beginning thereof is also sent. The PCK signal is a signal that becomes H level in the first 1 bit of the packet and becomes L level in other areas. In FIG. 2, signal lines 131 to 133 transmitted and received between the higher layer processing unit 15 and the AAL / CS sublayer processing unit 14 are shown.
An example of the timing chart of each signal above is shown. In the case of this example, it is assumed that the AAL-SDU also includes information indicating its length.

The AAL / CS sublayer processor 14 receives the AAL / CS-SDU passed from the higher layer processor 15.
AAL / CS sublayer processing is added to create an AAL / CS sublayer protocol data unit (referred to as PDU), and the unit is passed to the AAL / SAR sublayer processing unit 13. This processing is performed by the sequencer processing using the PCK sent from the higher layer processing unit 15 as a start signal. In addition, the AAL / CS sublayer processing unit 14 uses the AAL / SA
As a timing signal for sending the AAL / CS-PDU to the R sublayer processing unit 13, a PCK signal indicating the beginning thereof is also sent. This PCK signal is the first 1 in the packet.
It is a signal that becomes H level in bits and becomes L level in other regions. FIG. 3 shows an example of a timing chart of signals on the signal lines 121 to 123 exchanged between the AAL / CS sublayer processing unit 14 and the AAL / SAR sublayer processing unit 13. Even in the case of this example, AAL-
It is assumed that the CS-PDU contains information indicating its length.

The AAL / SAR sublayer processing unit 13
AAL passed from the AAL / CS sublayer processing unit 14
-AAL-SAR sublayer processing is added to SAR-SDU to create an AAL-SAR-PDU, which is passed to the ATM layer processing unit 12. This processing is performed by the sequencer processing using the PCK sent from the AAL / CS sublayer processing unit 14 as a start signal. The data passed to the ATM layer processing unit 12 is divided by the AAL / SAR sublayer processing unit 13 into the payload length of the ATM cell. This becomes AAL / SAR-PDU, and A
It is sent to the ATM layer processing unit 12 leaving a position where the TM header will be inserted.

At this time, the AAL / SAR sublayer processing unit 13 also transmits the CCK signal indicating the beginning thereof to the ATM layer processing unit 12 as a timing signal for transmitting the AAL / SAR sublayer-PDU. This CCK signal is a signal that becomes H level in the first 5 bits of the cell and becomes L level in other regions. At the same time, it also sends a significant / insignificant signal for determining whether the signal currently being transmitted is significant or insignificant. This signal is, for example, an H level signal when the currently transmitting cell is significant and an L level signal when the currently transmitting cell is insignificant. This signal changes in synchronization with CCK. Figure 4 shows AAL / SA
An example of a timing chart of signals on the signal lines 111 to 114 exchanged between the R sublayer processing unit 13 and the ATM layer processing unit 12 is shown.

The ATM layer processing unit 12 uses the AAL / SA
ATM layer processing is added to the ATM-SDU passed from the R sublayer processing unit 13 to create an ATM-PDU, which is passed to the physical layer processing unit 11. This process is AAL ・ SA
This is performed by sequencer processing using CCK sent from the R sublayer processing unit 13 as a start signal. The ATM layer processing unit 12 also transmits a CCK signal indicating the beginning of the ATM layer-PDU as a timing signal for transmitting the ATM layer-PDU to the physical layer processing unit 11. This C
The CK signal is at the H level at the first 5 bits of the cell and at the L level in the other regions. At the same time, the ATM layer processing unit 12 also sends to the physical layer processing unit 11 a significant / insignificant signal for determining whether the signal currently being sent is significant or unsigned. This signal is an H level signal when the currently transmitting cell is significant, and an L level signal when it is insignificant. This signal changes in synchronization with CCK. In Figure 5,
An example of a timing chart of signals on the signal lines 101 to 104 transmitted and received between the ATM layer processing unit 12 and the physical layer processing unit 11 is shown.

The physical layer processing unit 11 performs physical layer processing on the ATM-PDU passed from the ATM layer processing unit 12, and sends the physical layer-PDU to the physical transmission medium. This processing is performed by the C sent from the ATM layer processing unit 12.
This is performed by a sequencer process using CK as a start signal. When the signal on the significant / insignificant signal line 104 sent from the ATM layer processing unit 12 is at L level, the physical layer processing unit 11 inserts an empty cell at this position to match the transmission line speed. Try. Physical layer processing unit 11
The transmission form in the transmission line, which is the output of the above, may be a full ATM flow or a container flow of a synchronous interface such as SDH.

FIG. 6 is a block diagram more specifically showing the ATM communication cell assembling apparatus of FIG. This cell assembly device includes a transmission information generation unit 201, a buffer unit 202, a cell conversion unit 203, a physical layer processing unit 204, and a control unit 2.
It consists of 05. The transmission information generation unit 201 has a function of generating information to be transmitted, packetizing this, and passing it to the buffer unit 202. The buffer unit 202 (a) temporarily stores the packet received from the transmission information generation unit 201 and adjusts the speed with the cell assembling unit 203, and (b) when the cell assembling unit 203 makes a request. It is determined according to the function of dividing a packet from an ATM cell into a size obtained by removing the ATM header and AAL header / trailer parts, and (c) the cell timing signal (called CCK) sent from the cell assembling unit 203. A function of passing transmission information to the cell assembling unit 203 at a timing, and (d) whether the transmitted information is significant or insignificant, and which VC the transmitted information belongs to. Identification channel number (CH
Number) and the information about the length of the transmitted AAL / CS-PDU to the cell assembling unit 203. The cell assembling unit 203 has a function of adding an AAL header / trailer and an ATM header to the information sent from the buffer unit 202 to generate an ATM cell. The physical layer processing unit 204 inserts an empty cell to match the transmission line speed when the cell assembling unit 203 and the buffer unit 202 do not have information to be transmitted, according to the physical layer specifications of the CCITT recommendation. It has a function and a function of performing HEC calculation and scrambling for cell synchronization and transmitting the cell to the physical transmission medium. The control unit 205 has a function of controlling each of these units 201 to 204.

The correspondence relationship between FIG. 6 and FIG. 1 will be described. The transmission information generation unit 201 and the higher layer processing unit 15 and AAL.
The CS sublayer processing unit 14 performs the processing, and the buffer unit 2
02 and the cell conversion unit 203 perform the processing of the AAL / SAR sublayer processing unit 13 and the processing of the ATM layer processing unit 12,
The physical layer processing unit 204 performs the processing of the physical layer processing unit 11.

In FIG. 6, the transmission information sending unit 201 and the buffer unit 202 are connected by an interface 51. This interface 51 is a bit clock B
CK1 signal lines 251-1 to 251-3, packet transmission timing PCK signal lines 252-1 to 252-3, data signal lines 253-1 to 253-3 and flow control RE.
It is composed of ADY signal lines 254-1 to 254-3. In this example, the buffer unit 202 has three buffers, and correspondingly, three signal lines 251 to 254 are also provided.

BCK1 signal lines 251-1 to 251-3
Is a bit timing clock of a signal on another signal line connecting the transmission information generation unit 201 and the buffer unit 203.
The data signal lines 253-1 to 253-3 are 8-bit parallel and send the transmission information from the transmission information generation unit 201 to the buffer unit 202. In this case, the transmission information is AALCS-
Although it is sent in the form of PDU, the packet sending timing PC
The K signal lines 252-1 to 252-3 send a signal from the transmission information generating unit 201 to the buffer unit 2 that outputs an H level signal in the first 1 bit of this packet and an L level signal in other regions.
Send to 02.

Flow control READY signal line 254-1
˜254-3 is L when the storable memory amount in the buffer is less than a certain value, that is, when the buffer unit 202 cannot take in the information even if the information is sent from the transmission information generating unit 201. The level is set, and in other cases, that is, when the buffer unit 202 can capture the information sent from the transmission information generation unit 201, the buffer unit 202 sends a signal to the H level to the transmission information generation unit 201. These signal lines 254-1 to 254-3 are L
In the case of the level, the transmission information generation unit 201 controls the transmission rate by lowering the bit rate of the transmission information. Flow control of the buffer is performed by the signal lines 254-1 to 254-3.

Here, the above packet is AAL / SAR-
The payload of the PDU, that is, the length of the payload of the ATM cell minus the length of the AAL / SAR header / trailer, is an integral multiple of the length. When this information is packed in the ATM cell, the payload There is no loss of transmission information on the way. However, the packet length passed from the transmission information generation unit 201 to the buffer unit 202 is variable within the range of an integral multiple of the payload. Therefore, information on how many times the length of this packet is the payload length of the cell is information on the data signal lines 253-1 to 253.
-3 is included in the signal and transmitted to the buffer unit 202.

The buffer unit 202 and the cell assembling unit 203 are connected by an interface 52. This interface 52 is from the cell assembling unit 203 to the buffer unit 202.
There are a bit clock BCK2 signal line 261 and a cell transmission timing CCK signal line 262 as signal lines heading to the cell, and a data signal line 263 and a significant / insignificant signal line 264 as signal lines heading from the buffer unit 202 to the cell assembling unit 203. . The BCK2 signal line 261 is a signal line for transmitting a timing clock of a signal on another signal line. The CCK signal line 262 is connected to the AT at a timing when the cell assembling unit 203 wants the buffer unit 202 to send a cell.
It is a signal line that is at the H level for the length of the ATM header of the M cell, and is at the L level during the other time, that is, while the ATM header is removed from the ATM cell. Start the internal hardware sequencer by observing the rising edge of.

The data signal line 263 is used for the buffer section 202.
The signal line 2063 is an 8-bit parallel signal line used when information is transmitted from the cell conversion unit 203 to the cell conversion unit 203.
As described above, the above data is transmitted in synchronization with the timing clock on the CCK signal line 262, and the ATM cell outputs A
It is stored in the area excluding the TM header and AAL / SAR header / trailer. Further, the effective bit rate of the data put on the data signal line 263, that is, the product of the frequency of the bit clock and the parallelism is equal to the bit rate sent from the physical layer processing unit 11 to the transmission physical medium. In this case, it is assumed that the transmission mode is full ATM, but the case of using a synchronous interface such as SDH will be described later.

The data transmitted from the buffer unit 202 to the cell assembling unit 203 is the first block of the CS-PDU (a block means one unit obtained by cutting the CS-PDU into the length of the AAL / SAR payload). If so, a flag pattern indicating that effect is set in the first byte of the area for inserting the ATM cell header on the data signal line 263, and the next 1 byte is used to determine the number of blocks of the CS-PDU. The cell assembling unit 203 is notified of information on whether to continue. Further, even when the data transmitted from the buffer unit 202 to the cell assembling unit 203 is the final block of the CS-PDU, a flag indicating that fact is similarly set and the cell assembling unit 2 is set.
However, since the CS-PDU has a length that is an integral multiple of the AAL / SAR payload, the block is A
There is no need for notification of where the AL / SAR payload ends.

As described above, the CS-PDU is AAL
-If the final block is not necessarily an integral multiple of the SAR payload and may end in the middle of the SAR payload, the last block is set to AAL / SAR by using the 1 byte next to the flag indicating the final block. The cell conversion unit 203 is notified of information about where the payload ends. FIG. 10 shows a format of data flowing on the data signal line 263.

The block currently being sent is CS-
The buffer unit 202 recognizes information as to whether it is the first block of the PDU, the block in the middle, the last block, or the single block, and the information indicating the recognition result is directly converted into a cell. The unit 203 may be notified. In this case, the cell assembling unit 203 determines that the block is C
It is not necessary to have a function of analyzing which information type of the S-PDU belongs to.

The significant / insignificant signal line 264 is a signal line which becomes H level when the information flowing on the data signal line 263 is significant, and becomes L level when it is meaningless.
It is a signal line that changes every cell, that is, in synchronization with the beginning of the cell. The signal on this signal line 264 is the first 1 bit of the cell. If the data flowing on the data signal line 263 in parallel is significant, it indicates H level, and if it is insignificant, it indicates L level. CH number, next 1 bit is CL
Indicates P (Cell Loss Priority). L if CLP is 0
If the level is 1, the H level is inserted. The CH number will be described later. In this case, since the CH number is 3 bits, the CH number performed in the cell assembling unit 203 is V
Up to 8 keys can be used for conversion to PI / VCI.
Here, the AAL · S placed on the data signal line 263
Information other than the AR payload is information terminated in the AAL / SAR layer, and information other than the significant / insignificant information placed on the significant / insignificant signal line 264 is information terminated in the ATM layer.

Cellularizing unit 203 and physical layer processing unit 204
An interface 53 is used to connect between and. The interface 53 includes a bit clock BCK3 signal line 271, a cell transmission timing CCK signal line 272, a data signal line 273, and a significant / insignificant signal line 274. The BCK3 signal line 271 is a signal line for transmitting a timing clock of a signal on another signal line between the cell assembling unit 203 and the physical layer processing unit 204, and this timing clock is the timing clock on the BCK2 signal line 261 described above. It has the same bit timing as. The CCK signal line 272 is a signal line for notifying the timing of the beginning of the cell sent from the cell assembling unit 203 via the data signal line 273, and is at the H level for the length of the ATM header of the ATM cell. In the meantime, that is, while the ATM header of the ATM cell is removed, the signal line is at the L level. The physical layer processing unit 204 uses the CCK signal line 27.
The internal hardware sequencer is started by observing the rising edge of the signal on 2 and cell processing is performed.

The data signal line 273 is an 8-bit parallel signal line used when information is sent from the cell assembling unit 203 to the physical layer processing unit 204, and the data on this data line 273 is as described above. It is transmitted in synchronization with the timing clock on the CCK signal line 272. in this case,
An invalid bit pattern is contained in a time slot in which a valid cell of the signal on the data signal line 273 is not contained.
This invalid bit pattern is a bit pattern of "01101010" in order from the MSB used as the pattern of the payload part of the empty cell in the CCITT recommendation.

The significant / insignificant signal line 274 is a signal line which becomes H level when the data flowing on the data signal line 273 is significant and becomes L level when it is meaningless. That is, the signal line changes in synchronization with the rising edge of CCK.

Next, the flow of the cell assembling process in the cell assembling apparatus shown in FIG. 6 will be described. Transmission information generation unit 201
Generates the information to be transmitted and sends this to the AALCS-
It is stored in a PDU and passed to the buffer unit 202. At that time, BC
K1 signal lines 251-1 to 251-3, PCK signal line 25
2-1 to 252-3, data signal lines 253-1 to 253
-3 and each signal on the READY signal lines 254-1 to 254-3 are passed to the buffer unit 202 according to the timing chart shown in FIG. The signal passing operation on these signal lines may be performed in parallel corresponding to each of the plurality of buffers in the buffer unit 202. The frequencies of the timing clocks on the BCK1 signal lines 251-1 to 251-3 may be different from each other,
It may be different from the frequency of the timing clock on the BCK2 signal line 261.

The cell assembling section 203 has time slots for transmitting cells, and when it is necessary to transmit information other than user cells such as signaling cells and OAM cells, these cells are set as the time slots. The buffer unit 2 is stored at a timing when it is not necessary to send these cells.
A timing clock indicating the cell transmission timing is sent to the 02 through the CCK signal line 262 to prompt the buffer unit 202 to transmit the cell. Therefore, even if the information to be sent is inside, the buffer unit 202 cannot send the information data if the timing clock is not given from the cell assembling unit 203 via the CCK signal line 262. Become.

The buffer in the buffer unit 202 activates the internal sequencer to send the transmission information to the cell assembling unit 203 only when the cell sending timing is acquired from the cell assembling unit 203 through the CCK signal line 262. in this case,
CCK from the buffer unit 202 toward the cell conversion unit 203
Transmission data is transmitted on the data signal line 263 in synchronization with the timing clock on the signal line 262. At this time, when the data transmitted from the buffer unit 202 to the cell assembling unit 203 is the first block of the CS-PDU, it is left blank for inserting the ATM cell header on the data signal line 263 as described above. Set a flag pattern to that effect in the first byte of the area, and use the next 1 byte to
Information on how many blocks of S-PDU continues is provided to the cell assembling unit 20.
Notify 3. In addition, from the buffer unit 202 to the cell conversion unit 2
If the data sent to the terminal 03 is the last block of the CS-PDU, a flag indicating that fact is set and notified to the cell assembling unit 203. However, the CS-PDU uses the AAL / SAR.
Since the length is an integral multiple of the payload, it is not necessary to notify where the final block ends in the AAL / SAR payload.

As described above, the CS-PDU is AAL
If it is not necessarily an integral multiple of the SAR payload, the cellizing unit 203 uses the 1 byte next to the flag that the block is the final block to provide information on where the final block ends in the AAL / SAR payload. To notify. The buffer unit 202 does not send any information even if a signal prompting the information sending from the cell assembling unit 203 is given through the CCK signal line 262, that is, does not send any information, that is, the data signal line. Involuntary information will flow on 263. The significant / insignificant signal line 264 is
When the data signal flowing on the data signal line 263 is significant information, it is H level, when it is insignificant information, or when the CCK signal is not sent from the cell assembling unit 203 to the buffer unit 202, information is sent. If there is not, the L level is set to the 1st bit of the cell, the CH number is set from the 2nd bit to the 4th bit, the CLP is set to the 5th bit, and thereafter, if it is significant, it is the H level, and if it is insignificant, it is the L level. Is a signal line that stands. The level change, which is significant or insignificant, occurs in synchronization with the cell transmission timing. In addition,
After the cell heading timing signal 262 is sent from the cell assembling section 203 to the buffer section 202,
The time until 3 receives data from the buffer unit 202 is defined as, for example, a 1-bit clock.

FIG. 11 shows the internal structure of the buffer section 202. As shown in the figure, the buffer unit 202 includes a buffer control unit 301 and three buffers # 1 to # 3 (302
-1 to 302-3), a data bus 303 and a significant / insignificant signal bus 304. When the cell head timing signal sent from the cell assembling unit 203 via the CKK signal line 262 is input to the buffer control unit 301, the buffer control unit 301 causes the buffers 302-1 to 302-3.
, And transmits the cell head timing signal to the buffer as a data transmission permission signal. When selecting a buffer, the buffer control unit 301 gives a data transmission permission signal to the buffer in a form that complies with the traffic parameters defined at the time of call setup. Since the buffer cannot send data at the timing when the data transmission permission signal does not come, as long as the timing when the data transmission permission signal arrives satisfies the communication condition, the cell must be always transmitted to the safe side. And shaping will be performed.

The data transmission from the buffer is carried out to the data bus 303 provided in common for each buffer. At that time, if the data being transmitted is the first block of the CS-PDU, as shown in FIG. 10, a flag indicating the fact is sent to the first byte of the area where the ATM header will be inserted, and the CS-PDU is Information on how many times the length of the AAL / SAR payload has is stored in the second byte. In addition, the buffer transmitting the data sends the information indicating whether the information is significant or insignificant to the significance / insignificance signal bus 304 in synchronization with the cell transmission timing signal on the CCK signal line 262. The CH number of the information in the bit, the CLP of the information in the next 3 bits,
It is stored in the next 1 bit and transmitted. Here, the CH number may be a fixed value such as the buffer number when one buffer does not have a plurality of connections at the same time. In this case, the data bus of the buffer for which the information transmission permission has not been obtained,
The gate to the significant / insignificant bus is in a high impedance state. These data buses and significant / insignificant signal buses are physically assigned to only one buffer in a time-sharing manner because the data transmission enable signal is given to only one buffer. Multiplexing of significant / insignificant signals can be efficiently performed without providing a further buffer in the subsequent stage.

These signal lines, that is, the BCK2 signal line 261 and the CC from the cell assembling unit 203 to the buffer unit 202.
K signal line 262, buffer unit 202 to cell conversion unit 203
Data signal line 263 and significant / insignificant signal line 264 toward
Each of the above signals changes according to the timing chart as shown in FIG.

After that, the cell assembling unit 203 uses the AAL / SAR.
The header / trailer is added and the ATM header is added in order. Since the data on the data signal line flowing in the cell assembling unit 203 is stored in the area excluding the header / trailer portion, these can be added by inserting it in the empty portion, and the clock can be added. No transfer is required. After inserting signaling cell and OAM cell,
This is sent to the physical layer processing unit 204. These operations are performed in hardware by the sequencer operation by using the rising signal of the CCK signal line 272 as a trigger.

FIG. 12 shows the internal structure of the cell conversion unit 203. The cell conversion unit 203 includes an AAL / SAR header / trailer addition unit 401 and an ATM header / payload combination unit 4.
It consists of 02. The AAL / SAR header / trailer adding unit 401 adds A to the data received from the buffer unit 202.
It has a function of adding an AL / SAR header and a trailer to create an ATM cell payload and passing it to the ATM header / payload combining unit 402.

FIG. 13 shows the internal structure of the AAL / SAR header / trailer adding unit 401. Like this, AAL
The SAR header / trailer providing unit 401 includes a CH number analysis unit 501, a length analysis unit 502, a counter 503, a selector 504, an information type analysis unit 505, a selector 506, and a CRC calculation unit 507.

The CH number analysis unit 501 uses the CCK signal line 2
Referring to the first bit of the significant / insignificant signal line from the buffer unit 202 in synchronization with the cell transmission timing signal on 62,
If significant, analyze the CH number with reference to the following 3 bits. As a result, a timing signal is sent to the counter 503 corresponding to the CH number associated at the time of call setup, and the counter 503 increments one cell at a rate of "1" corresponding to the CH number. The count value of the counter 503 is sent to the selector 504 so as to be inserted into the sequence number in the AAL / SAR header, and the count value of the counter corresponding to the corresponding CH number is selected and sent.

The length analysis unit 502 uses the CCK signal line 262.
Data signal line 2 in synchronization with the above cell transmission timing signal
The data on 63 is referred to, and the first byte of the data is AA
If the flag indicating that it is the first block of the L-CS-PDU is set, the counter 503 corresponding to the CH number of the data is reset, and the length information inserted in the next 1 byte is set as information. Notify the type analysis unit 505. This length information is a value that is an index of how many SAR payloads are continuously sent in the CH number.

The information type analysis unit 505 is the length analysis unit 5
The length information notified from 02 is compared with the count value of the counter 503 corresponding to the corresponding CH number, and the BOM (Beginning of Mess) is performed according to the flowchart shown in FIG.
age), COM (Continuation of Message), EOM (End
Information types such as of Message) and SSM (Single Segment Message) are determined and notified to the selector 506.
That is, when the information analysis unit 505 receives the data of the length information (N) from the length analysis unit 502, it refers to the count value (C) of the counter 503 corresponding to the CH number of the data, Both are compared (S1-S
3). As a result of this comparison, if N = C, the information type is S
It is determined to be SM (S4), and if not, the information type is determined to be BOM (S5). Next, when the cell transmission timing signal (CCK) on the CCK signal line 262 is received, the information type analysis unit 505 similarly outputs the length information from the length analysis unit 502 at that time and the CH of the data of this length information. The count value of the counter 503 corresponding to the number is referred to and the two are compared (S6 to S8). As a result of this comparison, if N> C, it is determined that the information type is COM (S8 to S9), and if N = C, the information type is EOM.
Is determined (S10 to S11).

The selector 506 performs a sequencer process using one of the data on the data signal line 263, the output of the selector 504 and the output of the information type analysis unit 505 as the activation signal of the cell transmission timing signal on the CCK signal line 262. It is selected and output to the CRC calculation unit 507. In this case, the selection is AA of the ATM cell as shown in FIG.
It is performed by inserting it at an appropriate position so as to comply with the L format.

The CRC calculation unit 507 removes CRC from A
CRC operation of AL / SAR header, SAR payload and SAR trailer is performed, and the result is AA of ATM cell
Insert at an appropriate position so as to follow the L format. With the above operation, the functions of the AAL / SAR header / trailer addition unit are completed. The CS-PDU sent from the buffer unit 202 always has a length that is an integral multiple of the SAR payload, and if a fixed value (numerical value indicating Full) is entered in the length information in the SAR trailer format. For good reason, no analysis is needed in this case as to where in the final block the data is located in the SAR payload. However, CS-PDU is not always S
When the length information in the SAR format does not have to be an integral multiple of the length of the AR payload, it is necessary to analyze the length information in the SAR format in the form of a flag indicating the last block of the CS-PDU. The next 1
The length analysis unit 502 decodes this in the form of having the length information indicating how many bytes of information the block is, and notifies the information type analysis unit 505 of the decoding result. It takes the form of inserting information into the AAL trailer at the appropriate location.

FIG. 16 shows the ATM header of FIG.
The internal structure of the payload combining unit 402 is shown. Thus, the ATM header / payload combining unit 402 is composed of the cell header creating unit 601, the header / payload combining unit 602, the signaling cell / OAM cell generating unit 603, and the selector 604.

The cell header creation unit 601 refers to the first bit of the signal on the significant / insignificant signal line 264 in synchronization with the cell transmission timing signal on the CCK signal line 262, and if significant, the next 3 bits are read. Referring to the data signal line 26
3 analyzes the CH number of the data signal sent in parallel. The cell header creation unit 601 uses the CH number and VPI /
It is provided with a table that has VCI values as elements in a one-to-one correspondence. This table shows which CH number and which V
The control unit 205 provides information on whether the PI / VCI values correspond.
This information has been written in and obtained from. The cell header creation unit 601 acquires the VPI / VCI value to be inserted in the data by using the CH number read from the significant / insignificant signal line 264 as a key by referring to the above table. In this case, a plurality of CH numbers may correspond to one VPI / VCI value. In addition, significant
The CLP of the cell is acquired by referring to the next 1 bit on the involuntary signal line. In addition, GFC (Generic F
low control), PT area is set appropriately, and then ATM
Generate a cell header. In this case, HEC (HeaderError
For the control pattern, all 0's are inserted. The ATM header / payload combining unit 602 is added to the empty portion of the data sent from the previous stage (that is, the portion in which the ATM cell header is inserted) by the ATM cell header created here.
The ATM cell (referred to as a user cell) is generated by inserting it in (1) and is sent to the selector 604 in the next stage.

Further, when the control unit 205 recognizes that it is necessary to transmit the signaling cell or the OAM cell, the cell transmission timing signal is not transmitted to the CCK signal line 262 to the buffer unit 202, and the signaling cell / OAM cell is not transmitted. The cell generation unit 603 generates a signaling cell or an OAM cell and sends this to the selector 604 in the next stage.

These user cells or signaling cells / OAM cells are synchronized with the cell transmission timing signal on the CCK signal line 262 in synchronization with the selector 6 at the same timing.
Sent to 04. At the transmission timing of the signaling cell / OAM cell, etc., the cell transmission to the buffer unit is not prompted, so that the user cell and the signaling cell / OA
M cells and the like do not collide at the same cell transmission timing.

The selector 604 multiplexes the user cell flow from the header / payload combination unit 602 or the cell flow from the signaling cell / OAM cell generation unit 603,
A single ATM cell stream and signaling cell
Significant / insignificant signal line 274 while OAM cells are flowing
Is fixed to the H level meaning significant, and is transmitted to the physical layer processing unit 204 at the next stage.

When it is sent to the physical layer processing unit 204,
The signals on the BCK3 signal line 271, the CCK signal line 272, the data signal line 273, and the significant / insignificant signal line 274 are
It is passed to the physical layer processing unit 204 according to the timing chart as shown in FIG.

FIG. 17 shows the internal structure of the physical layer processing section 204. In this way, the physical layer processing unit 204 is generated by the empty cell insertion unit 701, the HEC generation unit 702, the scramble unit 703, and the transmission physical medium conversion unit 704.

The empty cell inserting unit 701 discriminates the significant / insignificant information of the cell sent from the cell assembling unit 203 via the significant / insignificant signal line 274, and is at the L level, that is, the data signal line if it is insignificant An empty cell or a physical layer OAM cell is inserted into the time slot of the cell on the H.273, and the significant cell is allowed to pass through to match the speed of the transmission line.
It has a function of sending to the HEC generator 702 of the next stage.

The HEC generator 702 is provided with the data signal line 27.
The HEC of the ATM cell flow which flows over 3 is connected to the CCK signal line 27.
2 has a function of calculating and inserting in synchronization with the cell transmission timing signal on the second cell and transmitting it to the scramble unit 703 of the next stage. The scrambler 703 has a function of scrambling the data signal and sending it to the transmission physical medium converter 704 in the next stage.

The transmission physical medium conversion unit 704 has a function of converting a data signal so as to be suitable for the transmission physical medium and transmitting the data signal to the transmission physical medium. For example, when the transmission physical medium is an optical cable, electricity-> optical conversion is performed.

In the above case, the transmission format of the transmission physical medium is assumed to be full ATM, but SDH (Synchronous Dig
If a synchronous interface such as ital Hierarcy) is used in the transmission format, an SDH compatible section is provided between the HEC generation section 702 and the scramble section 703 in the physical layer processing section 204, and here, a full ATM cell stream to an SDH container Mapping to the stream will be done. In this case, between the buffer unit 202 and the cell conversion unit 203,
Also, the effective bit rate of the data signal line between the cell assembling unit 203 and the physical layer processing unit 204 is the transmission speed of the synchronous interface minus the overhead of SOH and POH.

Further, in the cell assembling apparatus having the above-mentioned configuration, the significant / insignificant signal line may not be specially prepared, and the data signal line may have the role thereof. In that case, the significant / insignificant signal lines 264 and 274 in FIG. 6 are removed, and the data signal line 26 between the buffer unit 202 and the cell assembling unit 203 is removed.
3, the signal format on FIG. 3 is set to the signal line 272 between the cell assembling unit 203 and the physical layer processing unit 204.
The signal format on ˜274 may be the same as in FIG. By doing so, the number of signal lines between modules can be reduced, and since the PT and CLP are brought to the regular positions, the ATM layer processing unit 12
By passing this through, it is possible to reduce the amount of hardware. In the case of this configuration, FIG.
Buffers 302-1 to 302-1 in the buffer unit 202 shown in FIG.
The signal 302-3 may send a signal to the data bus 263 in the format shown in FIG. 18 (the significance / insignificant signal bus 264 is unnecessary). Also, the AAL / SAR of FIG.
In the header / trailer providing unit 401, the significant / insignificant signal line 264 is eliminated, and the data signal line 263 is connected to both the length analysis unit 502 and the CH number analysis unit 501. The length analysis unit 502 refers to the first block bit, the last block bit, and the length information, and the CH number analysis unit 501 refers to the CH number.
The same operation as when the unintentional signal line 264 is present is performed. However, the information on the data signal line 263 is rewritten in the format as shown in FIG. 19 and sent to the ATM header / payload combining section 402. Significant / unconscious signal line 2
64 to ATM header / payload combining section 40 in FIG.
It does not branch to 2.

In this case, the ATM header / payload combining section 402 of FIG. 12 has a structure as shown in FIG. 21, and the data on the data signal line 263 is directly input to the cell header creating section 601. Here, the data on the data signal line 263 is received in the format as shown in FIG. 18, and the cell header creation unit 601 controls the generation of the cell header by referring to the significant / insignificant bit of the data. Also, refer to the CH number,
Use this as a key to refer to the table and add VPI / VC
The I value is looked up, which determines the VPI / VCI value of the header. In addition, GFC is properly determined, and PT, C
An ATM header is created by passing the LP bits through, and this is the header / payload combining unit 60.
At 2, the user cell is combined with the ATM payload. In the header / payload combination unit 602, an ATM header is added as in the case of FIG. In addition, the cell header creation unit 601 generates a signal to the significant / insignificant signal line. This signal is at H level if significant, and at L level if it is insignificant in synchronization with the cell transmission timing signal on the CCK signal line 262. However, the cell is output from the signaling cell / OAM cell generation unit 603. When the signal is sent out, the selector 504 resets the signal to the H level which is significant. The function of the signaling cell / OAM cell generation unit 603 is the same as in the case of FIG. The selector 504 also distributes user cells and control cells.

[0078]

As described above in detail, according to the present invention, A
A signal line for transmitting a timing signal indicating the beginning of a cell or a data unit is provided between each layer processing unit in the TM communication system, and at least one layer processing unit starts processing for each cell according to the timing signal.
By adopting a configuration in which cell processing is performed by a sequencer, high-speed cell processing required for high-speed and real-time communication of image information can be performed using a hardware sequencer, which is suitable for fixed-length packet communication processing. Can be configured. Moreover, since the processing is divided for each layer, it is possible to realize a cell assembling apparatus having a flexible configuration suitable for changing the specification of a certain layer and coping with layers having different specifications.

In a preferred embodiment of the present invention, the cell assembling apparatus comprises a buffer unit for accumulating transmission information and a cell assembling unit for assembling cells, and the cell assembling unit stores the ATM cell payload or AAL / SAR payload in the buffer. Is transmitted, and the buffer unit is configured to transmit the payload to the cell formation unit by leaving the ATM header or the ATM header and the adaptation header / trailer portion in accordance with this timing signal, and further transmitting cells other than user information. At the timing to be issued, the timing signal is not transmitted to the buffer unit, and the timing of transmitting the timing signal is determined so as to satisfy the traffic condition determined at the time of call setup. A buffer is selected and the data from that buffer is A configuration that is trust.

With such a configuration, data collision does not occur in the cell assembling section, and a shaping function at the time of cell transmission can be provided. Further, in the cell assembling unit, the header / trailer can be formed into cells by inserting it into the data on the data signal line. Therefore, signals from a plurality of buffers can be formed into a plurality of cells without providing a buffer in the cell assembling unit. Since it can be configured without providing any section, the amount of hardware can be reduced.

When the buffer section has a plurality of buffers, when sending the payload to the cell assembling section, the cell assembling section is notified of channel information indicating which logical channel the sending information belongs to. As a result, the cell assembling unit can smoothly make ATM cells of the transmission information for each logical channel.

Further, by providing a significant / insignificant signal line between the buffer section and the cell conversion section, when the buffer section does not have transmission information and significant information does not flow on the data signal line connecting between them. This can be notified to the cell assembling unit.

Further, the channel information is transmitted to the AT on the data line.
By inserting an M header or an AAL / SAR header / trailer in an empty area for insertion and notifying the cell assembling section, channel information can be provided without providing a signal line for that purpose between the buffer section and the cell assembling section. Can be notified to the cell assembling unit, and the amount of hardware can be further reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an ATM communication cell assembling apparatus according to an embodiment of the present invention.

FIG. 2 is a timing chart of signals between a higher layer processing unit and an AAL / CS sublayer processing unit.

FIG. 3 AAL / CS sublayer processing unit and AAL / S
Timing chart of signals between AR sublayer processing units

FIG. 4 is a timing chart of signals between an AAL / SAR sublayer processing unit and an ATM layer processing unit.

FIG. 5 is a timing chart of signals between an ATM layer processing unit and a physical layer processing unit.

FIG. 6 is a more specific configuration diagram of the ATM communication cell assembling apparatus of FIG.

FIG. 7 is a timing chart of signals between a transmission information generation unit and a buffer unit.

FIG. 8 is a timing chart of signals between the cell assembling unit and the buffer unit.

FIG. 9 is a timing chart of signals between the cell conversion unit and the physical layer processing unit.

FIG. 10 is a diagram showing a format of data flowing on a data signal line between a buffer section and a cell conversion section.

FIG. 11 is an internal configuration diagram of a buffer unit.

FIG. 12 is an internal configuration diagram of a cell conversion unit.

FIG. 13 is an internal configuration diagram of an AAL / SAR header / trailer adding unit.

FIG. 14 is a flowchart showing an information type determination procedure in an AAL / SAR header / trailer adding unit.

FIG. 15 is a diagram showing an AAL format of an ATM cell.

FIG. 16 is an internal configuration diagram of an ATM header / payload combining unit.

FIG. 17 is an internal configuration diagram of a physical layer processing unit.

FIG. 18 is a diagram showing a signal format on a data signal line between a buffer section and a cell assembling section in the ATM communication cell assembling apparatus according to the embodiment.

FIG. 19 is a diagram showing a signal format on a data signal line between a cell assembling unit and a physical layer processing unit in the ATM communication cell assembling apparatus according to the embodiment.

FIG. 20 is a diagram showing a signal format on a data signal line between the AAL / SAR header / trailer providing unit and the ATM header / payload combining unit in the cell assembling unit in the ATM communication cell assembling apparatus according to the embodiment.

FIG. 21 is an internal configuration diagram of an ATM header / payload combining unit in the ATM communication cell assembling apparatus according to the embodiment.

[Explanation of symbols]

11 ... Physical layer processing unit 12 ... ATM layer processing unit 13 ... AAL / SAR layer processing unit 14 ... AAL
CS sub-layer processing unit 15 ... Higher layer processing unit 101, 111, 121, 131 ... Signal lines 102, 112 ... Cell timing signal lines 103, 113, 123, 133 ... Data signal lines 104, 114 ... Significant / insignificant Signal lines 122, 132 ... Packet timing signal line 201 ... Transmission information generation unit 202 ... Buffer unit 203 ... Cellularization unit 204 ... Physical layer processing unit 205 ... Control unit 51-53 ... Interface 251 ... Bit clock signal line 252 ... Packet transmission Timing signal line 253 ... Data signal line 254 ... Flow control READY signal line 261 ... Bit clock signal line 262 ... Cell transmission timing signal line 263 ... Data signal line 264 ... Significant / insignificant signal line 271 ... Bit clock signal line 272 ... Cell Send timing Signal line 273 ... Data signal line 274 ... Significant / insignificant signal line 301 ... Buffer control unit 302-1 to 30-30
2-3 ... Buffer 303 ... Data bus 304 ... Significant / insignificant signal bus 401 ... AAL / SAR header / trailer providing unit 402 ... ATM header / payload combining unit 501 ... CH number analyzing unit 502 ... Length analyzing unit 503 ... Counter 504 ... Selector 505 ... Information type analysis unit 506 ... Selector 507 ... CRC calculation unit 601 ... Cell header creation unit 602 ... Header / payload combination unit 603 ... Signaling cell / OAM cell generation unit 604 ... Selector 701 ... Empty cell insertion unit 702 ... HEC generation Unit 703 ... Scramble unit 704 ... Transmission physical medium conversion unit

Claims (5)

[Claims] 1. An ATM in which information is made into cells and asynchronously communicated.
In an ATM communication cell assembling apparatus in a communication system, a plurality of layer processing units are hierarchically arranged, and a signal line shown for transmitting a timing signal indicating the head of a cell or a data unit is transmitted between these layer processing units. An ATM communication cell assembling apparatus, wherein at least one layer processing unit starts processing for each cell according to a timing signal on the signal line, and performs cell processing by a sequencer. 2. The plurality of layer processing units include a physical layer processing unit, an ATM layer processing unit, an adaptation layer segmentation and reassembling sublayer processing unit, an adaptation layer convergence sublayer processing unit and a higher layer processing. 2. An ATM communication cell assembling apparatus according to claim 1, further comprising a unit. 3. The ATM layer processing section, the adaptation layer segmentation and reassembling sublayer processing section, the adaptation layer convergence sublayer processing section and the higher layer processing section, and a transmission information generating section for generating transmission information. A buffer unit for accumulating the generated transmission information and a cell assembling unit for composing the transmission information from the buffer unit into cells, and the cell assembling unit includes an ATM cell payload or an adaptation layer segmentation and reassembly in the buffer unit. The buffer unit has means for transmitting a timing signal for sending out a sublayer payload through the signal line, and the buffer unit of the ATM header or the ATM header and the adaptation header trailer matches the timing signal from the cell assembling unit. ATM communication cell assembling apparatus according to claim 2, characterized in that it comprises means for transmitting the payload to the cell unit at a minute. 4. The buffer unit includes an AT from the cell assembling unit.
When a timing signal indicating the timing of sending the M cell payload or AAL / SAR payload is transmitted, the payload is only provided at timings specified to satisfy the parameters satisfying the traffic conditions determined at the time of call setup among these timings. 4. The ATM communication cell assembling apparatus according to claim 3, wherein the cell assembling unit is sent to the cell assembling unit. 5. The buffer section has a plurality of buffers and a buffer control section for controlling these buffers, and when the buffer control section at the time of receiving the timing signal selects one buffer, 4. The ATM communication cell assembling apparatus according to claim 3, wherein said timing signal is sent as an information sending permission signal, and said buffer sends said payload to the same data bus.