JPH0636552A - Serial access memory - Google Patents

Abstract

PURPOSE:To simultaneously execute writing and reading operation by reducing a chip area. CONSTITUTION:A memory cell array consists of memory cells arranged in 10 rows and 100 columns, and a write bit line WB and a read bit line RB are provided at every row, and a write word line WW and a read word line RW are provided at every column. At the time of reading data in every column, charge is performed by that a MOSFET 38 for charge is turned on, and thereafter, one read word line RW is selected and the data in the memory cells on one row are read on the read bit line RB. At the time of writing the data in every column, all write bit lines WB are discharged by that the MOSFET 40 for discharge is turned on, and thereafter, one write word line WW is selected. Then, the data are sent successively at every write bit line WB, and data write in the column is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial access memory suitable for digital signal processing of video signals.

[0002]

2. Description of the Related Art Digital signal processing of video signals is performed in order to realize high image quality and multifunction of television receivers and VTRs. As a memory used for digital signal processing of a video signal, there is a memory used for delaying a video signal by writing and reading the video signal sent at the time of meditation. In such a memory, simultaneous write / read operation is possible. It is essential. As a memory for performing such an operation, for example, as described in Japanese Patent Application Laid-Open No. 62-43894, a dynamic type memory cell (hereinafter referred to as 3MOS type cell) using three MOSFETs as the memory cell. There is a memory cell array using.

The memory cell array will be described below. First, referring to FIG.
The S-type cell will be described. However, in the figure, M
1, M2, M3 are n-type MOSFETs, 39 is 3MOS
Type cell (hereinafter, simply referred to as memory cell), WB is a write bit line, WW is a write word line, RW is a read word line, and R is a read word line.
B is a read bit line, 38 is a p-type MOSFET, and 43 is a power supply.

In the figure, the write operation of the memory cell 39 is performed as follows. That is, the write word line W
When W becomes "H" level, the MOSFET (M1) is turned on and the data inputted from the write bit line WB is MOS.
It is transmitted to the MOSFET (M2) via the FET (M1). In the gate of the MOSFET (M2), a parasitic capacitance is formed between the gate of the MOSFET (M2) and the substrate due to the structure of the integrated circuit (hereinafter referred to as IC), and data is held in this. After that, the write word line WW becomes "L" level and the MOSF
Even if ET (M1) is turned off, the data is MOSFET (M
It is held as it is in the gate parasitic capacitance of 2).

The read operation is performed as follows. First, the read bit charge control signal PC of "L" level is applied to the MOSFET (38), whereby the MOSFE
When T (38) is turned on, the power supply 43 charges the read bit line RB to the "H" level. Next, the read word line RW is set to "H" level to turn on the MOSFET (M3).
At this time, the MOSFET (M2) receives the "L" level data.
When the data is held, the MOSFET (M2) is in the off state, so that the read bit line RB remains "H".
Hold the level. On the other hand, MOSFET (M
If "H" level data is held in 2), the MO
SFET (M2) and MOSFET (M3) turn on,
The read bit line RB is discharged through the MOSFETs (M3) and (M2) and becomes "L" level. That is, MOSFE
The data held in T (M2) is inverted and read on the read bit line RB.

Next, the memory cell 39 is moved in the row direction by m.
A memory cell array configured by arranging a plurality of cells and n cells in the column direction is described with reference to FIG. In the figure, 16 is an input terminal of data DATA to be written, 2
8 is an output terminal of the read data DATA ", 38
(1), 38 (2), ..., 38 (m) are p-type MOS
FET, 39 (1,1), 39 (1,2), ..., 39
(N, m) is the memory cell described in FIG. 12, 43 is a power supply, 53 is a write pointer, 54 is a read pointer, 5
Reference numeral 5 is an inverter, WB1, WB2, ..., WBm are write bit lines, WW1, WW2, ..., WWm are write word lines, RW1, RW2 ,.
B1, RB2, ..., RBn are read bit lines.

The write operation of this memory cell array is performed as follows. That is, the write word line WW1 is "H".
At the level, the memory cell 39 (1,1) in the first column,
39 (1,2), ..., 39 (1, m) MOSFETs
(M1) is turned on, and thereafter, the write pointer 53 applies one bit of data DATA in the order of the write bit lines WB1, WB2, ..., WBm, and the memory cell 3
9 (1,1), 39 (1,2), ..., 39 (1, m)
Are sequentially written in the MOSFETs (M2). Next, the write word line WW2 becomes "H" level, and in the same manner,
The memory cells 39 (2,1), 39 (2,2) in the second column,
.., 39 (2, m) are written, and then data is written in each column.

The read operation is performed as follows. That is, as described above, first, the read bit line charge control signal PC of "L" level is input from the input terminal 26, and the MOSF
ET38 (1), 38 (2), ..., 38 (m) are turned on, and the voltage of the power supply 43 causes the read bit lines RB1 to RB1.
RBn is charged to "H" level. Then, the read bit line charge control signal PC is set to "H" level, and the MOSFE
T38 (1), 38 (2), ..., 38 (m) are turned off to terminate the charging, and the read word line RW1 is set to the “H” level to set the memory cells 39 (1,1), 39 (1). ，
2), ..., 39 (1, m) MOSFETs (M3) are turned on, and these memory cells 39 (1,1), 39 (1,
2), ..., The data held in the MOSFET (M2) of 39 (1, m) is read out from the bit lines RB1, RB2.
..., read to RBm, and then read pointer 5
4, read bit lines RB1, RB2, ..., RBm
, And the data is sequentially output from them.

Next, the read bit line charge control signal PC is input again from the input terminal 26 to read the read bit lines RB1 to RB.
m is charged to the "H" level, the read word line RW2 is set to the "H" level, and the 3rd MOS type cell 39 (2,
Data is read from 1), 39 (2, 2), ... 39 (2, m), and then data of each column is read in the same manner.

In this way, one word line is set to "H".
When the level is set, data writing / reading of m 3MOS type cells becomes possible, and writing / reading of data is carried out one by one by the pointer.

[0011]

However, in such a conventional memory cell array, when the simultaneous write / read operation is performed, the following problems occur depending on the timing of writing and reading.

This problem will be described below. Here, when the read word line RW1 goes to "H" level and the read pointer 54 reads the data to the read bit line RB2, the write operation is performed. It is assumed that the word line WW1 has become "H" level. In this case, the read word line RW
As 1 is first set to the "H" level, as described above, data is read out to all m read bit lines RB1 to RBm at the same time. And, as mentioned above,
Memory cell 3 in which "H" level data is written
The read bit line RB to which 9 is connected is discharged to the “L” level because the MOSFETs (M2) and (M3) of the memory cell 39 are turned on, and
Memory cell 3 in which "L" level data is written
The read bit line RB to which 9 is connected is held at "H" level because the MOSFET (M2) of the memory cell 39 is off.

On the other hand, when the write word line WW1 becomes "H" level, all the MOSFETs (M1) of the memory cells 39 connected to the write word line WW1 are turned on.
Before the write bit line WB is selected by the write pointer 53 and the data is written, the MO of the memory cell 39 is changed.
The gate potential of the SFET (M2) becomes a potential obtained by dividing the difference between the potential of the write bit line WB and the potential due to the gate parasitic capacitance of the MOSFET (M2) by the inverse ratio of these parasitic capacitances. Since the write bit line WB is common to the n memory cells 39, the potential of the write bit line WB before the write word line WW1 is set to the “H” level is the same as the potential of the one before. It has a potential generated by writing to the memory cell 39. Further, the parasitic capacitance of the write bit line WB is considerably larger (several times to several tens of times) than the gate parasitic capacitance of the MOSFET (M2) in the memory cell 39. Therefore, if the write bit line WB is at "H" level before the write word line WW1 becomes "H" level, the write word line WW1 becomes "H" level and the MOSFET (M
When 1) is turned on, the memory cell 39 holding the “L” level data is
Almost "H" level of the write bit line WB is added to the gate of the FET (M2), and the held "L" data becomes "H" level. At this time, in this memory cell 39, since the read word line RW1 is at the "H" level and the MOSFET (M3) is on, the "H" level is held by the "H" level of the write bit line WB. MOSFET (M2) turned on and the read bit line RB connected to it
However, even though it must be held at the “H” level, it is discharged to the “L” level. If this occurs before the read by the read pointer 54, the read data is destroyed.

When such a memory cell array is used as a line memory and 1H delay (where 1H is the horizontal scanning period of the video signal) is performed, the write and read addresses are set to (0) at the timing of the horizontal synchronizing signal of the video signal. It is the easiest and most common to reset to the address and perform delay control. To execute this, the write word line WW and the read word line RW of the same memory cell 39 are simultaneously set to the "H" level. Although it is necessary, if the above occurs, the data can no longer be read.

Therefore, in the above-mentioned conventional example, the write word line WW is set to the "H" level, so that the memory cell 3
The stored data of No. 9 appears on the write bit line WB, a slight potential change of the write bit line WB is detected, amplified by the sense amplifier and written to the memory cell 39, thereby writing the data. The data was rewritten in the memory cell 39 to prevent the read data from being destroyed.

However, in such a conventional technique, it is necessary to provide one sense amplifier for each bit line, which causes a problem that the chip area becomes large.

An object of the present invention is to solve the above problems, to provide a serial access memory capable of simultaneously accessing a write word line and a read word line and reducing a chip area. .

[0018]

In order to achieve the above object, the present invention has memory cells arranged in m rows and n columns, and a write bit line and a read bit line are provided for each row of the memory cell arrangement. Has a memory cell array provided with a write word line and a read word line for each column, and the write word line is sequentially set to 1
Each time the write bit lines are selected one by one, m write bit lines are sequentially selected one by one, and the memory cell at a position determined by the selected write bit line and the write word line in the memory cell array. Every time data is written to the read word line, and one of the read word lines is selected one by one, m read bit lines are sequentially selected one by one, and the selected read bit line of the memory cell array is In a serial access memory in which data is read from the memory cell at a position determined by the read word line, M for discharging is provided for each write bit line.
An OSFET is provided so that the discharge MOSFETs are all driven at the same time immediately before the write word line is selected.

[0019]

When writing data in each column, first, the write word line in that column is selected, and then, m write bit lines are sequentially selected one by one, and the memory cells in that column are sequentially selected. Data is written into the memory cell, but immediately before the write word line is selected, all the discharge MOSFETs are turned on and all the write bit lines are discharged. Therefore, when the write word line is next selected and the data is written to the memory cell, the write bit line connected to the memory cell to which the data is written is discharged to the "L" level. Therefore, the potential of the write bit line does not affect the memory cell. As a result, even if the write word line connected to the memory cell in which data is being read is selected for data writing, it is not affected by the potential of the write bit line,
The data in this memory cell is retained as it is and does not hinder the read operation.

Therefore, even if the write word line and the read word line in the same column are selected at the same time, the read data is not destroyed, and each write bit line has a discharging MOSFET.
By providing only one each, a sense amplifier as in the prior art is not required, simultaneous write / read access is possible with a small number of elements, and the chip area can be reduced.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing an embodiment of a serial access memory according to the present invention, in which 1 is a memory cell array, 2 is a write decoder, 3 is a read decoder, 4 is a write system control circuit, and 5 is a read circuit. -A control circuit, 6 is a sense amplifier for data amplification, 7a and 7b are D-type flip-flops (hereinafter referred to as D-FFs), 8 is an output terminal of a write address signal WADS, and 9 is a read address. Signal RADS
, An output terminal of the write bit line selection switch control signal WBS1 of the first bit, an output terminal of the write bit line selection switch control signal WBS2 of the second bit, and a write operation of the mth bit An output terminal of the bit line selection switch control signal WBSm, 13 is an output terminal of the first bit read bit line selection switch control signal RBS1, and 14 is a second bit read bit line selection switch control signal RBS.
2, an output terminal of the m-th bit read bit line selection switch control signal RBSm, 16 a write terminal of the memory cell array 1, 17 a read terminal of the memory cell array 1, and 18 a write bit line discharge control An output terminal of the signal WCR, 19 is an input terminal of the write control clock WCLK, and 20
Is a write reset signal WRES input terminal, 21 is a write clock gate signal WCG input terminal, 22 is a read control clock RCLK input terminal, and 23 is a read reset signal R
RES input terminal, 24 is a read clock gate signal RC
G is an input terminal, 25 is a write control clock WCLK output terminal, 26 is a read bit line charge control signal PC output terminal, 27 is data DATA input terminal, and 28 is data D.
This is the output terminal of ATA '.

In the drawing, at the time of writing, data DATA to be written is input from the input terminal 27. Also,
The write control clock WCLK is input from the input terminal 19, the write reset signal WRES is input from the input terminal 20, and the write clock gate signal WCG is input from the input terminal 21. Here, the bit cycle of the data DATA is equal to the cycle of the write control clock WCLK, and the write system control circuit 4 receives the write control clock WCLK by receiving the write clock gate signal WCG. It also outputs to the output terminal 25.

The data DATA is supplied to the D-FF 7a and the write control clock WC supplied from the output terminal 25.
It is captured at the falling edge of LK. Therefore, this D-
Data synchronized with the falling edge of the write control clock WCLK is obtained from the FF 7a. The output data of the D-FF 7a is supplied to the D-FF 7b and fetched at the falling edge of the same write control clock WCLK. Therefore,
From the D-FF 7b, data DATA 'synchronized with the falling edge of the write control clock WCLK and delayed by one cycle of the write control clock WCLK from the output data of the D-FF 7a is obtained. 16 is supplied to the memory cell array 1. That is, the D-FF 7b delays the data by one cycle of the write control clock WCLK.

Here, it is assumed that the memory cell array 1 comprises 3MOS type memory cells (39) arranged in m rows and n columns as shown in FIG. 5, for example. In this case, the write reset signal WRES is the write control clock WCL.
The signal is "L" having a cycle of (m × n) times the cycle of K and having a pulse width of one cycle of the write control clock WCLK.

On the other hand, write system control circuit 4 is reset each time write reset signal WRES is supplied, and write bit line selection switch control signals WBS1 to WBSm and write bit are generated by write control clock WCLK. Line discharge control signal WCR and write address signal WADS
Is generated. These write bit line selection switch control signals WBS1 to WBSm and write bit line discharge control signal WC
R is supplied from the output terminals 10, 11, 12, and 18 to the memory cell array 1, and the write address signal WADS
Is supplied from the output terminal 8 to the write decoder 2.

WBS1 is the first bit write bit line selection switch control signal WBS, and WBS2 is the second bit write bit line selection switch control signal WBS, WBSm.
Is the write bit line selection switch control signal WB for the m-th bit
It is S. Under the control of the write bit line discharge control signal WCR, the write bit line selection switch control signal WBS and the write decoder 2, the data DAT is stored in the memory cell array 1.
A'is written.

The write bit line discharge control signal WCR is generated when the write reset signal WRES is supplied and each time m subsequent write control clocks WCLK are input, and the write reset signal WRES. Every time the write control clock WCLK is input, the write bit line selection switch control signals WBS1, WBS1, ..., WBSm are input.
Are generated sequentially and repeatedly. In addition, the write address signal WADS is generated immediately after the write bit line discharge control signal WCR is generated and the write bit line selection switch control signal WBS is 1 every time the write control clock WCLK is input m times.
Write bit bit selection switch control signal WBS1
It occurs just before.

Write system control circuit 4 for generating such a signal
A specific example will be described with reference to FIGS. 2 and 3. However, FIG.
Is a block diagram showing this specific example, and includes 7c, 7d,
7e is a D-FF, 29 and 30 are buffers, 31 is a write system reset edge detection circuit, 32 is a NAND circuit, 33
Is a write row address counter, 34 is a write address generation circuit (write column address counter), 35 is a write timing generation circuit, 36 is an inverter, and 37 is an AND circuit. I am wearing it. Further, in FIG. 3, a signal of each part of FIG. 2 is shown in a part thereof.

2 and 3, the write clock gate signal WCG input from the input terminal 21 is "L" when a write operation is performed in the memory cell array 1, and "H" otherwise. The buffer 30 passes the write control clock WCLK from the input terminal 19 only when the write clock gate signal WCG is “L” (that is, during the write operation of the memory cell array 1). The write control clock WCLK that has passed through the buffer 30 is supplied to the write system reset edge detection circuit 31, the write row address counter 33, and the write timing generation circuit 35, and is also output from the output terminal 25 as shown in FIG. D
-Supplied to the FFs 7a and 7b. Further, the “L” write reset signal WRES is input from the input terminal 20 and supplied to the write reset edge detection circuit 31 via the buffer 29.

In the write system reset edge detection circuit 31, the D-FF 7c captures the write reset signal WRES at each falling edge of the write control clock WCLK, so that the falling edge of the write control clock WCLK (time t1). And 1 of this write control clock WCLK
A "L" pulse for a period is obtained. This pulse is D-
The write control clock WCLK is latched in the FF 7d at the falling edge of the write control clock WCLK, synchronized with the falling edge (time t2) next to the falling edge of the write control clock WCLK at time t1, and 1 "L" for the cycle
Pulse and the inverted “H” pulse are obtained. Further, this "L" pulse is latched in the D-FF 7e at the falling edge of the write control clock WCLK, synchronized with the falling edge next to the falling edge of the write control clock WCLK at time t2, and Write control clock W
An "L" pulse for one cycle of CLK is obtained. Then, the "H" pulse from the D-FF 7d and the D-FF 7e
Is supplied to the NAND circuit 32, and the "L" pulse for one cycle of the write control clock WCLK is obtained in synchronization with the falling edge of the write control clock WCLK at time t2. To be This pulse is output as the reset pulse WEO from the write system reset edge detection circuit 31. The reset pulse WEO resets the write row address counter 33 and the write address generation circuit 34 to the value 0.

The D-FF 7c is for forming a pulse having a width of one cycle of the write control clock WCLK in synchronization with the falling edge of the write control clock WCLK from the "L" write reset signal WRES. And D-FF
7d outputs the output pulse of the D-FF 7c to the write control clock W
This is for delaying one cycle of CLK. Also, D
The "L" pulse output from -FF7d is D-FF7.
It is further delayed by one cycle of the write control clock WCLK by e, and is used as a gate signal of the NAND circuit 32 to which the "H" pulse output from the D-FF 7d is supplied. Write control clock WCL by D-FF7d
Delaying by one cycle of K, as will become clear later,
When this embodiment is operated as the 1H delay means, the write position in the memory cell array 1 is 3 MOS more than the read position.
This is because it is delayed by one mold cell.

From the above, the addresses in the row direction of the memory cell array 1 are up to the address m. The write row address counter 33 is a write system reset edge detection circuit 3
The reset pulse WEO is reset from 1, and the write control clock WCLK from the buffer 30 is counted, and the carry COW of "H" is output one by one every time the write control clock WCLK is counted m times. The write address generation circuit 34 is reset by the reset pulse WEO from the write system reset edge detection circuit 31, counts the carry COW, and sequentially generates the write column address of 7 bits, and the output terminal 8 outputs the write decoder of FIG. Supply to 2.

The carry COW output from the write row address counter 33 is inverted by the inverter 36 to become "L" and then supplied to the AND circuit 37.
The AND circuit 37 allows the reset pulse WEO of "L" and the carry COW of "L" to pass therethrough and supplies it to the write timing generation circuit 35.

The write timing generation circuit 35 has an AND
The write bit line discharge control signal WCR is generated each time the output signal of "L" is supplied from the circuit 37. When the write bit line discharge control signal WCR is generated, the rising edge of the write control clock WCLK is generated. The write bit line selection switch control signal WBS for the 1st bit, the write bit line selection switch control signal WBS for the 2nd bit, ..., The write bit line selection switch control signal WBSm for the mth bit are written in this order. It is generated in synchronization with the rising edge of the control clock WCLK. That is, in FIG. 3, the write control clock WCL
When the write bit line discharge control signal WCR is generated at time t3 after time t2 when K falls, the write bit line selection switch control signal for the first bit at the first rising edge time t5 of the write control clock WCLK thereafter. WBS1 is generated, the write bit line selection switch control signal WBS2 of the first bit is generated at the next rising edge time t6 of the write control clock WCLK, ..., And the mth rising edge time of the write control clock WCLK. At t (4 + m), the write bit line selection switch control signal WBSm of the m-th bit is generated. Then, the output signal of the AND circuit 37 is supplied again to generate the write bit line discharge control signal WCR, and the above operation is repeated.

The memory cell array 1 of FIG. 1 performs a write operation using the above signals.
A specific example of the memory cell array 1 will be described with reference to FIGS. 4 and 3. However, in FIG.
(1), 40 (2), ..., 40 (10) are M for discharging
OSFET, 41 (1), 41 (2), ..., 41 (1
0) is a writing MOSFET, 42 (1), 42
(2), ..., 42 (10) is a MOSFET for reading
Therefore, the parts corresponding to those in FIG. 13, FIG. 1 and FIG. Here, for convenience of description, it is assumed that the memory cell array 1 is composed of 10 rows and 100 columns of 3MOS type memory cells (that is, m = 10, n = 100).

4 and 3, when the write reset signal WRES is input to the write system control circuit 4 (FIG. 1), the write bit line discharge control signal WCR is output to the output terminal 18 as described above. Is output (time t3)
And discharging MOSFETs 40 (1), 40 (2), ...
..., 40 (10) is turned on, and the write bit lines WB1, WB
2, ..., WB10 are MOSFETs 40 (1), 4 respectively
0 (2), ..., 40 (10) is discharged through "L"
Becomes

Next, as described above, when the write reset signal WRES is input to the write system control circuit 4 (FIG. 1), the first write address signal WADS is output to the output terminal 8. Then, the write decoder 2 (FIG. 1) sets the write word line WW1 to "H" (time t4),
First-row 3MOS type memory cells 39 (1,1), 39
(1,2), ..., 39 (1,10) n-type MOSFE
Turn on T (M1). This makes 3 in the first row
MOS type memory cells 39 (1,1), 39 (1,2), ...
..., 39 (1, 10) are in a writable state.

In this state, the write control circuit 4
From the rising edge of the write control clock WCLK (time t
In synchronism with 5), the write bit line selection switch control signal WBS1 of the first bit is output to the output terminal 10, thereby turning on the MOSFET 41 (1) and writing bit line W.
Only B1 is connected to the write terminal 16. At this time, one bit of the data DATA 'described in FIG. 1 is supplied to the write terminal 16, and the MOSFET 41 (1) and the 3MOS are connected.
This bit is stored in the MOSFET (M2) of the 3MOS type memory cell 39 (1,1) by turning on the MOSFET (M1) of the type memory cell 39 (1,1).

Next, while the write word line WW1 remains in the "H" state, the write control clock W is sent from the write control circuit 4 to the write control clock W.
The second bit write bit line selection switch control signal WBS2 is output to the output terminal 11 in synchronization with the next rising edge of CLK (time t6). This allows the MOSFET
41 (2) is turned on, and only the write bit line WB2 is connected to the write terminal 16. At this time, the write bit 16 is supplied with the next 1 bit of the data DATA ′,
FET 41 (2) and 3MOS type memory cell 39 (1,
Since the MOSFET (M1) of 2) is turned on, this bit causes the 3MOS type memory cell 39 (1, 2)
Stored in the MOSFET (M2).

Similarly, the write bit line select switch control signal is synchronized with the successive rising edges of the write control clock WCLK from the write control circuit 4 while the write word line WW1 remains in the "H" state. WBS output, 3M
Data DAT up to OS type memory cell 39 (1, 10)
A'is stored bit by bit.

When the storage in the 3MOS type memory cell 39 (1, 10) is completed, the write system control circuit 4 outputs the next write bit line discharge control signal WCR (time t46), and the discharge MOSFET 40 (1 ), 40 (2), ...,
40 (10) is turned on and the write bit lines WB1, WB
2, ..., WB10 becomes "L". Then, the write system control circuit 4 outputs the next write address signal W to the output terminal 8.
ADS is output, and the write decoder 2 (FIG. 1) sets the next write word line WW2 to "H", and the 3rd MOS type memory cells 39 (2,1), 39 (2,2), ... In the second column. , 39
The (2, 10) n-type MOSFET (M1) is turned on. As a result, the 3MOS type memory cell 3 in the second column is
9 (2,1), 39 (2,2), ..., 39 (2,10)
Becomes a writable state.

Hereinafter, the 3rd MOS type memory cell 39 in the first column
The same operation as in the case of (1, 1), 39 (1, 2), ..., 39 (1, 10) is performed, and the write bit line selection switch control signal WBS of the 1st bit and the 1st bit of the WBS The write bit line selection switch control signal WBS2, ..., The 10th bit write bit line selection switch control signal WBS10 is sequentially supplied from the output terminals 10, 11 ,. Type memory cell 39 (2,
1), 39 (2, 2), ..., 39 (2, 10) sequentially store data DATA ′ bit by bit. Then, thereafter, the write word lines WW3, ..., WW100 sequentially become “H”, and the above operation is performed respectively to the 3rd MOS type memory cells 39 (100, 1), 39 in the 100th column.
(100, 2), ..., 39 (100, 10) data DATA 'is stored bit by bit, and when this is finished, the write reset signal WRES is supplied to the write system control circuit 4 and the 3rd MOS of the first column is supplied. Memory cells 39 (1,1), 3
The above writing operation is repeated again from 9 (1, 2), ..., 39 (1, 10).

1 and 3, the input terminal 2
The data DATA input from 7 is the write control clock W
Although it is synchronized with CLK, it is synchronized with the falling edge by the D-FF 7a, and further D-FF 7b.
Is delayed by one cycle of the write control clock WCLK,
As a result, the data D supplied to the memory cell array 1
The timing of ATA 'is matched with the write timing delayed by one cycle of the write control clock WCLK in the D-FF 7d of FIG. This means that the delay time can be accurately adjusted to 1H when operating as 1H delay means described later.
Is important to

The above is the write operation. Next, the read operation will be described. 1, at the time of reading, the read control clock RCLK is input from the input terminal 22, the read reset signal RRES is input from the input terminal 23, and the input terminal 24 is input.
Read clock gate signal RCG is input from each. Here, the cycle of the read control clock RCLK is equal to the cycle of the write control clock WCLK.

In the read system control circuit 5, the read clock gate signal RCG is input to take in the read control clock RCLK and the read reset signal R.
Each time RES is supplied, reset is performed, and read bit line selection switch control signals RBS1 to RBSm and read bit line charge control signal P are generated by the read control clock RCLK.
C and the write address signal RADS are generated. These read bit line selection switch control signals RBS1 to RBS
m and the read bit line charge control signal PC are output terminals 1 respectively
3, 14, 15, and 26 are supplied to the memory cell array 1, and the write address signal RADS is supplied from the output terminal 9 to the read decoder 3.

Note that RBS1 is the first bit read bit line selection switch control signal RBS, RBS2 is the second bit read bit line selection switch control signal RBS, RBSm.
Is the read bit line selection switch control signal RB for the m-th bit
It is S. By the read bit line charge control signal PC, the read bit line selection switch control signal RBS and the control of the read decoder 3, the data stored in the memory cell array 1 is read. The read data is output as data DATA ″ via the sense amplifier 6.

The read bit line charge control signal PC is generated when the read reset signal RRES is supplied and every time the subsequent read control clocks RCLK are input, and after the read reset signal RRES is input. Each time the read control clock RCLK is input, read bit line selection switch control signals RBS1, RBS1, ..., RBSm
Are generated sequentially and repeatedly. Further, the write address signal RADS selects the first read bit line of the read bit line selection switch control signal RBS immediately after the read bit line charge control signal PC is generated every time m read control clocks RCLK are input. It is generated immediately before the switch control signal RBS1.

A specific example of the read system control circuit 5 for generating these signals will be described with reference to FIGS. However,
In FIG. 5, 7f and 7g are D-FFs, 44 and 45 are buffers, 46 is a read system reset edge detection circuit, and 47
Is a NAND circuit, 48 is a read row address counter, 4
Reference numeral 9 is a read address generation circuit (read column address counter), 50 is a read timing generation circuit, 51 is an inverter, and 52 is an AND circuit. There is. Further, in FIG. 6, a part of the signal of each part of FIG. 5 is shown.

5 and 6, the read clock gate signal RCG input from the input terminal 24 is "L" when the read operation is performed in the memory cell array 1.
Otherwise, it is at "H", and the buffer 45 receives the input terminal 24 only when the read clock gate signal RCG is at "L" (that is, during the read operation of the memory cell array 1).
To pass the read control clock RCLK. The read control clock RCLK that has passed through the buffer 45 is supplied to the write system reset edge detection circuit 46, the read row address counter 48, and the read timing generation circuit 50. Further, the above-mentioned “L” read reset signal RRES is input from the input terminal 23, and is supplied to the read system reset edge detection circuit 46 via the buffer 44.

In the read system reset edge detection circuit 46, the D-FF 7f captures the read reset signal RRES at each falling edge of the read control clock RCLK, thereby synchronizing with the falling edge (time t7) of the read control clock RCLK. And 1 of this read control clock RCLK
A "L" pulse corresponding to a cycle and an "H" pulse obtained by inverting the pulse are obtained. Furthermore, this "L" pulse is D-
It is latched in the FF 7g at the falling edge of the read control clock RCLK, is synchronized with the next falling edge of the read control clock RCLK at the time t7, and is "L" for one cycle of the read control clock RCLK. A pulse is obtained. "H" pulse from D-FF 7d and D-FF
The "L" pulse from 7g is supplied to the NAND circuit 47, synchronized with the falling edge of the read control clock RCLK at the time t7, and read by the read control clock RCLK.
The pulse of "L" for one cycle is obtained. This pulse is output from the read system reset edge detection circuit 46 as a reset pulse REO. This reset pulse REO
As a result, the read row address counter 48 and the read address generating circuit 49 are reset to the address (0).

The D-FF 7f is the D-FF 7 in FIG.
D-FF 7g corresponds to D-FF 7e in FIG. Therefore, as described above, the reset pulse R
The timing of EO coincides with the time t7.

From the above, the addresses in the row direction of the memory cell array 1 are up to the address m. The read row address counter 48 is a read system reset edge detection circuit 4.
6 is reset by the reset pulse REO, the read control clock RCLK from the buffer 45 is counted, and a carry COR of "H" is output one by one every time the read control clock RCLK is counted m times. The read address generation circuit 49 is reset by the reset pulse REO from the read system reset edge detection circuit 46, then counts the carry COR to sequentially generate the write column address signal RADS of 7 bits, and the output terminal 9 of FIG. It is supplied to the read decoder 3.

The carry COR output from the read row address counter 48 is inverted by the inverter 51 to become "L" and then supplied to the AND circuit 52.
The AND circuit 52 passes the reset pulse REO of "L" and the carry COR of "L" and supplies the read pulse to the read timing generation circuit 50.

The read timing generation circuit 50 performs AND
The read bit line charge control signal PC is generated each time the output signal of "L" is supplied from the circuit 52, and the read bit line selection of the first bit is selected each time the read bit line charge control signal PC is generated. Switch control signal RBS 1st and 2nd bit read bit line selection switch control signal RBS, ..., M
Read bit bit selection switch control signal RBSm
Occurs in synchronization with the rising edge of the read control clock RCLK.

That is, in FIG. 6, the read control clock R
When the read bit line charge control signal PC is generated at time t8 after time t7 when CLK falls, 1 at time t10 of the first rising edge of the read control clock RCLK thereafter.
Read bit bit selection switch control signal RBS1 of the bit
Occurs, the read bit line select switch control signal RBS2 of the second bit is generated at time t11 of the next rising edge of the read control clock RCLK, ..., And the time t (of the mth rising edge of the read control clock RCLK. 9 + m) read bit line selection switch control signal RBS for the m-th bit
m occurs. Then, the output signal of the AND circuit 52 is supplied again to generate the read bit line charge control signal PC (time t47), and the above operation is repeated.

The memory cell array 1 of FIG. 1 performs a read operation using the signals as described above.
6 and FIG. 6, the read operation of the memory cell array 1 composed of 3 rows and 100 columns of 3MOS type memory cells will be described.

4 and 6, as described above, the read reset signal RRES is sent to the read system control circuit 5 (FIG. 1).
When the read bit line charge control signal PC is output to the output terminal 26 by inputting (at time t8), charging MOSFETs 38 (1), 38 (2), ..., 38 (1
0) is turned on and the read bit lines RB1, RB2, ..., R
B10 is connected to the power supply 43 and becomes "H".

Next, the read system control circuit 5 (FIG. 1) receives the read reset signal RRES and then outputs the first read address signal RADS to the output terminal 9 as described above.
Then, the read decoder 3 (FIG. 1) sets the read word line RW1 to "H" (time t9), and the 3rd MOS of the first column.
Type memory cell 39 (1,1), (1,2), ..., 39
The (1, 10) n-type MOSFET (M3) is turned on. As a result, these 3MOS type memory cells 39
(1,1), (1,2), ..., 39 (1,10) are ready for reading.

In this state, the read system control circuit 5
From the rising edge of the read control clock RCLK (time t
10), the first bit read bit line selection switch control signal RBS1 is output to the output terminal 13, whereby the MOSFET 42 (1) is turned on and the read bit line R is read.
Only B1 is connected to the read terminal 17. And 3MOS
Of the 3MOS type memory cell 39 by turning on the MOSFET (M3) of the type memory cell 39 (1, 1)
The bit stored in the MOSFET (M2) of (1,1) is the MOSF of the 3MOS type memory cell 39 (1,1).
ET (M3), read bit line RB1, MOSFET 42
It is read to the output terminal 17 via (1).

Next, while the read word line RW1 remains in the "H" state, the read system control circuit 5 reads the read control clock RC.
The second bit read bit line selection switch control signal RBS2 is output to the output terminal 14 in synchronization with the next rising edge of LK (time t11), whereby the MOSFET 4
2 (2) is turned on to connect only the read bit line RB2 to the read terminal 17. Then, the 3MOS type memory cell 39
Since the MOSFET (M3) of (1, 2) is turned on, this bit causes the 3MOS type memory cell 39 (1 ,,
The bit stored in the MOSFET (M2) of 2) is the MOSFET of the 3MOS type memory cell 39 (1, 2)
(M3), read bit line RB2, MOSFET 42
It is read to the output terminal 17 via (2).

Similarly, the read bit line selection switch control signal RBS is output from the read system control circuit 5 in synchronization with the successive rising edges of the read control clock RCLK while the read word line RW1 is in the "H" state. And 3M
Bits up to the OS type memory cell 39 (1, 10) are sequentially read.

When the bit read in the 3MOS type memory cell 39 (1, 10) is completed, the read system control circuit 5 outputs the next read bit line charge control signal PC (time t4.
7), MOSFETs 38 (1), 38 (2), ...
.., 38 (10) is turned on, and read bit lines RB1, R
B2, ..., RB10 becomes “H”. Then, the next read address signal RADS is output from the read system control circuit 5 to the output terminal 9, and the read decoder 3 (FIG. 1) sets the next read word line RW2 to "H" and the 3rd MOS type memory cell in the second column. 39 (2,1), 39 (2,2), ..., 39
The (2, 10) n-type MOSFET (M3) is turned on. As a result, the 3MOS type memory cell 3 in the second column is
9 (2,1), 39 (2,2), ..., 39 (2,10)
Is ready for reading.

Hereinafter, the 3rd MOS type memory cell 39 in the first column
The same operation as in the case of (1, 1), (1, 2), ..., 39 (1, 10) is performed, and the read bit line selection switch control signal RBS of the first bit and the read bit of the second bit The line selection switch control signal RBS2, ..., The 10th bit read bit line selection switch control signal RBS10 is sequentially supplied from the output terminals 13, 14 ,. (2,1),
One bit is sequentially read from 39 (2,2), ..., 39 (2,10). Then, the read word line R
W3, ..., RW100 sequentially become “H”, and the above operation is performed respectively, and the 3rd MOS type memory cells 39 (100,1), 39 (100,2) ,.
Bit read is performed up to 9 (100, 10), and when this is completed, the read system control circuit 5 is again read with the read reset signal R.
RES is supplied, and the 3rd MOS type memory cell 39 in the first column
The above reading operation is repeated again from (1, 1), 39 (1, 2), ..., 39 (1, 10).

The data write / read operation of this embodiment has been described above. Next, regarding the operation of this embodiment when it is used as the 1H delay means, the timing relationship between the above-mentioned drawings and the signal timings of these parts will be described. This will be described with reference to FIG.

Here, as shown in FIG. 7, the write control clock WCLK and the read control clock RCLK have the same frequency and the same phase, and the write reset signal WRES and the read reset signal RRES also have the same cycle and the same phase. Suppose there is. Specifically, the frequency of the write control clock WCLK and the read control clock RCLK is 4 fsc, and the cycle of the write reset signal WRES and the read reset signal RRES is 1.
H (one horizontal scanning period of video signal). However, 1H
Is one horizontal scanning period of the video signal, fsc is also the color carrier frequency, and in the case of the NTSC system video signal, fsc =
3.58 MHz, 1H is write control clock WC
This corresponds to 910 cycles of LK and read control clock RCLK.

First, the write system reset edge detection circuit 3
1 (FIG. 2) and the read system reset edge detection circuit 46 (FIG. 5), "L" at the falling edge of the write control clock WCLK or the read control clock RCLK at time t12.
The level write reset signal WRES and the read reset signal RRES are respectively detected, and at time t21, which is the same timing as this time t12, the read system reset edge detection circuit 46.
From the write control clock WCLK, the reset signal WEO is output from the write system reset edge detection circuit 31 at time t13. The timing relationship between the reset signals WEO and REO is, as described above, the D-FF 7d of FIG.
Is set by.

The read row address counter 48 and the read address generating circuit 49 are reset by the reset signal REO, and the read address signal RADS output from the read address generating circuit 49 is set to the address (0). To do.
Next, at time t15, the read timing generation circuit 50 outputs the read bit line charge control signal PC. By this operation, the read bit lines RB1, RB, ... In FIG.
, RB10 is charged to the "H" level, and after this charging (time t14), read word line RW1 is set to the "H" level by read address signal RADS at address (0). The operation up to time t14 described above is performed within 1/2 cycle of the write control clock WCLK or the read control clock RCLK after the reset signal REO is generated.

After the read word line RW1 goes to "H" level, the read bit line selection switch control signal RBS1, from the read timing generation circuit 50 is generated at every rising edge of the read control clock RCLK (time t22, t16, ...).
RBS2, ..., RBSm are output in this order, and the 3rd in the first column
MOS type cell 39 (1,1), (1,2), ..., 39
Data is read in the order of (1, 10).

Further, from time t21, the write control clock W
The write-system reset edge detection circuit 31 outputs the reset signal WEO at time t13 which is delayed by one cycle of CLK or the read control clock RCLK, whereby the write row address counter 33 and the write address generation circuit 34 are reset, and the write address is written. The write address signal WADS output from the address generation circuit 34 is set to the address (0).
Next, at time t17, the write timing generation circuit 35 outputs the write bit line discharge control signal WCR. By this operation, the write bit lines WB1, WB2, ... Of FIG.
.., WB10 is discharged to the "L" level, and after this discharge (time t18), the write word line WW1 is set to the "H" level by the write address signal WADS at the address (0). The operation up to time t14 described above is performed within 1/2 cycle of the write control clock WCLK or the read control clock RCLK after the reset signal REO is generated.

Then, after the write word line WW1 becomes the "H" level, the write bit line selection is made from the write timing generation circuit 35 at each rising edge of the write control clock WCLK (time t19, t20, ...). Switch control signal W
BS1, WBS2, ..., WBSm are output in this order, and 1
3MOS type cell 39 (1,1), (1,2), ...
The data is written in the order of 39 (1, 10).

By this operation, the 3MOS type cell 39
When data is read at (1, 2), 3 MO
Just as data writing is performed in S-type cell 39 (1, 1), data reading is performed in 3MOS type cell 35 which is one before the 3MOS type cell 35 in which data reading is performed.

As described above, the read bit line charge control signal PC is generated every time the carry address COR is output from the read address counter 48, and the above operation is repeated to sequentially read the data in each column. The write bit line discharge control signal WCR is generated every time carry COW is output from the write row address counter 33, and the write bit line discharge control signal WCR is generated. Data is written in columns.

Thus, as shown in FIG. 7, the data DATA 'is (0), (1),
When written in the order of (2), (3), ..., These are read from time t50, which is delayed by 1H, and output to the output terminal 17 as data DATA ″.

In the above operation, the 3MOS type cells 3 in each column are
At the time of data writing to 9, the write word line WW is set to the “H” level and the MOSs of all the 3MOS type cells 39 in the same column are set.
Before turning on the FET (M1), all the write bit lines WB are discharged to the "L" level, so that the write word line WW
Even if these MOSFETs (M1) are turned on by setting "H" to "H" level, the data of "L" is held at this time 3
The MOSFET (M2) of the MOS cell 39 does not turn on,
The data held in this MOSFET (M2) remains "L" and is not affected.

Therefore, even if the write word line WW simultaneously becomes "H" level in the column where the read word line RW is at "H" level, the read data is not destroyed. For this reason, the sense amplifier for each write bit line as in the prior art described above is not necessary, and instead, the M for discharging, which is simple in configuration and each is a single element, is used.
Since only the OSFET is added to each write bit line, write / read can be simultaneously accessed in the same column of the memory cell array with a smaller number of elements as compared with the case where a sense amplifier is used, and the chip area is small. can do.

As is clear from the above operation, the positional deviation between the write timing and the read timing is 3MOS.
Since it can be set to one type cell, the delay time of this 1H delay means is exactly one cycle of the write control clock WCLK shorter than the time of 1H, but this cycle is 1H. Since the time is sufficiently shorter than the time and can be ignored, the data delayed by 1H can be obtained with high accuracy by using the necessary minimum number of 3MOS type cells.

In the above, the write reset signal WRES and the read reset signal RRES have the same timing in the cycle of 1H in order to use this embodiment as the 1H delay means. However, this embodiment can perform only such operation. There is not. Next, operations other than the above will be described. First,
Write control clock WCLK and read control clock RCLK
The operation when the write reset signal WRES and the read reset signal RRES have the same frequency and phase but the same cycle but different phases will be described with reference to FIG.

In this case, as shown in FIG. 8, the write system reset edge detection circuit 31 outputs the write control clock WCLK.
The write reset signal WRES of "L" is detected at the falling edge at the time t23 of the write control clock WC
Reset pulse WE is delayed by one cycle of LK at time t25.
It is assumed that O is generated, and time T is longer than time t23.
It is assumed that the read system reset edge detection circuit 46 detects the read reset signal RRES of "L" at the falling edge of the read control clock RCLK at time t24 delayed by d, and the reset pulse REO is generated at this time t24.

When the reset signal WEO is generated, the write row address counter 33 and the write address generation circuit 34 are reset, and the write address signal WADS output from the write address generation circuit 34 is set to the address (0). Then, at time t30, write bit line discharge control signal WCR is output from write timing generation circuit 35. By such an operation, the write bit line WB1, in FIG.
.., WB10 are discharged to the "L" level, and after this discharge (time t31), the write address signal WADS at the address (0) sets the write word line WW1 to the "H" level. . The operation up to time t31 is performed within 1/2 cycle of the write control clock WCLK after the reset signal WEO is generated. Then, after the write word line WW1 becomes the “H” level, every rising edge of the write control clock WCLK (time t32, t3).
3, ...) From the write timing generation circuit 35 to the write bit line selection switch control signals WBS1, WBS2 ,.
, WBSm are output in this order, and the data DATA ′ (0), (1), 3 (1), (1, 2), ... (2), ……
Is written.

As described above, the write bit line discharge control signal WCR is generated every time the carry row address counter 33 outputs the carry COW, and the above operation is repeated to sequentially perform the operation in each column. Data writing is performed.

A read row address counter 48 and a read address generation circuit 49 are generated together with the generation of the reset signal REO at time t24 which is delayed by time Td from time t23.
Are reset, and the read address signal RADS output from the read address generation circuit 49 is set to the address (0). Next, at time t26, the read timing generation circuit 5
The read bit line charge control signal PC is output from 0. By this operation, the read bit lines RB1 and RB in FIG.
2, ..., RB10 are charged to the "H" level, and after this charging (time t27), read word line RW1 is set to the "H" level by read address signal RADS at address (0). The operation up to time t27 is performed within 1/2 cycle of read control clock RCLK after generation of reset signal REO. Then, after the read word line RW1 goes to the “H” level, every rising edge of the read control clock RCLK (time t28, t2).
, ...) from the read timing generation circuit 50 to the read bit line selection switch control signals RBS1, RBS2 ,.
,, RBSm are output in this order, and the 3rd MOS cells 39 (1,1), 39 (1,2), ..., 39 (1,1) in the first column are output.
Data DATA ′ written in the order of 0) is data DA
It is read as TA "(0), (1), (2), ....

As described above, the read bit line charge control signal PC is generated every time the carry address COR is output from the read address counter 48, and the above operation is repeated to sequentially read the data in each column. Is performed.

In this way, the data written in each column is after time Td (more accurately, after (Td-Tc), where TC is one cycle of the read control clock WCLK).
Once read, the data will be delayed by the time Td. Here, since the phase between the write reset signal WRES and the read reset RRES can be arbitrarily set, the delay time Td can be arbitrarily set. If the delay time Td is 1H>Td> (1H-m * Tc), data writing will start in the column in which data is being read. Even in this case, the operation as the 1H delay means is performed. The data that is read is not destroyed in the same way as is done.

By the way, when the above embodiment is operated as the 1H delay means as described with reference to FIG. 7, the same 3MOS is used even though the write reset signal WRES and the read reset signal RRES have the same timing. The write timing of the mold cell is delayed from the read timing by one cycle of the write control clock WCLK. This is because the read bit line RB is sufficiently charged.
By shortening this charging time, the delay of the write timing from the read timing in the same 3MOS type cell can be made shorter than one cycle of the write control clock WCLK. An embodiment for performing the operation in this case is described below with reference to FIG.
~ It demonstrates by FIG.

In FIG. 9, also in this embodiment, as in the case of the operation described in FIG. 7, the write control clock WCLK is generated.
And read control clock RCLK, write reset signal WRE
S and the read reset signal RRES have the same timing. Write control clock WCLK and read control clock R
"L" level write reset signal WRES and read reset signal RRES at the falling edge of CLK at time t36.
Pulse is detected and the reset signals WEO and REO are output from the write system reset edge detection circuit 31 and the read system reset edge detection circuit 46, respectively, at t37 at the same time, and the write address generation circuit 34 and the read address generation circuit are output. The write address signal WADS and the read address signal RADS at the address (0) are output from 49, respectively.

Then, the read timing generation circuit 50 generates the read bit line charge control signal PC at the same time as the supply of the reset signal REO at the time t37 (time t3.
8) The read bit line RB is charged to "H" level.
After this charging is completed, at time t39, the read word line RW1 is set to the “H” level by the read address signal RADS at the address (0). As a result, the first-row 3MOS type cells 39 (1,1), 39 (1,2), ..., 39 (1 ,,
Data is read at 10), but at this time t39.
When the read word line RW1 becomes "H" level at
At 40, write timing generation circuit 35 generates write bit line discharge control signal WCR based on reset signal WEO supplied at time t37, and discharges write bit line WB to "L" level. Then, the time t41 when this discharge ends
Then, by the write address signal WADS at the address (0),
The write word line WW1 is set to "H" level. As a result, the 3rd MOS cells 39 (1,1), 39 (1,
Data is written at 2), ..., 39 (1, 10). Thereafter, reading and writing of such data is performed for each column.

In this operation, from the time t36, the next write control clock WCLK and read control clock RCLK
The read bit line RB is charged in the first half of these 1/2 cycles until the rising edge of
Are respectively discharged, which causes the next write control clock WCLK and read control clock RCL from time t36.
In the first half of these 1 cycles until the falling edge of K, reading of data from a 3MOS type cell in a certain column is started, and in the latter half, writing of data from the 3MOS type cell in the same column is started. .

Therefore, in this case, the delay time is only shifted by a time smaller than 1H by less than 1 cycle of the write control clock WCLK and the read control clock RCLK (for example, 1/2 cycle), and 1H. The delay accuracy of the delay means is further enhanced.

In addition, in FIG. 3 and FIG. 9, the write control clock W
As is clear from a comparison of the data write timing in the same 3MOS type cell 39 with the detection timing (t1, t36) of the write reset signal WRES by CLK,
In the case of the operation shown in FIG. 9, compared to the operation shown in FIG.
The data write timing is 1 of the write control clock WCLK.
It means that it has been advanced by the cycle. Therefore, it is necessary to advance the data DATA ′ to be written in accordance with this by one cycle, and the D-FF 7b for adjusting the phase of the data DATA in FIG. 1 is not necessary. Therefore, FIG.
As shown in FIG.
Only the D-FF 7a for synchronizing with LK can be used. Similarly, the write control circuit 4 shown in FIG.
Also, the D-FF 7d for phase adjustment in the write system reset edge detection circuit 31 is unnecessary, and as shown in FIG. 11, therefore, the D-FFs 7d and 7e as shown in FIG.
Will be enough.

As described above, in the above-described embodiment, the delay of any time including 1H can be performed, and the read data is destroyed even if the data writing and reading are simultaneously performed in the same column. In addition, the chip area can be reduced by eliminating the need for the sense amplifier required in the above-mentioned conventional technique.

Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments. For example, if the configuration of the memory cell array 1 is 10 rows 100
Although the number of columns and columns is not limited to this, any number of rows and columns may be used.

[0092]

As described above, according to the present invention,
Simultaneous write / read operations using a memory cell array composed of 3MOS type cells can be performed without causing destruction of stored data, the chip area can be reduced, and 1H can be achieved. It is possible to delay for any time including.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a serial access memory according to the present invention.

FIG. 2 is a block diagram showing a specific example of a write control circuit in FIG.

FIG. 3 is a timing chart showing a write operation of the first embodiment.

FIG. 4 is a circuit diagram showing a specific example of the memory cell array in FIG.

5 is a block diagram showing a specific example of a read system control circuit in FIG.

FIG. 6 is a timing chart showing the read operation of the first embodiment.

FIG. 7 is a timing chart showing the operation when the 1H delay means is used in the first embodiment.

FIG. 8 is a timing chart showing an operation when the first embodiment is used as a delay unit having an arbitrary delay time.

FIG. 9 is a timing chart showing the operation of the second embodiment of the serial access memory according to the present invention.

FIG. 10 is a block diagram showing the overall configuration of a second embodiment.

11 is a block diagram showing a specific example of a write control circuit in FIG.

FIG. 12 is a circuit diagram showing a configuration of a 3MOS type cell.

FIG. 13 is a circuit diagram showing a configuration of a conventional memory cell array using 3MOS type cells.

[Explanation of symbols]

 1 Memory Cell Array 2 Write Decoder 3 Read Decoder 4 Write System Control Circuit 5 Read System Control Circuit 31 Write System Reset Edge Detection Circuit 33 Write Row Address Counter 34 Write Address Generation Circuit 35 Write Timing Generation Circuit 38 Charging MOSFET 39 3MOS type cell 40 Discharge MOSFET 41 Write MOSFET 42 Read MOSFET 46 Read system reset edge detection circuit 48 Read row address counter 49 Read address generation circuit 50 Read timing generation circuit

Claims (1)

[Claims] 1. A 3MOS type cell composed of three MOSFETs is arranged in m rows and n columns, and a write bit line and a read bit line are provided for each row of the arrangement of the 3MOS type cells, and the 3M type cell is provided.
A memory cell array in which a write word line and a read word line are provided for each column of the array of OS cells, and m write bit line selection switch control signals are sequentially generated one by one and repeatedly, and A write control circuit that generates a write address signal each time m write bit line selection switch control signals are generated, and m read bit line selection switch control signals one by one and repeatedly. , A read control circuit that generates a read address signal every time the read bit line selection switch control signal is generated m, and n read memory circuits of the memory cell array according to the write address signal from the write control circuit. A write decoder that sequentially selects the write word lines one by one, and n read word lines of the memory cell array sequentially according to the read address signal from the read control circuit. A read decoder that selects one by one, and the m write bit lines of the memory cell array are sequentially selected one by one according to the write bit line selection switch control signal to select the memory cell array. Further, data is written in the 3MOS type cell at a position determined by the write bit line and the write word line, and m read bits of the memory cell array are read according to the read bit line selection switch control signal. In a serial access memory in which lines are sequentially selected one by one, and data is read from the 3MOS type cell at a position determined by the selected read bit line and read word line of the memory cell array, A discharge MOSFET is provided for each embedded bit line, and each time the write control circuit generates the write bit line selection switch control signals, the write bit line selection switch control signals are generated. Means for generating an internal bit line discharge control signal is provided, and every time the write word line is selected by the write decoder, all the discharge MOSFETs are driven by the write bit line discharge control signal, A serial access memory characterized in that all the write bit lines are discharged.