JPH0635620A - System for controlling storage device - Google Patents

Abstract

PURPOSE:To constitute a system so that an access can be made even from a sector on the halfway so that the time required for completing read/write can be shortened by comparing and deciding the ranges of a sector detection address and an access designation address. CONSTITUTION:A read-out command consisting of the head number of a sector to be read out and the number of sectors is transferred from a host computer 1 to a control circuit. The control circuit transfers the head number and the number of sectors to an address comparing circuit 11. On the other hand, read- out information from a head 32 is read out by a reading-out circuit 13 and only sector address information is transferred to the address comparator circuit 11. A comparing/deciding circuit 14 compares whether the head sector address information is within the range of a final sector address number obtained by adding the number of sectors to the address information or not. In the case it is within the range, a data storing command is requested immediately to a buffer memory 12 to the control circuit and in the buffer memory 12, data corresponding to a current sector address 11b are transferred successively to the host computer 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control system for a disk storage device.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a control system of a conventional disk storage device. In the figure, 1 is a host computer that issues a read / write command, 1a is a read command line, 2 is a control circuit that controls the operation of the control system,
Reference numeral 2a is an address information line for reading, and 2b is a transfer command line for instructing data transfer. Reference numeral 13 is a read circuit for controlling the reading of the disk storage device, 13a is a sector address information line, 13b is a data line, 32 is a head, 53 is an address match detection circuit for detecting a match between read address information and sector address information, and 53a. Is an address match signal line, and 55 is a transfer register for transferring data with the host computer 1.

First, the storage format of the disk storage device will be described. FIG. 3 shows the format, and the sector 31 is divided into one round. Next, the operation will be described. The disk is rotating and the information is sequentially read by the head 32. The details of the sector 31 are composed of an address 43 showing the number of the sector 31 and data 44 as shown in FIG. Therefore, in the block diagram of the control system of the conventional disk storage device shown in FIG. 5, the host computer 1 transfers to the control circuit 2 a read command consisting of the sector start number and the number of sectors to be read, which is transferred on the line 1a. In the control circuit 2, the address information of the first sector is transferred to the address information line 2a.
And transfer it to the address match detection circuit 53.

In this state, the read information from the head 32 is placed on the line 32a and transferred to the read circuit 13. From there, the sector address information is placed on the line 13a and transferred to the address coincidence detection circuit 53. The address coincidence detection circuit 53 compares with the address information of the head sector from the control circuit 2. As a result, if they do not match, the read circuit 13 waits for the sector address information to be transferred. Prompt the transfer of. On the other hand, in the transfer register 12, the data from the read circuit 13 is transferred to the line 1 in synchronization with the transfer command from the control circuit 2.
3b and transfers the disk storage information to the host computer 1 on its line 12a.

[0005]

Since the conventional disk storage device control method is controlled as described above, it is only when the address information of the leading sector to be read and the sector address information read from the head 32 match. Data can be read. If both addresses do not match, the address 4 of the sector 31 expected by the head 32
At the position immediately after 3, it is necessary to wait for the sector to make one round, and when reading all sectors, there is a problem that a maximum of two rounds of time is required. During this time, there is also a problem that the disk storage device operates wastefully.

The present invention has been made to solve the above problems, and an object thereof is to obtain a control system for a storage device which shortens the disk rotation waiting time and speeds up the write / read operation. To do.

[0007]

A control method for a storage device according to the present invention compares a detected address from the storage device with an external access designated address for data access to the storage device, Comparing and judging means for judging that the detected address is within the range of the designated address, and number adding means for adding a sequence-corresponding number within the specified address are provided, and the detected address is within the range of the designated address. When judged, the corresponding detection address is accessed, and if necessary, the sequence corresponding number in the designated address is added and the data is transmitted. Further, the invention of claim 2 is for data access to a storage device,
A comparison / determination means for comparing the detected address from the storage device with an external access designated address to determine that the detected address is within the designated address range, and temporarily storing data for the access. A buffer memory and an address sequence sending means are provided, and when it is determined that the detected address is within the range of the designated address, the corresponding detected address is accessed, and when the access of the entire designated address range ends, the The data was sent out in the order of addresses within the specified address.

[0008]

In the storage device control method according to the present invention, when the detected address from the storage device and the designated address from the outside match, the storage devices are accessed in the order of matching. Further, the data is sent to the outside in the order in which the addresses match, with the order corresponding numbers in the addresses being added if necessary. In the invention of claim 2, when the detected address from the storage device and the designated address from the outside match, the storage device is accessed in the order of matching. Data is sent to the outside by rearranging in the order of addresses when the access to all designated address ranges is completed.

[0009]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a storage device control system according to the present invention. In FIG. 1, 2c is a read / write sector number information line, 2d is a data storage command line, 2
e is a sequence number line. An address comparison circuit 11 compares the read sector address information with the information from the address information line 2a and the sector number information line 2c from the control circuit 2. 11a is a detection signal line within the address range, 1
Reference numeral 2 is a buffer memory for arranging the order of data transferred with the host computer 1. Reference numeral 14 is a comparison / determination circuit that determines whether or not the detected sector address is within a designated address range from the outside of the control circuit, and 15 is the address of the data read from the sector, which is the number of the designated address range. Is a number adding circuit for adding a number to identify whether or not the address is. Other parts are the same as in the conventional example.

Next, the operation will be described. In FIG. 1, the host computer 1 transfers to the control circuit 2 a read command consisting of the head number of the sector to be read and the number of sectors to be read, placed on the line 1a. In the control circuit 52, the address information of the leading sector and the sector number information to be read are placed on each line and transferred to the address comparison circuit 11. On the other hand, the read information from the head 32 is read by the read circuit 13 and only the sector address information is transferred to the address comparison circuit 11 through the line 13a. In the address comparison circuit 11 and the comparison determination circuit 14, the head sector address information (information 2a) from the control circuit 2 and sector number information (information 2c) are added to the access address information.
Is compared to see if it is within the range of the final sector address number.

If the result of comparison and determination is within the range, it is immediately output to the address range detection signal line 11a, and the control circuit 2
To the buffer memory 12 (2d
Information). As a result, the buffer memory 12
Then, in synchronization with the data storage command from the control circuit 52, the data from the read circuit 13 corresponding to the current sector address information (information of 11b) from the address comparison circuit 11 is read via the data line 13b, Sequential data within the designated address range from the number adding circuit 15 is added and sequentially transferred to the host computer 1 as disk storage information (information of 12a).

In the above embodiment, when data is transferred to the host in the order in which it is determined that the detected address coincides with the address within the specified range, the buffer memory may have a small capacity and a simple register. In this case, the host side creates a complete sentence based on the sequence data. In the above embodiment,
Although the read operation has been described, the write operation is also an operation of writing in the corresponding sector position of the storage device in the order in which the coincidence of both addresses is detected, as in the above embodiment.

Example 2. Next, the invention of claim 2 will be described based on an embodiment shown in FIG. In the figure, 12 represents the buffer memory of FIG. 1, and this memory is assumed to be composed of data storage areas 21 to 26. Further, in the configuration diagram of the control system in this case, an address sequential transmission control circuit 16 is provided instead of the number addition circuit 15 of FIG. Also,
The buffer memory 12 has a capacity for temporarily accommodating at least one sector of data to be transferred at one time. Now, assume that the data with sector address numbers 1 to 5 is read. When the head 32 happens to be at the position where the sector address is 3, when the read command comes and the command is executed, the details of the storage order in the memory buffer are as follows.

First, the data transferred to the memory buffer 12 is data having a sector address of 3,
Since the first sector is the third sector from the first address, the address sequential transmission control circuit 16 checks the sequence, and the data is stored in the third data storage area 21 of the memory buffer 12. Next, since the data having the sector address of 4 is transferred, the data is similarly stored in the fourth data storage area 22 from the beginning, and subsequently, similarly,
Data is stored in the fifth data storage area 23 from the top. Next, the data having the sector address of 1 is transferred, the data is stored in the first data storage area 24 from the head, and similarly, the data is stored in the second data storage area 25 from the head. No data is stored in the data storage area 26. In this way, when the data 1 to data 5 are prepared, the data are continuously transferred to the host computer 1 in this order.

In the second embodiment, the buffer from the storage device
When the data is stored in the memory 12, the data 1 to 5 are rearranged so as to be in the order of addresses, but when the data is stored in the buffer memory 12, they are stored in the order of reading,
The address forwarding control circuit 1 for continuous transfer to the host
6, the data 1 to the data 5 may be sequentially transmitted in the address order.

Further, in the above-mentioned embodiment, the read operation is shown, but also in the write operation, similarly to the above-mentioned embodiment, the data is once stored in the buffer memory 12 and the detected sector address and the designated address range match. In this order, the writing operation is performed in the corresponding sector position of the storage device. Further, although the memory buffer is one of the control system configurations in the above-described embodiment, the same effect can be achieved even if the memory buffer is implemented in the memory in the host computer.

[0017]

As described above, according to the present invention, since the comparison / determination means for determining the sector detection address and the range of the access designation address is provided, the write / read operation can be performed even from the intermediate sector. This has the effect of shortening the time required to complete read / write.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a control system of a storage device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating writing to a memory according to the control method of the storage device of claim 2;

FIG. 3 is a diagram showing a storage format of a disk storage device and a position of a head.

FIG. 4 is a diagram showing details of a storage format within a sector of a disk storage device.

FIG. 5 is a configuration diagram of a conventional storage device control method.

[Explanation of symbols]

 1 host computer 1a read command line 2 control circuit 2a address information line 2b transfer command line 2c sector number information line 2d data storage command line 2e sequence number line 11 address comparison circuit 11a address range detection signal line 11b current sector address information line 12 Buffer memory 12a Disk storage information line 13 Read circuit 13a Sector address information line 13b Data line 14 Comparison judgment circuit 15 Number addition circuit 16 Address sequential sending control circuit 31 Sector 32 Head 32a Read information 43 Address 44 data

Claims (2)

[Claims] 1. For data access to a storage device, a detection address from the storage device is compared with an external access designated address, and the detection address is within the range of the designated address. Comparing and judging means, and number adding means for adding the order corresponding number in the designated address are provided. When it is determined that the detected address is within the range of the designated address, the corresponding detected address is accessed and necessary. A method of controlling a storage device for transmitting data by adding a sequence corresponding number in the designated address according to the above. 2. For data access to a storage device, a detection address from the storage device is compared with an access designated address from the outside, and the detection address is within a range of the designated address. Comparison determination means, buffer memory for temporarily storing the data for access, address order sending means for indicating the address order of the data within the specified address, and the detected address is determined to be within the range of the specified address. Then, the control method of the storage device in which the corresponding detection address is accessed, and when the access to the entire designated address range is completed, data is sent out in the order of addresses within the designated address as necessary.