JPH06350396A - Decimation circuit - Google Patents

Abstract

PURPOSE:To reduce a circuit scale and to reduce power consumption by simplifying the circuit configuration of a digital filter sections of both a medium speed conversion circuit and a low speed conversion circuit and realizing a filter characteristic of filters except low pass type filters in a few tap numbers. CONSTITUTION:A decimation circuit in an A/D converter circuit is made up of three stages of a high speed conversion circuit 21, a medium speed conversion circuit 22 and a low speed conversion circuit 23. Thus, the sampling frequency of input data is decreased in order of the high speed conversion circuit 21, the medium speed conversion circuit 22 and the low speed conversion circuit 23 and an optional frequency characteristic is set to a digital filter section of the low speed conversion circuit 23 whose sampling frequency is lowest.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oversampling type analog / digital conversion circuit (hereinafter referred to as an A / D conversion circuit), which is used for a modulation / demodulation device or the like which requires an arbitrary frequency characteristic, and more particularly The present invention relates to a decimation circuit for reducing the sampling frequency accelerated by sampling to the original sampling frequency.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional example and is a frequency characteristic diagram showing a frequency characteristic of a second conversion circuit in a decimation circuit. FIG. 5 is a block diagram showing an A / D conversion circuit and a digital filter in the case of digitally processing a reception signal of the frequency division multiplexing system.
FIG. 6 is a block diagram showing a delta-sigma modulation A / D conversion circuit and a digital filter in the case of digitally processing a reception signal of the frequency division multiplexing system. FIG. 7 shows a conventional example and is a block diagram showing a configuration of an A / D conversion circuit of a delta-sigma modulation system.

In a modem (modulator / demodulator) or the like, when a received signal of the frequency division multiplexing system is digitally processed and the signal after analog / digital conversion has a predetermined frequency characteristic, it is input as shown in FIG. After converting the analog signal into a digital signal by the A / D conversion circuit 110,
It is necessary for the digital filter 120 to extract only the signal in the frequency band of the received signal. A of this FIG.
The same applies when the A / D conversion circuit 110 is the delta-sigma modulation type A / D conversion circuit 130. As shown in FIG. 6, after the A / D conversion circuit 130, only the signal in the frequency band of the reception signal is received. Digital filter 1 for taking out
Twenty must be connected.

A / D conversion circuit 1 of delta-sigma modulation system
Reference numeral 30 is an A / D conversion circuit that combines the oversampling method and the noise shaping method. This A /
The D conversion circuit 130 includes a delta sigma modulation circuit 131 and a decimation circuit 132. This A / D
The conversion circuit 130 receives the analog signal, and the delta-sigma modulation circuit 131 outputs a high-speed 1-bit digital signal. The decimation circuit 132 converts this into a multi-bit digital signal at the original sampling frequency. Further, the decimation circuit 132 normally decreases the sampling frequency by a two-stage configuration of a first conversion circuit 132a and a second conversion circuit 132b, and outputs a multi-bit digital signal at a low speed, as shown in the figure. Since the signal speed becomes low, the frequency characteristic is set to the low-pass characteristic in order to remove unnecessary components such as aliasing distortion generated at the time of sampling. Therefore, in order to obtain an arbitrary frequency characteristic, it is necessary to separately provide a digital filter. To extract only the signal in the frequency band of the received signal from the output of the A / D conversion circuit 130, A / D
It is necessary to connect the digital filter 120 after the D conversion circuit 130.

By the way, the A of the delta-sigma modulation system is used.
It has been conventionally proposed to add a low-pass or high-pass frequency characteristic to the decimation circuit 132 when the D / D conversion circuit 130 is used (actual fairness 4-5306).
No. 9).

As shown in FIG. 7, this delta-sigma modulation type A / D conversion circuit is composed of a delta-sigma modulation circuit 1 and a decimation circuit 2. The delta-sigma modulation circuit 1 has the same configuration as the delta-sigma modulation circuit 131 shown in FIG. 6, and the decimation circuit 2 is also configured by the first conversion circuit 24 and the second conversion circuit 25. The decimation circuit 13 shown in FIG. 6 above.
Same as 2. Further, the first conversion circuit 24 uses a window function for removing high-frequency noise such as aliasing distortion in the digital filter section, and this also has the same configuration as the first conversion circuit 132a shown in FIG.

The second conversion circuit 25 comprises a digital filter section and a decimation section. This second conversion circuit 2
As shown in FIG. 7, the number 5 is n (n
Is a positive integer), n multipliers 25b connected to the output of each of these delay devices 25a, and an adder 25c for adding the outputs of these multipliers 25b. There is. This is a FIR (Finite Impulse Res)
Since it has the same circuit configuration as the ponse) type digital filter, the digital filter section is configured. Further, the adder 25c constitutes a decimation section by thinning out and outputting the data to be added, thereby lowering the sampling frequency. In the case of an ordinary delta-sigma modulation type A / D conversion circuit, the digital filter section of the second conversion circuit 25 is set to have a low-pass characteristic in order to remove unnecessary high-frequency components. In the A / D conversion circuit of No. 7, each multiplier 2
The filter coefficient multiplied by 5b is adjusted to add an arbitrary frequency characteristic other than the low-pass characteristic.

Therefore, in the A / D conversion circuit of the delta-sigma modulation system shown in FIG. 7, it is possible to set an arbitrary frequency characteristic in the second conversion circuit 25 of the decimation circuit 2, and therefore, it is shown in FIG. The digital filter 120 is unnecessary, and the circuit configuration can be simplified.

[0009]

However, when the high-pass characteristic or the band-pass characteristic other than the low-pass characteristic is set in the second conversion circuit 25, the filter order becomes large, and the delay device 25a and the multiplier 25b have a large filter order. As the number increases,
The circuit scale of the second conversion circuit 25 shown in FIG. 6 is larger than that of the second conversion circuit 132b shown in FIG. Moreover, this filter order generally increases in proportion to the sampling frequency, and the multiplier 2 in the second conversion circuit 25 in FIG.
Since 5b has to operate at the sampling frequency of the data output from the first conversion circuit 24, the sampling frequency becomes higher than that of the digital filter 120 of FIG.
The circuit scale becomes larger than 20. For this reason, A / of the conventional delta-sigma modulation system with arbitrary frequency characteristics added
The D conversion circuit has a problem that the effect of reducing the circuit scale is not sufficient.

An object of the present invention is to reduce the sampling frequency of input data in order by a three-step conversion circuit and set an arbitrary frequency characteristic in the digital filter section of the low-speed conversion circuit having the lowest sampling frequency. An object of the present invention is to provide a decimation circuit that can simplify the circuit configuration of the filter unit.

[0011]

In order to solve the above-mentioned problems, the decimation circuit of the present invention uses a data of an arbitrary frequency characteristic other than the low-pass characteristic when lowering the sampling frequency to a predetermined sampling frequency. Is a decimation circuit configured to output only, a window function is set in the digital filter unit, input data sampled at the first sampling frequency is received, and data sampled at the second sampling frequency is received. A high-speed conversion circuit for outputting and a digital filter section having a low-pass characteristic, a medium-speed conversion circuit for receiving data from the high-speed conversion circuit and outputting data sampled at a third sampling frequency, and a low-frequency conversion circuit. Includes a digital filter section having frequency characteristics other than pass characteristics, It receives data from the circuit, a fourth and a low-speed conversion circuit for outputting the sampled data at the sampling frequency, highest first sampling frequency, the second sampling frequency,
The above-mentioned object is achieved by the sampling frequency being low in the order of the third sampling frequency and the fourth sampling frequency.

[0012]

The digital data which is high-speed sampled and quantized by the oversampling is input to the decimation circuit of the present invention, and passes through the high-speed conversion circuit, the medium-speed conversion circuit and the low-speed conversion circuit to sample the sampling frequency as originally It will be output down to the frequency. Further, at this time, the decimation circuit of the present invention outputs only the data of any frequency characteristic other than the low-pass characteristic. The A / D conversion circuit in the preceding stage of this decimation circuit may be of a delta sigma modulation system using an oversampling system.

The high-speed conversion circuit removes unnecessary components such as aliasing distortion at the time of sampling by passing the input data of high-speed sampling through the digital filter section in which the window function is set, and thins out the data output in the decimation section. The sampling frequency is lowered and converted to medium-speed sampling data. In addition, the medium-speed conversion circuit removes unnecessary high-frequency components by passing the medium-speed sampling data output from the high-speed conversion circuit through a digital filter unit in which a low-pass characteristic is set, and at the same time, the decimation unit converts the data. The sampling frequency is further reduced and converted to low-speed sampling data. Then, the low-speed conversion circuit allows the low-speed sampling data output from the medium-speed conversion circuit to pass through the digital filter unit in which a desired frequency characteristic other than the low-pass characteristic is set, thereby limiting only the arbitrary frequency characteristic. , The decimation unit further lowers the sampling frequency by one step and converts it into the original sampling frequency data. The frequency characteristics other than the low pass characteristic include a band pass characteristic, a high pass characteristic, and a band attenuation characteristic.

Here, the digital filter section of the medium-speed conversion circuit in which the low-pass characteristic is set to remove unnecessary high-frequency components does not need to have frequency characteristics other than the low-pass characteristic, so the filter order is It can be made small and the circuit configuration becomes extremely simple. Further, in the digital filter section of the low-speed conversion circuit in which the frequency characteristics other than the low-pass characteristics are set in order to obtain the desired frequency characteristics, the filter order cannot be made too small, unlike the case of only the low-pass characteristics. As compared with the case where the same frequency characteristic is obtained in the medium-speed conversion circuit that handles the data of the medium-speed sampling whose sampling frequency is faster than this, the filter order can be made sufficiently small and the circuit configuration becomes simple.

Generally, in a FIR type digital filter, when it is desired to obtain the same filter characteristics for the pass band and the ripple, the filter order is proportional to the sampling frequency. Therefore, the higher the ratio of the sampling frequency of the medium-speed sampling data input by the medium-speed conversion circuit to the low-speed sampling data input by the low-speed conversion circuit, the higher the sampling frequency of the medium-speed conversion circuit becomes. Than the filter order required when also having the frequency characteristics of
The sum of the filter orders of the digital filter section of the medium speed conversion circuit and the digital filter section of the low speed conversion circuit in the present invention is smaller. Moreover, the number of arithmetic circuits for multiplying the filter coefficients is reduced in accordance with the filter order, and the digital filter portion of the low speed conversion circuit can use a slower arithmetic speed.

As a result, according to the decimation circuit of the present invention, the number of taps of the delay device and the number of arithmetic circuits are reduced by reducing the filter order of the digital filter section, and this arithmetic circuit also has a higher operation speed. Since the slower one can be used, the circuit configuration can be simplified and the circuit scale can be reduced.

[0017]

EXAMPLES Examples of the present invention will be described below. As an example, a delta-sigma modulation type A / D conversion circuit used in a reception circuit of a modem will be described.

One embodiment of the present invention is shown in FIGS. Figure 1 shows the delta-sigma modulation system A /
It is a block diagram which shows the structure of a D conversion circuit. FIG. 2 is a frequency characteristic diagram showing frequency characteristics of the medium speed conversion circuit in the decimation circuit. FIG. 3 is a frequency characteristic diagram showing the frequency characteristic of the low speed conversion circuit in the decimation circuit. In addition, the same numbers are added to the constituent members having the same functions as those of the conventional example shown in FIG.

As shown in FIG. 1, the A / D conversion circuit is composed of a delta-sigma modulation circuit 1 and a decimation circuit 2. The delta sigma modulation circuit 1 has the same configuration as the delta sigma modulation circuit 1 in the conventional A / D conversion circuit shown in FIG. 7, and oversamples the input analog signal to input it by the delta sigma modulation method. The converted analog signal is converted into a high-speed 1-bit digital signal.

The decimation circuit 2 is a high speed conversion circuit 2.
1, a medium speed conversion circuit 22 and a low speed conversion circuit 23 are included. These high speed conversion circuit 21, medium speed conversion circuit 22,
The low-speed conversion circuit 23 and the low-speed conversion circuit 23 respectively include a digital filter section and a decimation section.

The high speed conversion circuit 21 has the same structure as the first conversion circuit 24 in the decimation circuit 2 of FIG. 7, and by setting the window function in the digital filter section, unnecessary signals in the signal such as aliasing distortion can be eliminated. In addition to removing the component, the decimation section is provided with a delta-sigma modulation circuit 1
The sampling frequency of the high-speed 1-bit digital signal output from is reduced to convert the input signal to the high-speed conversion circuit 21 into a medium-speed multi-bit digital signal.

As shown in FIG. 1, the medium speed conversion circuit 22 is connected in cascade (i is a positive integer).
22a, i multipliers 22b connected to the outputs of the respective delay devices 22a, and an adder 22c for adding the outputs of the multipliers 22b.

The delay unit 22a, the multiplier 22b, and the adder 22c constitute a digital filter section. This digital filter section acts as an FIR type digital filter. This digital filter unit is set so that the frequency characteristic becomes a low-pass characteristic by adjusting the coefficient used for multiplication in the multiplier 22b. The adder 22c constitutes a decimation unit. The adder 22c reduces the sampling frequency again by thinning out and outputting the added data.

The medium speed conversion circuit 22 removes unnecessary high frequency components in the signal by setting a low-pass characteristic in the digital filter section, and the decimation section outputs the medium speed conversion circuit 21. And by lowering the sampling frequency of the multi-bit digital signal again,
The input signal to the medium speed conversion circuit 22 is converted into a low speed and multi-bit digital signal.

A more specific description will be given. The medium-speed conversion circuit 22 removes aliasing distortion by suppressing frequency components at a frequency equal to or higher than half the upper limit of the frequency of the signal in the frequency band of the signal output from the high-speed conversion circuit 21. As described above, the medium-speed conversion circuit 22 has an effect of halving the sampling frequency, so that it is not necessary to make the frequency characteristic steep, and further,
A low-pass digital filter that attenuates the high-frequency part and operates at a sampling frequency of ½ to generate an output signal may be used, whereby the circuit scale can be reduced. Here, the ratio of the output frequency of the high speed conversion circuit 21 and the output frequency of the medium speed conversion circuit 22 is 4: 2.

As shown in FIG. 1, the low-speed conversion circuit 23 is connected in cascade (j is a positive integer).
23a, j number of multipliers 23b connected to the output of each of these delay devices 23a, and an adder 23c for adding the outputs of these multipliers 23b.

The delay unit 23a, the multiplier 23b, and the adder 23c constitute a digital filter section. This digital filter section acts as an FIR type digital filter. In this digital filter unit, the frequency characteristic is set to a frequency characteristic other than the low-pass characteristic by adjusting the coefficient used for multiplication in the multiplier 23b. The adder 23c constitutes a decimation unit. The adder 23c reduces the sampling frequency to the original sampling frequency by thinning and outputting the added data.

In the low-speed conversion circuit 23, frequency characteristics other than the low-pass characteristics are set in the digital filter section, and the decimation section samples the low-speed and multi-bit digital signal output from the medium-speed conversion circuit 22. By further reducing the frequency, the input analog signal is converted into a digital signal sampled at the original sampling frequency.

A more specific description will be given. The low-speed conversion circuit 23 samples the signal output from the medium-speed conversion circuit 22 at a low sampling frequency. already,
With the medium speed conversion circuit 22, the sampling frequency is 1 /
Since it is 2, in the low speed conversion circuit 23, 1
With the number of taps of / 2, the same frequency characteristic as the conventional one can be obtained. Comparing the second conversion circuit of the prior art with the low speed conversion circuit 23 of the present invention, the sampling frequency of the low speed conversion circuit 23 of the present invention is 1/2 of the sampling frequency of the second conversion circuit of the prior art. Since the delay amount of one delay device is doubled, the number of delay devices is 1/2,
The same frequency characteristic as that of the second conversion circuit of the related art can be obtained. The sampling frequency ratio of the output from the medium speed conversion circuit 22 and the output from the low speed conversion circuit 23 is 2: 1. Therefore, the ratio of the sampling frequencies of the high speed conversion circuit 21, the medium speed conversion circuit 22 and the low speed conversion circuit 23 is 4: 2: 1. The factor that directly affects the circuit scale or the number of calculations is F
In the case of an IR type digital filter, it is the filter order (the number of taps), and in the circuit of the present invention, it is the number of delay units DL and multipliers MP.

The operation of the A / D conversion circuit having the above structure will be described. In the present embodiment, the sampling frequency in the high speed conversion circuit 21 is 28800 hertz (hereinafter referred to as Hz).
The sampling frequency in the medium speed conversion circuit 22 is set to 14400 Hz, which is one half of the sampling frequency, and the low speed conversion circuit 23
The case where the original sampling frequency output by the device is 7200 Hz, which is one half of the original sampling frequency, is shown. The following band pass characteristics are set in the digital filter section of the low speed conversion circuit 23 as an example.

The design method is the optimum linear phase method, the frequency characteristic is a band pass type, and the lower limit frequency of the pass band is 2000 Hz.
The upper limit frequency of the pass band is 3000 Hz, the maximum attenuation of the pass band is 1 dB, and the upper limit frequency of the lower stop band is 1400.
Hz, the maximum attenuation of the lower stopband is 40 dB, the lower limit frequency of the upper stopband is 3600 Hz, and the maximum attenuation of the upper stopband is 40 dB. The low speed conversion circuit 23
The design of the digital filter unit of (1) used the design method of the FIR type digital filter. More specifically, Mc
The design method of the linear phase FIR filter by Clellan and Parks was used.

Here, in the case of the conventional decimation circuit 2 shown in FIG. 7, since the first conversion circuit 24 has the same structure as the high speed conversion circuit 21 of the present embodiment, the sampling frequency of the output data is 28800 Hz. , The second conversion circuit 2
5 would reduce this to a quarter, 7200 Hz. Therefore, when the band pass characteristic is added to the digital filter section of the second conversion circuit 25,
28800 from 3600 Hz, which is the Nyquist frequency of Hz
Since aliasing distortion occurs over a wide frequency band up to Hz, it is necessary to reliably attenuate the signal in this band. For this purpose, a filter order of 61 (61 taps) is required.
Is required. That is, the second conversion circuit 25 has 61 (=
n) delay devices 25a and 61 multipliers 25b are required, and the 61 multipliers 25b are 2880
A fast multiplication of the filter coefficients has to be performed at a frequency of 0 Hz. As shown in FIG. 4, the second conversion circuit 25 at this time has a Nyquist frequency of 1840, which is a Nyquist frequency of 28800 Hz, except for the pass band from 2000 Hz to 3000 Hz.
The characteristic is that no pass band is generated over a wide frequency band up to 0 Hz.

However, the medium speed conversion circuit 22 in this embodiment changes the output of the high speed conversion circuit 21 to the low speed conversion circuit 23.
This is for attenuating the frequency component of the portion which causes the aliasing distortion, and the coefficient and the number of multipliers are set so as to be a low-pass FIR digital filter. Since the digital filter portion of the medium speed conversion circuit 22 is a digital filter having a low-pass characteristic, the sampling frequency is a high sampling frequency of 28800 Hz, but the filter order (number of taps) is 11. Therefore, the delay unit 22a and the multiplier 2
The number of 2b is 11 each, 28800Hz
The number of multipliers 22b that need to be multiplied by the filter coefficient at a high frequency is only 11. At this time, in the medium speed conversion circuit 22, as shown in FIG. 2, the upper limit frequency of the pass band is 3600 Hz and the lower limit frequency of the cutoff region is about 7 Hz.
A slow characteristic of 200 Hz is sufficient.

On the other hand, the low speed conversion circuit 23 has a band pass type frequency characteristic in this embodiment. Low speed conversion circuit 2
Although the band pass characteristic is set in the digital filter unit 3 of 3, the sampling frequency is 14
Since the frequency is 400 Hz, the filter order (number of taps) is 3
It becomes 1. Therefore, the numbers of the delay devices 23a and the multipliers 23b are 31, respectively, and the 31 multipliers 23b are also 1 in number.
The multiplication of the filter coefficient may be performed at a relatively low frequency of 4400 Hz. At this time, the low-speed conversion circuit 23 has a pass band of 2000 Hz to 3000 as shown in FIG.
In addition to up to 10Hz, 10800Hz to 1300Hz
Although it appears in the period between 10800Hz and 1300
Since the signals up to Hz have already been attenuated by the low-pass characteristics of the medium speed conversion circuit 22, these medium speed conversion circuit 22
And the frequency characteristic of the low-speed conversion circuit 23 are equivalent to the frequency characteristic of the conventional second conversion circuit 25 shown in FIG.

At this time, the signal input to the low-speed conversion circuit 23 has the sampling frequency halved by the medium-speed conversion circuit 22, and the high frequency component has already been attenuated. As shown in FIG. 3, even if there is a band that is not attenuated on the high frequency side, as a result, a characteristic equivalent to the frequency characteristic shown in FIG. 4 is obtained.

As described above, according to the decimation circuit 2 of this embodiment, in order to obtain the same band pass characteristic, the filter order of 61 in the prior art is changed to the medium speed conversion circuit 22 and the low speed. The sum of the filter orders with the conversion circuit 23 is 42 (= 11 + 31). Delay devices 22a and 23
The circuit scale can be reduced by reducing the number of a and the multipliers 22b and 23b by the value of the difference between the filter orders. Further, in the past, as many as 61 multipliers 25b have been used.
However, it was necessary to perform high-speed calculation at a frequency of 28800 Hz. In the case of the present embodiment, the 11 multipliers 22b in the medium speed conversion circuit 22 perform the high speed operation at the frequency of 28800 Hz, so that 3 in the low speed conversion circuit 23.
The single multiplier 23b can perform an operation at a relatively low frequency of 14400 Hz. The number of multipliers in the medium speed conversion circuit 22 is 1/6 of the number of multipliers in the conventional circuit, and the number of circuit elements is 42/61 of the number of circuit elements according to the conventional circuit configuration.

Therefore, it is possible to contribute to the reduction in the number of circuit elements in that the necessity of high-speed calculation is reduced. And with such a reduction in the number of circuit elements,
It is also possible to reduce power consumption.

When a filter design similar to that of the embodiment of the present invention is performed on the second conversion circuit 132b of FIG. 6, the cutoff frequency of the second conversion circuit 132b of FIG. 6 is 3600 Hz.
And the frequency characteristic curve becomes steeper than the curve shown in FIG. Also, the filter order of 59 is required. Comparing the circuit scales of FIGS. 6 and 7 with the circuit scale of the present invention, the circuit scale of FIG. 6 and the circuit scale of FIG. 7 are almost equal, whereas the present invention significantly reduces the circuit scale. I know that I can do it.

[0039]

As is apparent from the above description, according to the decimation circuit of the present invention, the sampling frequency of the input data is sequentially reduced by the three-stage conversion circuit so that the low-speed conversion circuit with the lowest sampling frequency can be used. By setting an arbitrary frequency characteristic in the digital filter section,
Since the circuit configuration of the digital filter unit can be simplified in the entire decimation circuit, the circuit scale can be reduced and the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention and showing a configuration of an A / D conversion circuit of a delta-sigma modulation system.

FIG. 2 shows an embodiment of the present invention and is a frequency characteristic diagram showing the frequency characteristic of the medium speed conversion circuit in the decimation circuit.

FIG. 3 is a frequency characteristic diagram showing the frequency characteristic of the low speed conversion circuit in the decimation circuit, showing the embodiment of the present invention.

FIG. 4 is a frequency characteristic diagram showing a conventional example and showing a frequency characteristic of a second conversion circuit in the decimation circuit.

FIG. 5 is a block diagram showing an A / D conversion circuit and a digital filter in the case of digitally processing a reception signal of the frequency division multiplexing system.

FIG. 6 is a block diagram showing a delta-sigma modulation A / D conversion circuit and a digital filter in the case of digitally processing a reception signal of the frequency division multiplexing system.

FIG. 7 is a block diagram showing a conventional example and showing a configuration of an A / D conversion circuit of a delta-sigma modulation system.

[Explanation of symbols]

 2 Decimation circuit 21 High speed conversion circuit 22 Medium speed conversion circuit 23 Low speed conversion circuit

Claims (1)

[Claims] 1. A decimation circuit configured to output only data having an arbitrary frequency characteristic other than a low-pass characteristic when the sampling frequency is lowered to a predetermined sampling frequency, wherein a window function is set. And a high-speed conversion circuit for receiving input data sampled at a first sampling frequency and outputting data sampled at a second sampling frequency, and a digital filter section having a low-pass characteristic. Then
The medium-speed conversion circuit includes a medium-speed conversion circuit that receives data from the high-speed conversion circuit and outputs data sampled at a third sampling frequency, and a digital filter unit having frequency characteristics other than low-pass characteristics. And a low-speed conversion circuit that outputs data sampled at a fourth sampling frequency, the first sampling frequency being the highest, the second sampling frequency, the second sampling frequency A decimation circuit in which the sampling frequency is set to decrease in the order of the third sampling frequency and the fourth sampling frequency.