JPH06349746A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH06349746A JPH06349746A JP14052693A JP14052693A JPH06349746A JP H06349746 A JPH06349746 A JP H06349746A JP 14052693 A JP14052693 A JP 14052693A JP 14052693 A JP14052693 A JP 14052693A JP H06349746 A JPH06349746 A JP H06349746A
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- Prior art keywords
- semiconductor
- ion
- substrate
- semiconductor layer
- distribution
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置及びその製
造方法に係る。さらに詳細には、キャリア濃度に分布を
もつ半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method. More specifically, the present invention relates to a semiconductor device having a carrier concentration distribution and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】ＬＳＩの高集積化に伴い個々の素子は益
々微細化が進んでいる。しかし、例えばＭＯＳＦＥＴに
おいて、短チャネル化が進むと、ゲートにバイアスを印
加していない状態でもソース側の空乏層とドレイン側の
空乏層が接してしまう現象（パンチスルー）が起こる。
パンチスルーを防ぐためにチャネル領域の下部ではキャ
リア濃度を高くする必要がある。この高濃度層を形成す
るためにイオン注入が一般に行われているが、以下に示
すようにイオン注入ではガウス分布のみしか形成できず
パンチスルー防止のための理想的なキャリア分布を形成
できない。2. Description of the Related Art With the high integration of LSIs, individual devices are becoming finer and finer. However, in a MOSFET, for example, as the channel becomes shorter, a phenomenon occurs in which the source-side depletion layer and the drain-side depletion layer are in contact with each other (punch-through) even when the gate is not biased.
In order to prevent punch through, it is necessary to increase the carrier concentration below the channel region. Ion implantation is generally performed to form this high-concentration layer, but as shown below, only Gaussian distribution can be formed by ion implantation, and an ideal carrier distribution for punch-through prevention cannot be formed.
【０００３】従来、半導体中にキャリア濃度の分布を形
成する手段としては、主として次の技術が知られてい
る。Conventionally, the following techniques are mainly known as means for forming a carrier concentration distribution in a semiconductor.
【０００４】（１）イオン注入技術により半導体表面か
ら不純物を打ち込む方法 （２）熱拡散技術により不純物を半導体中に浸透させる
方法 しかし、上記従来技術には、次のような問題がある。(1) Method of implanting impurities from semiconductor surface by ion implantation technology (2) Method of permeating impurities into semiconductor by thermal diffusion technology However, the above-mentioned conventional technology has the following problems.
【０００５】イオン注入技術では、注入された不純物が
ガウス分布をもつため、これ例外のキャリア濃度分布を
形成することはできない。一例として、加速電圧２００
ｋｅＶでＳｉにリンをイオン注入した例を図８に示す。
さらにイオン注入後には、結晶欠陥の除去及びイオン元
素の活性化のために１０００℃程度での熱処理が必要で
ある。このため、注入された不純物の分布は、熱拡散に
よってそのピーク値が低下し、分布の広がりも増大す
る。The ion implantation technique cannot form an exceptional carrier concentration distribution because the implanted impurities have a Gaussian distribution. As an example, the acceleration voltage 200
FIG. 8 shows an example in which phosphorus is ion-implanted into Si by keV.
Furthermore, after the ion implantation, a heat treatment at about 1000 ° C. is required for removing crystal defects and activating the ionic element. For this reason, the peak value of the distribution of the implanted impurities decreases due to thermal diffusion, and the spread of the distribution also increases.
【０００６】一方、熱拡散技術で形成される不純物濃度
分布は、一般的に図９のようになる。図９において、縦
軸は表面不純物濃度で規格化した不純物濃度の分布であ
り、横軸は拡散係数と拡散時間で規格化した深さであ
る。図が示すように、この技術では表面の不純物濃度を
高くすることは可能だが、半導体内部にキャリア濃度の
ピークを作ることはできない。また、１μｍ以下の薄い
拡散層を形成するのも困難である。このように熱拡散技
術では、不純物を拡散できる深さ及び分布形態に制約が
ある。また、一般的に、処理温度が１０００℃以上であ
るため、プロセスの低温化という点で問題がある。On the other hand, the impurity concentration distribution formed by the thermal diffusion technique is generally as shown in FIG. In FIG. 9, the vertical axis represents the distribution of the impurity concentration standardized by the surface impurity concentration, and the horizontal axis represents the depth standardized by the diffusion coefficient and the diffusion time. As shown in the figure, this technique can increase the surface impurity concentration, but cannot create a carrier concentration peak inside the semiconductor. It is also difficult to form a thin diffusion layer having a thickness of 1 μm or less. As described above, in the thermal diffusion technique, there are restrictions on the depth and distribution form in which impurities can be diffused. Further, generally, since the processing temperature is 1000 ° C. or higher, there is a problem in that the process temperature is lowered.
【０００７】また、上記方法以外に、熱ＣＶＤ法あるい
はプラズマＣＶＤ法を用い、堆積用ガス（ＳｉＨ4等）
と不純物用ガス（ＰＨ3，Ｂ2Ｈ6等）の流量比を経時的
に変化させ、膜厚方向にキャリア濃度を変える方法があ
るが応答性が悪く、例えばステップ状の分布を得ること
は非常に難しい。In addition to the above method, a thermal CVD method or a plasma CVD method is used, and a deposition gas (SiH 4 etc.) is used.
There is a method of changing the carrier concentration in the film thickness direction by changing the flow rate ratio of the impurity gas (PH 3 , B 2 H 6, etc.) with time, but the responsiveness is poor and, for example, a stepwise distribution cannot be obtained. very hard.
【０００８】半導体中のキャリア濃度の分布を任意の形
状にすることは、上記のチャネル内の分布以外にも要求
される場合は多数あるが、以上述べたように従来の技術
では、これらの要求に対して必ずしも理想的な分布を形
成できないのが現状である。There are many cases in which the carrier concentration distribution in the semiconductor has an arbitrary shape in addition to the above-mentioned distribution in the channel, but as described above, in the conventional technique, these requirements are satisfied. At present, however, it is not always possible to form an ideal distribution.
【０００９】[0009]
【本発明が解決しようとする課題】本発明は、半導体の
任意の深さに任意のキャリア濃度分布を形成することが
でき、且つ高温熱処理を必要としない半導体装置とその
製造方法を提供することを目的とする。SUMMARY OF THE INVENTION The present invention provides a semiconductor device capable of forming an arbitrary carrier concentration distribution in an arbitrary depth of a semiconductor and requiring no high temperature heat treatment, and a method of manufacturing the same. With the goal.
【００１０】[0010]
【課題を解決するための手段】本発明の半導体装置は、
基板上に堆積成長させた所定の不純物を含む半導体層を
用いた半導体装置において、前記半導体層中の前記不純
物の濃度と、前記不純物より供給されるキャリアの濃度
との比が、前記半導体層の膜厚方向に変化していること
を特徴とする。The semiconductor device of the present invention comprises:
In a semiconductor device using a semiconductor layer containing a predetermined impurity deposited and grown on a substrate, the ratio of the concentration of the impurity in the semiconductor layer to the concentration of carriers supplied from the impurity is It is characterized in that it changes in the film thickness direction.
【００１１】また、本発明の半導体装置の製造方法は、
基板上に所定の不純物を含む半導体層を堆積成長させる
方法において、前記半導体層の成長表面に対し連続的に
イオン照射を施すとともに、前記イオン照射のイオンエ
ネルギ及び／またはイオン照射量を、時間的に変化させ
ることにより、前記半導体層中の前記不純物の濃度と、
前記不純物より供給されるキャリアの濃度との比を、前
記半導体層の膜厚方向に変化させることを特徴とする。The semiconductor device manufacturing method of the present invention is
In a method of depositing and growing a semiconductor layer containing a predetermined impurity on a substrate, the growth surface of the semiconductor layer is continuously irradiated with ions, and the ion energy and / or the ion irradiation amount of the ion irradiation is temporally changed. By changing the concentration of the impurities in the semiconductor layer,
The ratio to the concentration of carriers supplied from the impurities is changed in the film thickness direction of the semiconductor layer.
【００１２】[0012]
【作用】堆積膜成長時に、照射するイオンのエネルギ及
び／または照射量を制御することにより、導入される不
純物の活性化率を変えることが可能となり、半導体材料
中の任意の位置に任意のキャリア濃度分布を形成するこ
とができる。When the deposited film is grown, the activation rate of the introduced impurities can be changed by controlling the energy and / or the irradiation amount of the ions to be irradiated, and it is possible to change the activation rate of the introduced impurities to arbitrary positions in the semiconductor material. A concentration distribution can be formed.
【００１３】この理由は、現在のところ明らかではない
が次のように考えられる。即ち、活性化には、堆積膜の
１原子当たりの照射されるイオンの全エネルギ量（即
ち、（イオンエネルギ）×（照射イオン数））が関係す
ると考えられ、不純物の活性化率は、一定の温度におい
て個々の堆積膜に対し照射イオンの全エネルギが適正な
値になると最大となり、エネルギ量が過剰になると結晶
性には影響を与えないものの、余分なエネルギが不純物
原子とシリコン原子との結合を弱めるため、活性化率は
低下するものと考えられる。The reason for this is not clear at present, but it is considered as follows. That is, it is considered that the activation is related to the total energy amount of irradiated ions per atom of the deposited film (that is, (ion energy) × (number of irradiated ions)), and the activation rate of impurities is constant. When the total energy of irradiated ions reaches a proper value for each deposited film at the temperature of, it becomes maximum, and if the amount of energy becomes excessive, it does not affect the crystallinity, but the extra energy causes the impurity atoms and silicon atoms It is thought that the activation rate is lowered because the binding is weakened.
【００１４】また、全エネルギが小さいと結晶成長がス
ムーズに行われず、結晶性は低下してしまうが、全エネ
ルギだけでなく、イオンエネルギ、イオン照射量の個々
についても結晶成長において重要な因子であり、イオン
エネルギは０〜３０ｅＶ、イオン照射量は堆積膜構成原
子１原子当たり１〜５０であることが好ましい。Further, if the total energy is small, the crystal growth will not be carried out smoothly and the crystallinity will be deteriorated. However, not only the total energy but also the ion energy and the ion irradiation dose are important factors in the crystal growth. It is preferable that the ion energy is 0 to 30 eV and the ion irradiation dose is 1 to 50 per atom constituting the deposited film.
【００１５】以上のように、イオンエネルギ及び／照射
量を適正値に制御することによって、結晶性を保ちなが
ら、キャリア濃度の膜厚方向の分布を自由に制御するこ
とができ、従来の技術では形成が困難であった、例えば
ステップ状キャリア濃度分布をもった結晶半導体を形成
することができるなど、半導体デバイスの高性能化を達
成することが可能となる。また、半導体層の堆積速度
は、前記イオン照射量が得られれば特に限定されること
はない。As described above, by controlling the ion energy and / or the irradiation amount to appropriate values, it is possible to freely control the carrier concentration distribution in the film thickness direction while maintaining crystallinity. It is possible to achieve high performance of a semiconductor device, which is difficult to form, for example, a crystalline semiconductor having a stepwise carrier concentration distribution can be formed. Moreover, the deposition rate of the semiconductor layer is not particularly limited as long as the ion irradiation amount is obtained.
【００１６】[0016]
【実施例】以下、本発明の実施例を説明する。 （実施例１）図１に、Ｓｉ薄膜形成に用いた低エネルギ
イオン照射プロセスを特徴とするＲＦ−ＤＣ結合バイア
ススパッタ装置の概略図を示す。本装置は、チャンバ１
０１とその内部に半導体製のターゲット１０２と、それ
と平行におかれた基板１０３を有し、ガス導入口１０４
と真空排気系１０５で構成されている。真空排気系１０
５は、オイルフリーのターボ分子ポンプとドライポンプ
で構成され、チャンバ１０１の到達真空度は１０-10台
の超高真空を達成している。また、超高純度のアルゴン
ガスがガス導入口１０４から供給されている。EXAMPLES Examples of the present invention will be described below. (Embodiment 1) FIG. 1 is a schematic view of an RF-DC coupled bias sputtering apparatus featuring a low energy ion irradiation process used for forming a Si thin film. The apparatus is chamber 1
01 and a semiconductor target 102 inside thereof, and a substrate 103 placed in parallel therewith, and a gas inlet 104
And an evacuation system 105. Vacuum exhaust system 10
Reference numeral 5 is composed of an oil-free turbo molecular pump and a dry pump, and the ultimate vacuum degree of the chamber 101 achieves an ultrahigh vacuum of 10 -10 units. Further, ultra-high purity argon gas is supplied from the gas inlet 104.
【００１７】プラズマ放電に用いるＲＦ電源１０９は、
ターゲット１０２にマッチング回路１０６を介して接続
されている。ターゲット１０２と基板１０３はそれぞれ
ローパスフィルタ１０７、１０７’を介して、直流電源
１０８、１０８’に接続されており、それぞれ独立に電
位を制御できる。The RF power source 109 used for plasma discharge is
It is connected to the target 102 via a matching circuit 106. The target 102 and the substrate 103 are connected to DC power supplies 108 and 108 'via low-pass filters 107 and 107', respectively, and the potentials can be controlled independently.
【００１８】プラズマ発生時のチャンバ内部の空間電位
分布は図２のようになり、照射イオン（Ａｒイオン）の
エネルギはプラズマポテンシャルＶｐと基板バイアスＶ
ｓの差で表される。つまり、基板１０３に接続されたＤ
Ｃ電源１０８’によって、基板１０３に照射されるイオ
ンエネルギを制御できる。また、ターゲット１０２に接
続されたＤＣ電源１０８によって成膜速度を制御するこ
とができる。The spatial potential distribution inside the chamber at the time of plasma generation is as shown in FIG. 2, and the energy of irradiation ions (Ar ions) is plasma potential Vp and substrate bias V.
It is represented by the difference of s. That is, D connected to the substrate 103
The C power supply 108 'can control the ion energy with which the substrate 103 is irradiated. Further, the deposition rate can be controlled by the DC power source 108 connected to the target 102.
【００１９】ターゲット１０２の材料としては、リンを
４×１０19ｃｍ-3程度ドーピングしたＳｉを用いた。基
板１０３としてはＳｉを用いた。As the material of the target 102, Si doped with phosphorus at about 4 × 10 19 cm −3 was used. Si was used as the substrate 103.
【００２０】成膜原子１個当たりに照射されるイオンの
数を規格化照射量と定義し、この規格化照射量６、成膜
速度２０ｎｍ／ｍｉｎ、基板温度３５０℃の条件で、イ
オン照射エネルギを変えて成膜を行った結果の一例を図
３に示す。図が示すように、イオン照射エネルギが１０
ｅＶ程度以下ではキャリア密度が３×１０19ｃｍ-3程度
であり、ターゲットのキャリア密度と同程度である。し
かし、イオン照射エネルギが増加するにしたがいキャリ
ア密度は減少することが分かる。一方、形成された薄膜
の結晶性はイオン照射エネルギに関わらず良好であるこ
とが確認されている。The number of ions irradiated per film-forming atom is defined as a standardized irradiation amount, and the ion irradiation energy is set under the conditions of the standardized irradiation amount 6, the film forming rate of 20 nm / min, and the substrate temperature of 350 ° C. FIG. 3 shows an example of the result of film formation with different values. As shown in the figure, the ion irradiation energy is 10
Below about eV, the carrier density is about 3 × 10 19 cm −3, which is about the same as the target carrier density. However, it can be seen that the carrier density decreases as the ion irradiation energy increases. On the other hand, it has been confirmed that the crystallinity of the formed thin film is good regardless of the ion irradiation energy.
【００２１】次に、図４に示すようにイオン照射エネル
ギを１５ｅＶから６ｅＶにそして再び１５ｅＶと、５分
毎にステップ状に変化させて約３００ｎｍの成膜を行っ
た。Next, as shown in FIG. 4, the ion irradiation energy was changed from 15 eV to 6 eV and again to 15 eV in steps every 5 minutes to form a film having a thickness of about 300 nm.
【００２２】このようにして形成したＳｉ膜をリン酸中
で表面を陽極酸化して、この酸化膜を希フッ酸でエッチ
ングしシリコンを１０ｎｍ除去した後、四探針法でシー
ト抵抗を測定した。この工程を繰り返して得られたエッ
チング深さとシート抵抗の関係から式（１）を用いて深
さ方向の抵抗率の分布を求めた。 ρ ＝−Δｄ／ΔＧS （１） ここで ＧS＝１／ＲS ρ ：抵抗率 ｄ ：エッチング深さ ＲS ：シート抵抗 さらに、アービンカーブから抵抗率とキャリア濃度の対
応を得ることで、深さ方向のキャリア濃度分布を調べた
結果、図５に示すステップ状キャリア分布が得られた。The surface of the Si film thus formed was anodized in phosphoric acid, the oxide film was etched with dilute hydrofluoric acid to remove 10 nm of silicon, and then the sheet resistance was measured by the four-point probe method. . From the relationship between the etching depth and the sheet resistance obtained by repeating this process, the distribution of the resistivity in the depth direction was obtained using the formula (1). ρ = −Δd / ΔG S (1) Here, G S = 1 / R S ρ: resistivity d: etching depth R S : sheet resistance Furthermore, by obtaining the correspondence between the resistivity and the carrier concentration from the Irvin curve, As a result of examining the carrier concentration distribution in the depth direction, the stepwise carrier distribution shown in FIG. 5 was obtained.
【００２３】図４及び５から明らかなように、イオン照
射エネルギを時間的に変化させて成膜を行うことで、良
好な結晶性のままキャリア密度を変化させることが可能
となる。As is clear from FIGS. 4 and 5, the carrier density can be changed while maintaining good crystallinity by changing the ion irradiation energy with time to form a film.
【００２４】本実施例ではターゲット及び基板としてＳ
ｉを用いたが、ターゲット材としてＳｉ以外の半導体を
用いてもよいし、リン以外のドーパント（例えばＡｓや
Ｂなど）を用いてもよい。基板としてもＳｉ以外の半導
体、導体、絶縁体を用いてもよいことは言うまでもな
い。規格化照射量、成膜速度、基板温度についても本実
施例に限定されない。また、イオン照射エネルギについ
ても６ｅＶ、１５ｅＶ以外の場合でもよいし、ステップ
状の変化に限定されないことも言うまでもない。In this embodiment, S is used as the target and the substrate.
Although i is used, a semiconductor other than Si may be used as the target material, or a dopant other than phosphorus (for example, As or B) may be used. Needless to say, a semiconductor, conductor, or insulator other than Si may be used as the substrate. The normalized irradiation dose, film formation rate, and substrate temperature are not limited to those in this embodiment. It is needless to say that the ion irradiation energy may be other than 6 eV and 15 eV, and is not limited to the stepwise change.
【００２５】（実施例２）本実施例では、ＲＦ電力を変
えてプラズマ密度を変化させ、更にターゲットのバイア
スを制御して、図６に示すように、規格化照射量を１７
から６にそして再び１７に時間的に変化させて成膜を行
った。イオン照射エネルギは６ｅＶ一定とし、他の条件
は実施例１と同様とした。(Embodiment 2) In this embodiment, the RF power is changed to change the plasma density, and the target bias is controlled so that the normalized irradiation dose is 17 as shown in FIG.
The film was formed by changing the time from 6 to 17 and then again to 17. The ion irradiation energy was kept constant at 6 eV, and the other conditions were the same as in Example 1.
【００２６】実施例１と同様にして、膜厚方向のキャリ
ア濃度分布を求めた。結果を図７に示す。図７が示すよ
うに、規格化照射量を時間的に変えることにより実施例
１と同様にステップ状キャリア分布を得ることができ
た。In the same manner as in Example 1, the carrier concentration distribution in the film thickness direction was obtained. The results are shown in Fig. 7. As shown in FIG. 7, a stepwise carrier distribution could be obtained as in Example 1 by changing the normalized irradiation amount with time.
【００２７】なお、本実施例ではイオン照射エネルギは
変化させずに規格化照射量のみを制御したが、イオン照
射エネルギと規格化照射量とを、共に制御してもよいこ
とは言うまでもない。また、成膜速度を変えることで
も、実質的にイオンから成膜原子１個当たりに与えられ
る全エネルギを変えることができるため、成膜速度を時
間的に変化させて成膜を行っても膜厚方向のキャリア濃
度を変えることが可能である。In this embodiment, only the normalized irradiation dose was controlled without changing the ion irradiation energy, but it goes without saying that both the ion irradiation energy and the normalized irradiation dose may be controlled. In addition, by changing the film formation rate, the total energy given from one ion to one film formation atom can be changed substantially. Therefore, even if the film formation is performed by changing the film formation rate with time. It is possible to change the carrier concentration in the thickness direction.
【００２８】以上の実施例は、上述のＲＦ−ＤＣ結合プ
ラズマ装置を用いた場合であるが、二周波励起スパッタ
装置、直流放電スパッタ装置等種々のプラズマ装置を用
いてもよいことは言うまでもない。Although the above-mentioned embodiment uses the above-mentioned RF-DC coupled plasma apparatus, it goes without saying that various plasma apparatuses such as a dual-frequency excitation sputtering apparatus and a DC discharge sputtering apparatus may be used.
【００２９】[0029]
【発明の効果】本発明により、任意の深さに任意のキャ
リア濃度分布形態をもつ半導体を、低温で製造すること
が可能となり、その結果、高性能半導体装置を実現する
ことが可能となるAccording to the present invention, a semiconductor having an arbitrary carrier concentration distribution pattern at an arbitrary depth can be manufactured at a low temperature, and as a result, a high performance semiconductor device can be realized.
【図面の簡単な説明】[Brief description of drawings]
【図１】ＲＦ−ＤＣバイアスパッタ装置の概念図であ
る。FIG. 1 is a conceptual diagram of an RF-DC via sputtering device.
【図２】プラズマ中の空間電位分布を示す図である。FIG. 2 is a diagram showing a spatial potential distribution in plasma.
【図３】Ｓｉ薄膜のキャリア濃度と、イオンエネルギと
の関係を示すグラフである。FIG. 3 is a graph showing the relationship between the carrier concentration of a Si thin film and ion energy.
【図４】成膜中におけるイオンエネルギの時間的変化を
示すグラフである。FIG. 4 is a graph showing a temporal change in ion energy during film formation.
【図５】形成した薄膜の表面からの深さとキャリア濃度
との関係を示したグラフである。FIG. 5 is a graph showing the relationship between the depth from the surface of the formed thin film and the carrier concentration.
【図６】成膜中における規格化照射量の時間的変化を示
すグラフである。FIG. 6 is a graph showing a temporal change in normalized irradiation dose during film formation.
【図７】形成した薄膜の表面からの深さとキャリア濃度
との関係を示したグラフである。FIG. 7 is a graph showing the relationship between the depth from the surface of the formed thin film and the carrier concentration.
【図８】イオン注入後及び熱処理後の不純物分布を示し
たグラフである。FIG. 8 is a graph showing an impurity distribution after ion implantation and after heat treatment.
【図９】熱拡散による不純物分布を示したグラフであ
る。FIG. 9 is a graph showing an impurity distribution due to thermal diffusion.
１０１ チャンバ、 １０２ ターゲット、 １０３ 基板、 １０４ ガス導入口、 １０５ 真空排気系、 １０６ マッチング回路、 １０７，１０７’ ローパスフィルタ、 １０８，１０８’ ＤＣ電源、 １０９ ＲＦ電源。 101 chamber, 102 target, 103 substrate, 104 gas introduction port, 105 vacuum exhaust system, 106 matching circuit, 107,107 'low pass filter, 108,108' DC power supply, 109 RF power supply.
Claims (4)
含む半導体層を用いた半導体装置において、前記半導体
層中の前記不純物の濃度と、前記不純物より供給される
キャリアの濃度との比が、前記半導体層の膜厚方向に変
化していることを特徴とする半導体装置。1. In a semiconductor device using a semiconductor layer containing a predetermined impurity deposited and grown on a substrate, the ratio of the concentration of the impurity in the semiconductor layer and the concentration of carriers supplied from the impurity is A semiconductor device, wherein the semiconductor layer is changed in a film thickness direction.
堆積成長させる方法において、前記半導体層の成長表面
に対し連続的にイオン照射を施すとともに、前記イオン
照射のイオンエネルギもしくはイオン照射量もしくはそ
の両方を、時間的に変化させることにより、前記半導体
層中の前記不純物の濃度と、前記不純物より供給される
キャリアの濃度との比を、前記半導体層の膜厚方向に変
化させることを特徴とする半導体装置の製造方法。2. A method of depositing and growing a semiconductor layer containing a predetermined impurity on a substrate, wherein the growth surface of the semiconductor layer is continuously irradiated with ions, and the ion energy of the ion irradiation or the ion irradiation amount or By changing both of them with time, the ratio of the concentration of the impurities in the semiconductor layer to the concentration of carriers supplied from the impurities is changed in the film thickness direction of the semiconductor layer. And a method for manufacturing a semiconductor device.
あることを特徴とする請求項２に記載の半導体装置の製
造方法。3. The method of manufacturing a semiconductor device according to claim 2, wherein the ion energy is 0 to 30 eV.
たり１〜５０であることを特徴とする請求項１または２
に記載の半導体装置の製造方法。4. The ion irradiation dose is 1 to 50 per atom of deposited atoms, according to claim 1 or 2.
A method of manufacturing a semiconductor device according to item 1.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14052693A JPH06349746A (en) | 1993-06-11 | 1993-06-11 | Semiconductor device and its manufacture |
| PCT/JP1994/000945 WO1994029896A1 (en) | 1993-06-11 | 1994-06-10 | Semiconductor device and production method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14052693A JPH06349746A (en) | 1993-06-11 | 1993-06-11 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06349746A true JPH06349746A (en) | 1994-12-22 |
Family
ID=15270721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14052693A Pending JPH06349746A (en) | 1993-06-11 | 1993-06-11 | Semiconductor device and its manufacture |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH06349746A (en) |
| WO (1) | WO1994029896A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6365009B1 (en) | 1997-06-17 | 2002-04-02 | Anelva Corporation | Combined RF-DC magnetron sputtering method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2758948B2 (en) * | 1989-12-15 | 1998-05-28 | キヤノン株式会社 | Thin film formation method |
| JPH03250622A (en) * | 1990-02-28 | 1991-11-08 | Canon Inc | Forming method for thin semiconductor film |
-
1993
- 1993-06-11 JP JP14052693A patent/JPH06349746A/en active Pending
-
1994
- 1994-06-10 WO PCT/JP1994/000945 patent/WO1994029896A1/en active Application Filing
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6365009B1 (en) | 1997-06-17 | 2002-04-02 | Anelva Corporation | Combined RF-DC magnetron sputtering method |
Also Published As
| Publication number | Publication date |
|---|---|
| WO1994029896A1 (en) | 1994-12-22 |
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