JPH06349287A - Flag data memory circuit - Google Patents

Abstract

PURPOSE:To relax the restriction on the writing amount required for bringing an EPROM into writing state when the EPROM cell comprising a writing transistor and a reading transistor, sharing the floating gate, is used as a flag data memory element. CONSTITUTION:An EPROM cell mounted on a single chip microcomputer and having a laminated gate structure of a floating gate FC and a control gate CG comprises an enhancement writing transistor T3 and a depletion reading transistor T4 sharing the floating gate. The flag data memory circuit is provided with a read/write control circuit for applying a writing voltage to the drain and control gate of the writing transistor T3 when a data is written in the EPROM whereas applying a clamp voltage to the drain of the read transistor T4 and the ground potential to the control gate thereof when a data is read out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flag data storage circuit formed in a one-chip microcomputer, and more particularly to a flag data storage circuit using a transistor having a stacked gate structure as a nonvolatile memory cell.

[0002]

2. Description of the Related Art A one-chip microcomputer (hereinafter,
A one-chip microcomputer) is equipped with a flag data storage circuit for storing flag data for function selection.

This flag data storage circuit must be constructed so that the stored information is not lost when the operating power of the one-chip microcomputer is turned off or when any stress is applied to the one-chip microcomputer. It is often constructed using non-volatile memory cells such as ultraviolet erasable / rewritable ROM) cells.

FIG. 5 shows a conventional flag data storage circuit. In this circuit, 10 is FLOTOX (Fl
EPROM consisting of otaing gate Tunnel Oxide type cell
It is a cell. The EPROM cell 10 has an N-channel for data storage having a gate structure in which a source of an N-channel MOS transistor for selection gate (hereinafter referred to as a selection transistor) 11 and a floating gate and a control gate are stacked.
The drain of a channel MOS transistor (hereinafter referred to as a cell transistor) 12 is connected, and the source of the cell transistor 12 is connected to a ground potential (Vss) node.

Reference numeral 13 is a Vpp / VCC switching node to which a high potential write voltage Vpp is applied during data writing (programming) and a normal power supply potential VCC is applied during data reading. An N channel MOS transistor (hereinafter referred to as a write transistor) 14 for writing data is connected between the Vpp / VCC switching node and the drain of the selection transistor 11, and the gate of the write transistor 14 is connected. The write data / DATA is given to.

Between the Vcc node to which the normal power supply potential Vcc is applied and the drain of the selection transistor 11,
A normally-on type P whose gate is connected to the Vss node
Load transistor 16 for reading, which is a channel MOS transistor, and N-channel MO for clamping potential
The S transistor 17 is connected in series.

The potential clamping transistor 17 is
The drain potential of the cell transistor 12 at the time of reading is clamped, a bias potential Vbias is applied to the gate, and the connection node between the drain and the read load transistor 16 is the sense amplifier 1.
8 input nodes.

In this flag data storage circuit, a high voltage Vpp is applied to the gate of the selection transistor 11 and the control gate of the cell transistor 12 at the time of writing (programming) data. As a result, the selection transistor 11 is turned on, and when the high voltage Vpp is applied from the Vpp / VCC switching node 13 to the drain of the cell transistor 12 via the write transistor 14 and the selection transistor 11, the drain and source of the cell transistor 12 are connected. An on-current flows and hot electron and hot hole pairs are generated near the drain. The holes flow to the substrate as substrate current, but
By injecting electrons into the floating gate, the threshold value seen from the control gate rises and the writing is completed.

At the time of reading data, a read clamp voltage (for example, 1
V) is applied, and a read voltage is applied to the gate of the selection transistor 11 and the control gate of the cell transistor 12. As a result, the selection transistor 11 is turned on, and the cell transistor 12 is supplied with a cell current determined according to its threshold voltage (that is, corresponding to the written state / non-written state), and its on / off state (of the stored data). "1" / "0") is detected.

By the way, since the EPROM cell 10 used in the flag data storage circuit of FIG. 5 uses one cell transistor 12 for both writing and reading, the writing characteristic and the reading characteristic should be optimized. Is difficult. For example, in order to maintain the write characteristic and the punch-through breakdown voltage at the time of writing, the threshold voltage V of the cell transistor 12
It was difficult to reduce th, and it was difficult to reduce the read voltage.

In order to read at a low voltage, there is a method of applying a boosted potential to the control gate of the cell transistor 12. However, this method requires a booster circuit and a limiter circuit for preventing the boosted potential from becoming too large in a region where the power supply voltage Vcc is high. Further, the write voltage Vpp and the boosted voltage are required. A power supply switching circuit for switching the potential and applying it to the control gate of the cell transistor is also required. This causes a problem that the circuit configuration becomes complicated and the pattern area increases.

In addition, when the booster circuit as described above is used, it takes a long time for the boosted potential to stabilize when the power is turned on, so that the time for reading the data from the flag data storage circuit becomes long. Considering that it is necessary to read the flag data immediately when the power is turned on, it is inappropriate to use the booster circuit as described above in the flag data storage circuit.

On the other hand, a technique using a writing transistor and a reading transistor sharing a floating gate as an EPROM cell is an ISSCC 85 DIGEST OF TECHNICAL.
PAPERS p.162-163, S.Pathak et al., "A 25ns 16K CMOS PR
OM using a 4-Transistor Cell ".

In this EPROM cell, as shown in FIG. 6, one EPROM cell is a writing transistor 12.
a and a read transistor 12b,
Both transistors share the floating gate 20. The write transistor 14 and the first selection transistor 11a are connected in series between the Vpp node and the write transistor 12a, and the read load transistor 16 is provided between the Vcc node and the read transistor 12b. The potential clamping transistor 17 and the second selection transistor 11b are connected in series.

The writing transistor 12a and the reading transistor 12b are both enhancement type MOS transistors. The control gates 21 of the both transistors 12a and 12b have a writing voltage Vpp during writing and a reading voltage Vcc during reading. Is applied. Then, at the time of writing, the writing transistor 12a
The threshold value of the read transistor 12b is shifted by the electrons injected into the floating gate 20 of the above.

In this EPROM cell, the write characteristic and the read characteristic can be easily optimized, and the threshold voltage Vth of the read transistor 12b can be lowered. There are some problems to mention.

That is, when the writing amount of the writing transistor 12a during writing is small and the threshold shift amount of the reading transistor 12b is not sufficient, it is applied to the control gate 21 of the reading transistor 12b during reading. When the read voltage is high, a current flows through the read transistor 12b which should be in the off state, and in the worst case, the read data is inverted, which causes a malfunction.

As a specific example, the writing transistor 12
It is assumed that the initial value of the threshold value of a (the threshold value in the erased state) is 2V, the initial value of the threshold value of the reading transistor 12b is 1V, and the threshold value of each is shifted by 3V by writing. Then,
The threshold value of the writing transistor 12a after writing is 5V,
Since the threshold value of the read transistor 12b is 4V, the read transistor 12b is turned on when the read voltage applied to the control gate 21 of the read transistor 12b is 5V, for example.

If the write amount is sufficiently large (threshold shift amount is sufficiently large) in order to avoid such a malfunction, the amount of decrease in the cell threshold during long-term use becomes large, so that the data retention (Data retention) reduces reliability.

[0020]

As described above, the conventional flag data storage circuit is composed of a writing transistor and a reading transistor which share a floating gate.
When the PROM cell is used as a memory element, if the threshold voltage of the read transistor is lowered, there is a problem that the write amount in the initial state for bringing the EPROM cell into the write state must be made sufficiently large.

The present invention has been made to solve the above problems, and when a non-volatile memory cell composed of a writing transistor and a reading transistor sharing a floating gate is used as a flag data storage element, the non-volatile An object of the present invention is to provide a flag data storage circuit that can relax restrictions on the amount of programming in the initial state for bringing a memory cell into the programming state.

[0022]

The present invention is mounted on a one-chip microcomputer and has a gate structure in which a floating gate and a control gate are laminated, and an enhancement type write transistor and a read transistor sharing the floating gate. A non-volatile memory cell including a depletion type transistor for storing flag data for selecting a function of the one-chip microcomputer, and a drain and a control gate of the writing transistor when writing data to the non-volatile memory cell. Write / read control for applying a write voltage to the non-volatile memory cell and applying a read clamp voltage to the drain of the read transistor and applying a ground potential to its control gate at the time of reading data from the nonvolatile memory cell. Characterized by comprising the road.

[0023]

[Effect] Even if the write amount in the initial state for bringing the cell into the written state is not made sufficiently large, normal reading can be performed by applying the ground potential to the control gate of the reading transistor of the cell. It becomes possible to operate stably in a wide power supply voltage range. Therefore, an excessive amount of writing becomes unnecessary, a margin for data retention is expanded, and reliability is improved.

[0024]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows an example of a flag data storage circuit according to an embodiment of the present invention. This flag data storage circuit is mounted in a one-chip microcomputer, and an EPROM cell for a flag data storage element and a write / read operation for writing / reading flag data to / from this EPROM cell.
And a read control circuit.

The EPROM cell is divided into a writing transistor T3 and a reading transistor T4. The above-mentioned writing transistor T3 is subjected to channel implantation (ion implantation) so as to be an enhancement type suitable for writing characteristics, and the reading transistor T4 is subjected to a channel implantation so as to be a depletion type which is not too deep. Plantation is taking place.

That is, the threshold values of the write transistor T3 and the read transistor T4 are controlled by implanting ions of different concentrations into the respective channel portions, and the read transistor T3 and the read transistor T4 are controlled.
The threshold value of 4 is set lower than the threshold value of the writing transistor T3.

The writing transistor T3 and the reading transistor T4 share the floating gate FG, and the control gate CG is also formed in common (or may be separate), and their sources are ground potential Vss.
It is connected to the.

Between the Vpp node and the drain of the write transistor T3, an N-channel enhancement type transistor T5 for write control and an N-channel enhancement type transistor T6 for write load are provided.
Are connected in series.

The output voltage of the first level shifter circuit 1 is applied to the gate of the write control transistor T5. The first level shifter circuit 1 is supplied with the output signal of the two-input AND gate circuit 3 to which the write data (flag data) / DATA and the write control signal PGM are input, the high voltage Vpp at the time of writing, and the ground potential Vss at other times.
Is output.

The output voltage of the second level shifter circuit 2 is applied to the gate of the write load transistor T6, the write transistor T3 and the control gate CG of the read transistor T4. The second level shifter circuit 2 outputs the high voltage Vpp during writing and the ground potential Vss during reading.

Further, between the Vcc node and the drain of the read transistor T4, a read load P is provided.
A channel enhancement type transistor T7 and a potential clamping N channel intrinsic type transistor T8 are connected in series.

The output signal of the two-input OR gate circuit 5 to which the reset signal / RESET and the write control signal PGM are input is given to the gate of the read load transistor T7. A predetermined bias voltage is applied from the bias circuit 6 to the gate of the potential clamping transistor T8.

Further, the input node of the clocked inverter circuit 7 whose operation is controlled by the reset signal / RESET is connected to the series connection node of the read load transistor T7 and the potential clamp transistor T8. The latch circuit 8 is connected to the output side of the clocked inverter circuit 7.

2 (a) and 2 (b) show the EP in FIG.
An example of characteristics of the writing transistor T3 and the reading transistor T4 of the ROM cell 1 is shown. Next, the operation of the flag data storage circuit of FIG. 1 will be described with reference to FIG.
This will be described with reference to the characteristic diagrams of (a) and (b).

At the time of writing to the EPROM cell, the write data / DATA and the write control signal PGM are "H".
And the output of the two-input AND gate circuit 3 becomes "H" level. As a result, the first level shifter circuit 1 outputs the high voltage Vpp and applies it to the gate of the writing control transistor T5, so that the writing control transistor T5 is turned on.

At this time, the second level shifter circuit 2 is
Receiving the "H" level write control signal PGM, the high voltage V
pp is output and applied to the gate of the write load transistor T6 and the control gate CG of the cell. As a result, the write load transistor T6 is controlled to be in the ON state, and the drain and control gate C of the write transistor T3 are controlled.
Since a high voltage is applied to G, the writing transistor T
Write to 3.

At this time, the two-input OR gate circuit 5 is
Since the "H" level write control signal PGM is received and the "H" level output signal is applied to the gate of the read load transistor T7, the read load transistor T7 is controlled to the off state. As a result, the drain of the read transistor T4 is in an open state, and erroneous writing is prevented even if the high voltage Vpp is applied to the control gate CG of the read transistor T4 at this time.

Threshold value Vth of the writing transistor T3
Has an initial value (threshold in erased state) of, for example, 2V, and the threshold value Vth of the read transistor T4 has an initial value of, for example, -2V.
If each threshold is shifted by 3V during writing,
After writing, the threshold value of the writing transistor T3 becomes 5V, and the threshold value of the reading transistor T4 becomes 1V.

On the other hand, at the time of reading from the EPROM cell 1, the write control signal PGM becomes "L" level, and the output of the two-input AND gate circuit 3 becomes "L" level. As a result, the first level shifter circuit 1
Write control transistor T5 that outputs the ground potential Vss
Applied to the gate of the write control transistor T
5 is controlled to the off state.

At this time, the second level shifter circuit 2
Upon receiving the "L" level write control signal PGM, the ground potential Vss is output and applied to the gate of the write load transistor T6 and the control gate CG of the cell. This allows
The write load transistor T6 is controlled to the off state,
The drain of the writing transistor T3 is opened.

At this time, the two-input OR gate circuit 5 is
Since the "L" level write control signal PGM is received and the "L" level output signal is applied to the gate of the read load transistor T7, the read load transistor T7 is applied.
Is controlled to the ON state. Also, the potential clamping transistor T8 is controlled to be in the ON state.

As a result, the read transistor T4
The data is read out with a clamp voltage of about 1 V applied to the drain and the ground potential Vss applied to the control gate CG.

Then, the read transistor T4
The data (flag data) read from is latched by the latch circuit 8 via the clocked inverter circuit 7 which operates at the timing of the reset signal / RESET.

In other words, when the reset signal / RESET is supplied to the flag data storage circuit at the time of resetting the one-chip microcomputer, the flag data is read at the timing of the reset signal / RESET and used for the mode setting of the one-chip microcomputer. Will be possible.

The two-input OR gate circuit 5 is
Even when the "L" level reset signal / RESET is supplied, the "L" level output signal is applied to the gate of the read load transistor T7 to control the read load transistor T7 to the ON state.

In the read operation as described above, E
If the PROM cell is in the erased state (non-written state), the threshold value of the read transistor T4 is negative (-2 in this example).
V), and when the ground potential Vss is applied to its control gate CG, the read transistor T4 is turned on and a cell current flows.

On the other hand, when the EPROM cell is in the written state and the threshold value of the read transistor T4 exceeds 0V (1V in this example), the ground potential Vss is applied to its control gate CG. When read, the read transistor T4 is turned off and no cell current flows.

Therefore, according to the flag data storage circuit of the above-described embodiment, the transistor E for writing and the transistor for reading T4 sharing the floating gate CG are formed.
By lowering the threshold voltage Vth of the read transistor T4 of the PROM cell and applying the ground potential Vss to the control gate CG of the cell at the time of reading to read, the write amount in the initial state for bringing the cell into the written state is sufficiently increased. Even if the size is not increased, malfunction of reading does not occur, stable operation in a wide power supply voltage range becomes possible, data retention becomes advantageous, and cell reliability is improved.

If the drain potential of the read transistor T4 rises excessively, the electric field between the floating gate and the drain becomes strong, and the electrons accumulated in the floating gate escape through the gate oxide film of the read transistor T4. There is a risk. However, since the potential clamping transistor T8 operates so as to clamp the drain potential of the read transistor T4, it is possible to prevent the drain potential of the read transistor T4 from rising too much and the stress becoming strong as described above. There is.

The EPROM cell used in the flag data storage circuit of the above embodiment has a pattern area about twice as large as that of the EPROM cell used in the conventional flag data storage circuit shown in FIG. . However, EPRO
Since the pattern area of the peripheral circuit of the EPROM cell is considerably larger than the pattern area of the M cell, the pattern area of the entire flag data storage circuit in the above embodiment does not increase so much as compared with the conventional example.

FIG. 3 is a circuit diagram showing a modification of part of the flag data storage circuit of FIG. This flag data storage circuit is different from the flag data storage circuit of FIG. 1 in that the read load transistor T7 is replaced by a P for precharge.
A channel enhancement type transistor T9 is connected, an N channel enhancement type transistor T10 for discharging is inserted between the source of the reading transistor T4 and the Vss node, and the precharging transistor T7 and the discharging transistor T10 are complemented with each other. The difference is that a precharge signal / PR for controlling the switch is supplied, and the other parts are the same, so the same reference numerals as in FIG. 1 are given.

In this flag data storage circuit, the discharge transistor T10 is controlled to be in the off state during the precharge period when writing and reading the flag data and is turned on during the precharge period when reading the flag data. Controlled by the state. As a result, basically, the same write / read operation as that of the flag data storage circuit of FIG. 1 is possible.

FIG. 4 is a circuit diagram showing another modification of a part of the flag data storage circuit of FIG. This flag data storage circuit is different from the flag data storage circuit of FIG.
The sources of the write transistor T3 and the source of the read transistor T4 are connected in common, and the discharge transistor T10 is inserted between this common connection node and the Vss node, but otherwise the same. Therefore, the same reference numerals as in FIG. 3 are attached.

In this flag data storage circuit, the discharge transistor T10 is controlled to be off during the precharge period when reading the flag data, and is turned on during the period after precharge during the reading and during writing the flag data. By being controlled, basically the same write / read operation as that of the flag data storage circuit of FIG. 1 is possible.

[0055]

As described above, according to the present invention, when a nonvolatile memory cell composed of a writing transistor and a reading transistor sharing a floating gate is used as a flag data storage element, the nonvolatile memory cell is programmed. Flag data storage of a one-chip microcomputer capable of relaxing restrictions in determining the amount of write in the initial state for achieving the standby state so as to achieve both prevention of standby current and prevention of deterioration of reliability due to data retention A circuit can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a flag data storage circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of characteristics of a writing transistor and a reading transistor of the EPROM cell in FIG.

FIG. 3 is a circuit diagram showing a modification of a part of the flag data storage circuit of FIG.

FIG. 4 is a circuit diagram showing another modification of a part of the flag data storage circuit of FIG.

FIG. 5 is a circuit diagram showing an example of a conventional flag data storage circuit.

FIG. 6 is a circuit diagram showing another example of a conventional flag data storage circuit.

[Explanation of symbols]

1 ... First level shifter circuit, 2 ... Second level shifter circuit, 3 ... Two-input AND gate circuit, 5 ... Two-input OR gate circuit, 6 ... Bias circuit, 7 ... Clocked inverter circuit, 8 ... Latch circuit, FG ... Floating Gate, CG ... Control gate, T3 ... Write transistor, T4 ... Read transistor, T5 ... Write control transistor,
T6 ... Write load transistor, T7 ... Read load transistor, T8 ... Potential clamp transistor,
T9 ... Precharge transistor, T10 ... Discharge transistor.

Claims (5)

[Claims] 1. A one-chip microcomputer, which has a gate structure in which a floating gate and a control gate are stacked, and comprises an enhancement type write transistor and a read depletion type transistor sharing the floating gate, A nonvolatile memory cell for storing flag data for selecting a function of a one-chip microcomputer, and a write voltage is applied to a drain and a control gate of the write transistor when writing data to the nonvolatile memory cell, When data is read from the non-volatile memory cell, a write / read control circuit for controlling the drain of the read transistor to apply a read clamp voltage and a ground potential to its control gate is provided. Flag data storage circuit to. 2. The flag data storage circuit according to claim 1, wherein the write / read control circuit, during the write operation,
A flag data storage circuit, characterized in that the drain of the reading transistor is opened, and the drain of the writing transistor is controlled to be opened during the reading. 3. The flag data storage circuit according to claim 1, wherein an enhancement-type MOS transistor for read load and a potential clamp connected in series between a power supply potential node and the drain of the read transistor. A MOS transistor, a gate circuit that controls the read load transistor to be in an ON state during the reset operation and the read operation of the one-chip microcomputer, and is connected to a series connection node of the read load transistor and the potential clamping transistor. A flag data storage circuit further comprising a circuit for latching data read to the serial connection node during the reset operation. 4. The flag data storage circuit according to claim 1, wherein an enhancement-type MOS transistor for precharge and a potential clamp connected in series between a power supply potential node and the drain of the read transistor. It further comprises a MOS transistor, and an enhancement type MOS transistor for discharging, which is connected between the source of the reading transistor and a ground potential node and is switch-controlled complementarily to the precharging transistor. Flag data storage circuit. 5. The flag data storage circuit according to claim 3, wherein the potential clamping MOS transistor is an N-channel intrinsic type.