JPH06348774A - Logic simulation result editor - Google Patents

Abstract

PURPOSE:To provide a logic simulation result editor in which the test time of an LSI can be shortened, and the developmental cost of a program for Hiz pattern in accordance with inidvidual test can be reduced, a pin multiplex waveform can be edited and the effective use of test pattern storage capacity can be attained by compressing the same test pattern. CONSTITUTION:Data representing the simulation result of a logic circuit stored in a logic simulation result file 11 and control data required for the edit of the test pattern stored in a control data file 12 are inputted, and a time of the most delayed signal change in respective period is recognized in each period of a logic simulation result to edit the data of an intermediate test pattern to generate test programs in accordance with testers 17-1, 17-2, 17-3,..., and a time until prescribed time included in the control data elapses from recognized time is found as the period of the intermediate test pattern in accordance with each period of the logic simulation result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation result editing device for a test program generating device for a logic circuit such as an LSI chip. More specifically, the logic circuit is actually tested on a tester based on the logic simulation result. The present invention relates to a logic simulation result editing device of a test program generation device that generates a test program necessary for performing.

[0002]

2. Description of the Related Art FIG. 8 is a schematic diagram showing the structure of a general test program generating apparatus. In FIG. 8, reference numerals
Reference numeral 11 is a logic simulation result file, which stores data as a result of logic simulation of the logic circuit to be tested. Reference numeral 12 is a control data file, which stores information such as a signal line name necessary for editing the test pattern, its input, output, pin class indicating distinction of bidirectional signals, and test period, that is, control data. ing.

Reference numeral 13 is a logic simulation result editing device, which reads data from the logic simulation result file 11 and the control data file 12 described above, and generates an intermediate test pattern independent of the tester. The intermediate test pattern generated by the logic simulation result editing device 13 is temporarily stored in the intermediate test pattern file 14.

Reference numeral 15 is a translator, which converts the intermediate test pattern stored in the intermediate test pattern file 14 into a test program corresponding to each tester. The test program created in this way is stored in the test program file 16 and is output for testing by the corresponding testers 17-1, 17-2, 17-3, ... As necessary.

By the way, as the test cycle of the intermediate test pattern generated by the logic simulation result editing apparatus of the conventional test program generating apparatus, the test cycle used when performing the logic simulation is directly edited as the test cycle of the intermediate test pattern. And output to the intermediate test pattern file 14. Therefore, in the actual test, there is a sufficient time margin after the output signal finally stabilizes in each test cycle. Therefore, if an actual test is performed on the tester using such a test cycle, it means that the test is wasted.

A detailed description will be given below with reference to the timing chart of FIG. 9 showing the result of the logic simulation. The shortest test cycle that can be tested on the tester is sufficient as the test cycle actually required when testing the logic circuit on the tester. By the way, the shortest test cycle that can be tested on the tester is, as shown in FIG. 9, the maximum delay time 2a when the time to the latest signal change in each test cycle 2d in the logic simulation is Margin value from that point until the signal stabilizes
It is a period 2e until 2b and the dead zone value 2c in the latter half of the tester cycle elapse.

Therefore, the test cycle in simulation
Although it is possible to actually perform a sufficient test in the period indicated by reference numeral 2e in FIG. 9 which is shorter than 2d, conventionally, the test period 2d in the logic simulation is directly used as the test period in the tester as the test period. Since the editing device 13 was generating the test pattern, the test required extra time.

A high impedance state (hereinafter, Hi
When testing a z pattern) on the tester, it is necessary to lengthen the time to compare on the tester as compared with the case of testing the logic value (high level, low level) of the signal. Therefore, conventionally, when the translator 15 generates a test program for each tester, the test cycle including the Hiz pattern is extended. However, if such a measure is taken, it is necessary to develop a program for each translator 15 to perform such processing, which has been a factor of increasing the development cost.

Furthermore, since the multi-clock waveform and the pin multiplex waveform could not be edited by the logic simulation result editing device 13 in the past, the number of test patterns increases and the capacity of the intermediate test pattern file 14 is effectively used. The result is hindering. Both of these waveforms can apply a plurality of phases of clocks in one cycle, which is effective for reducing the test pattern.

Further, when the same test pattern is continuous, the number of test patterns is large because all the test patterns are conventionally output even if the patterns are the same, and there is a problem similar to the above. .

[0011]

As described above, in the conventional logic simulation result editing device of the test program generating device, the test period in the logic simulation is directly used as the test period in the tester, so that the test time is unnecessarily long. Moreover, it is necessary to develop a program for each tester of the translator to test the HiZ state on the tester, and the number of test patterns increases because the multi-clock waveform and pin multiplex waveform cannot be edited. Further, even when the same test pattern is continuous, all the test patterns are output, so that there are various problems such as an increase in the number of test patterns.

The present invention has been made in view of the above circumstances, and shortens the LSI test time, reduces the development cost of a program for a Hiz pattern corresponding to each tester, multi-clock waveform, pin multiplex. It is an object of the present invention to provide a logic simulation result editing device that enables editing of waveforms and efficient use of test pattern storage capacity by compressing the same test pattern.

[0013]

A first aspect of the logic simulation result editing apparatus according to the present invention inputs data of a logic simulation result of a logic circuit and control data necessary for editing a test pattern. In order to edit the data of the intermediate test pattern for generating the test program corresponding to each tester, for each cycle of the logic simulation result, a means for recognizing the point of the slowest signal change in each cycle, and And means for obtaining the period of the intermediate test pattern corresponding to each period of the logic simulation result from the time point recognized by the means to the time point when a predetermined time contained in the control data elapses.

A second aspect of the invention is to provide a means for recognizing the latest signal change time point in each cycle of the logic simulation result, and the latest time point for all cycles of the time points recognized by this means. And means for obtaining, as a cycle of the intermediate test pattern common to all cycles of the logic simulation result, from a time point selected by this means to a time point when a predetermined time included in the control data elapses. There is.

According to a third aspect of the present invention, a means for recognizing whether or not each of the cycles of the logic simulation result is in a high impedance state, and a cycle of an intermediate test pattern of a cycle recognized as a high impedance state by this means. And a means for editing an extended test pattern as an intermediate test pattern in accordance with data of a predetermined time included in the control data.

According to a fourth aspect of the present invention, means for recognizing a signal change time point in each cycle of the logic simulation result,
A means for editing the multi-clock waveform as an intermediate test pattern based on the signal change point recognized by this means and the pin class indicating the input / output of the signal line and the bidirectional signal included in the control data; Is equipped with.

According to a fifth aspect of the invention, means for recognizing a time point of signal change for each cycle of the logic simulation result,
Means for editing the multiplex waveform as an intermediate test pattern based on the signal change time recognized by this means and the pin class indicating the input / output of the signal line and the bidirectional signal included in the control data. Is equipped with.

According to a sixth aspect of the present invention, there is provided a first means for storing a pattern for two cycles of the logic simulation result and a second means for comparing the patterns for two cycles stored in the first means. When the comparison result by the second means is the same, the third means for saving the pattern of the next cycle in place of the newer pattern saved by the first means, and the second means Fourth means for storing the newer pattern in place of the older one stored by the first means when the comparison results do not match, and the older one stored by the first means Is edited as an intermediate test pattern.

[0019]

In the first aspect of the logic simulation result editing apparatus according to the present invention, for each cycle of the logic simulation result, the time point of the latest signal change in each cycle is recognized, and from that time point, a predetermined value included in the control data is recognized. Up to the point in time at which the time elapses is obtained as the cycle of the intermediate test pattern corresponding to each cycle of the logic simulation result.

In the second aspect of the invention, for each cycle of the logic simulation result, the latest signal change time point in each cycle is recognized, and the latest time point in all cycles is selected. From the time point to the time point when a predetermined time included in the control data elapses, the cycle of the intermediate test pattern common to all cycles of the logic simulation result is obtained.

In the third aspect of the invention, for each cycle of the logic simulation result, whether or not the high impedance state is recognized is recognized, and the cycle of the intermediate test pattern of the cycle recognized as the high impedance state is included in the control data. The extended pattern is edited as an intermediate test pattern according to the data of a predetermined time.

In the fourth aspect of the invention, the signal change time point is recognized for each cycle of the logic simulation result, and the recognized signal change time point and the input / output and bidirectional signal of the signal line included in the control data are recognized. The multi-clock waveform is edited as an intermediate test pattern based on the pin class indicating another.

In the fifth aspect of the present invention, the signal change time point is recognized for each cycle of the logic simulation result, and the recognized signal change time point and the input / output of the signal line and the bidirectional signal included in the control data are recognized. The multiplexed waveform is edited as an intermediate test pattern based on the pin class indicating another.

In the sixth invention, the pattern for two cycles of the logic simulation result is stored by the first means,
The stored patterns for two cycles are compared, and when the comparison results match, the pattern of the next cycle is stored in place of the newer pattern stored by the first means,
When the comparison result does not match, the new pattern is stored in place of the old pattern stored by the first means, and the old pattern is edited as an intermediate test pattern.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments thereof. The logic simulation result editing device of the present invention is configured as a part of the conventional test program generating device shown in FIG. FIG. 1 is a flowchart showing the operation procedure of the first invention of the logic simulation result editing apparatus according to the present invention. First, the logic simulation result editing device 13 reads and saves the margin value, the dead zone value, and the test cycle from the control data stored in the control data file 12 (step S11).

Next, the logic simulation result editing device 13
Inputs the data of the logic simulation result from the logic simulation result file 11 for each cycle, and obtains the latest signal change time in the cycle, that is, the maximum delay time 2a (step S12).

Then, the logic simulation result editing device 13 adds the margin value 2b and the dead zone value 2c to the time 2a obtained in step S12 to calculate the shortest testable period 2e on the tester (step S13). , The result is output to the intermediate test pattern file 14 and stored (step
S14). The above processing is the logical simulation result file
Performed for all cycles of the data stored in 11
(Step S15).

FIG. 2 is a flow chart showing the operation procedure of the second invention of the logic simulation result editing apparatus according to the present invention. First, the logic simulation result editing device
13 reads and saves the margin value, dead zone value, and test period from the control data stored in the control data file 12 (step S21).

Next, the logic simulation result editing device 13
Inputs the data of the logic simulation result from the logic simulation result file 11 for each cycle, and obtains the latest signal change time in the cycle, that is, the maximum delay time 2a (step S22).

Then, the logic simulation result editing device 13 compares the maximum delay time 2a stored in the past with the value obtained this time, and stores the larger one (step S2
3).

The logic simulation result editing device 13 repeats the above processing for all cycles (step S24), adds the margin value 2b and the dead zone value 2c to the finally stored maximum delay time 2a, and then the tester The shortest cycle 2e common to all cycles that can be tested above is calculated (step S25), and the result is output and stored in the intermediate test pattern file 14 (step S26).

FIG. 3 is a timing chart showing the result of logic simulation of the three signal lines 8a, 8b, 8c. In the timing chart shown in FIG. 3, since the signal change timing of the signal line 8a becomes the maximum delay time 2a in the first cycle, a value obtained by further adding the margin value 2b and the dead zone value 2c from this time point. Is the shortest test cycle 2e of the first cycle.

FIG. 4 is a flow chart showing the operation procedure of the third invention of the logic simulation result editing apparatus according to the present invention. The type of test pattern that can be recognized by the logic simulation result editing device 13 from the logic simulation result is one of "1", "0", "X", and "Z".

First, the logic simulation result editing device 13
Converts the signal value of each cycle of the logical simulation result into a test pattern (step S31). At this time, the logic simulation result editing device 13 recognizes the cycle in which the "Z" pattern, which means the Hiz pattern, is edited as the test pattern (step S32), and the test cycle of the cycle in which the Hiz pattern exists is defined as the control data file 12 Edit according to the control data stored in (Step S3
3). Finally, the logic simulation result editing device 13 outputs the obtained test cycle to the intermediate test pattern file 14 and stores it (step S34).

In the example shown in the timing chart of FIG. 3, since the "Z" pattern continues to the end of each of the third and fourth periods of the signal line 8c, the logic simulation result editing device is provided. 13 outputs by extending the test cycle of those cycles.

FIG. 5 is a waveform diagram showing a multi-clock waveform. The fourth invention of the logic simulation result editing apparatus of the present invention edits a multi-clock waveform as shown in FIG. 5, and the fifth invention of the present invention edits a pin multiplex waveform.

Hereinafter, description will be made with reference to the flowchart of FIG. In order to recognize the multi-clock waveform as shown in FIG.
First, it recognizes what kind of signal change occurred at what time from the beginning of the cycle in the input mode of the input signal and the bidirectional signal (step S41).

If the condition shown in the waveform chart of FIG. 5 is satisfied, that is, one cycle is equally divided, and the same signal change pattern is present in each equally divided portion. For example, the logic simulation result editing device 13 recognizes it as a multi-clock waveform (step S42), and determines the timing required when applying the multi-clock waveform on the tester.
Information regarding 6a, 6b, 6c is extracted (step S43), and the result is stored in the intermediate test pattern file 14 (step S43).
S44).

On the other hand, in order to recognize the pin multiplex waveform, the same step S41 as in the case of the above-described multi-clock waveform is performed, and if the recognized signal change time and the like do not satisfy the condition of FIG. If there are only a plurality of signal changes in one cycle, the logic simulation result editing device 13 recognizes it as a pin multiplex waveform.
(Step S42) The timing information necessary for applying the pin multiplex waveform on the tester is extracted (Step S42).
S45), the result is stored in the intermediate test pattern file 14.
(Step S44).

FIG. 7 is a flow chart showing a sixth aspect of the logic simulation result editing apparatus according to the present invention, that is, an operation procedure for extracting the same pattern in consecutive cycles. The logic simulation result editing device 13 first edits the test pattern of the first cycle and saves it until the pattern editing of the next cycle is completed (step S51). Then, the logic simulation result editing device 13 saves it when the pattern editing of the next cycle is completed (step S5
2), compare the saved new and old patterns (step S53).

If the comparison results match, the logic simulation result editing device 13 stores information indicating how many cycles of patterns match and the pattern information.
If they do not match, the older one of the saved pattern information is output and stored in the intermediate test pattern file 14,
The newer pattern is saved (step S55).

The above process is repeated for all cycles.
(Step S56), the finally saved pattern is also stored in the intermediate test pattern file 14 (step S7).
g). By such processing, the intermediate test pattern file 14 for the same pattern over a plurality of cycles
Can be stored in.

In the example of the timing chart of FIG. 3, the first and second cycles of the signal line 8b have the same pattern, and the third and fourth cycles have the same pattern. In the present invention, the pattern output for four cycles is sufficient to output the pattern for four cycles.

[0044]

As described in detail above, according to the logic simulation result editing apparatus of the present invention, the LSI test time is shortened, and the development cost of the program for the Hiz pattern corresponding to each tester is reduced. Multi-clock waveform,
The pin multiplex waveform can be edited, and the same test pattern can be compressed to efficiently use the test pattern storage capacity.

[Brief description of drawings]

FIG. 1 is a flowchart showing an operation procedure of a first invention of a logic simulation result editing device according to the present invention.

FIG. 2 is a flowchart showing an operation procedure of the second invention of the logic simulation result editing device according to the present invention.

FIG. 3 is a timing chart showing an example of a logic simulation result of three signal lines.

FIG. 4 is a flowchart showing an operation procedure of the third invention of the logic simulation result editing device according to the present invention.

FIG. 5 is a waveform diagram showing a multi-clock waveform.

FIG. 6 is a flowchart showing the operation procedure of the fourth and fifth inventions of the logic simulation result editing device according to the present invention.

FIG. 7 is a flowchart showing an operation procedure of the sixth invention of the logic simulation result editing device according to the present invention.

FIG. 8 is a schematic diagram showing a configuration of a general test program generation device.

FIG. 9 is a timing chart showing the result of logic simulation.

[Explanation of symbols]

 11 Logic simulation result file 12 Control data file 13 Logic simulation result editing device 14 Intermediate test pattern file 15 Translator 16 Test program file 17 Tester

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[Procedure amendment]

[Submission date] February 17, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 4

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 5

[Correction method] Change

[Correction content]

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

According to a fourth aspect of the present invention, means for recognizing a signal change time point in each cycle of the logic simulation result,
The time of the signal change recognized by this means and the control data
And a means for editing the multi-clock waveform as an intermediate test pattern based on the test cycle included in the data .

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

According to a fifth aspect of the invention, means for recognizing a time point of signal change for each cycle of the logic simulation result,
The time of the signal change recognized by this means and the control data
And a means for editing the multiplexed waveform as an intermediate test pattern based on the test cycle included in the data .

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

In the second invention, for each cycle of the logic simulation result, the time point of the latest signal change in each cycle is recognized, the latest time point is selected in all cycles , and the selected time point is selected. From the time when the predetermined time included in the control data elapses,
It is obtained as the cycle of the intermediate test pattern that is common to all cycles of the logic simulation result.

[Procedure correction 6]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

According to the fourth aspect of the present invention, the signal change time point is recognized for each cycle of the logic simulation result, and the recognized signal change time point and the test included in the control data are recognized.
The multi-clock waveform is edited as an intermediate test pattern based on the cycle .

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Change

[Correction content]

In the fifth invention, the signal change time point is recognized for each cycle of the logic simulation result, and the recognized signal change time point and the test included in the control data are recognized.
The multiplex waveform is edited as an intermediate test pattern based on the period .

Claims (6)

[Claims] 1. Data of a logic simulation result of a logic circuit and control data necessary for editing a test pattern are input, and data of an intermediate test pattern for generating a test program corresponding to each tester is input. In the logic simulation result editing device to be edited, for each cycle of the logic simulation result, means for recognizing the latest signal change time point in each cycle, and a predetermined time contained in the control data from the time point recognized by the means A logic simulation result editing device, comprising: means for obtaining a period of an intermediate test pattern corresponding to each period of a logic simulation result up to the point of time. 2. Data of a logic simulation result of a logic circuit and control data necessary for editing a test pattern are input, and data of an intermediate test pattern for generating a test program corresponding to each tester is input. In the logical simulation result editing device to be edited, for each cycle of the logical simulation result, means for recognizing the latest signal change time point in each cycle, and the latest time point for all cycles of the time points recognized by the means are identified. A means for selecting, and a means for obtaining from the time point selected by the means to the time point when a predetermined time included in the control data elapses as a cycle of the intermediate test pattern common to all cycles of the logic simulation result. A logic simulation result editing device characterized by the above. 3. Data of a logic simulation result of a logic circuit and control data necessary for editing a test pattern are input, and data of an intermediate test pattern for generating a test program corresponding to each tester is input. In the logical simulation result editing device to be edited, means for recognizing whether each of the cycles of the logical simulation result is in a high impedance state, and a cycle of an intermediate test pattern of the cycle recognized as a high impedance state by the means. And a means for editing a pattern, which is extended according to data of a predetermined time included in the control data, as an intermediate test pattern. 4. Data of a logic simulation result of a logic circuit and control data necessary for editing a test pattern are input, and data of an intermediate test pattern for generating a test program corresponding to each tester is input. In the logical simulation result editing device to be edited, means for recognizing a signal change time point for each cycle of the logic simulation result, a signal change time point recognized by the means, and a signal line input included in the control data, A logic simulation result editing apparatus comprising: a means for editing a multi-clock waveform as an intermediate test pattern based on a pin class indicating the output and the bidirectional signal. 5. Data of a logic simulation result of a logic circuit and control data necessary for editing a test pattern are input, and data of an intermediate test pattern for generating a test program corresponding to each tester is input. In the logical simulation result editing device to be edited, means for recognizing a signal change time point for each cycle of the logic simulation result, a signal change time point recognized by the means, and a signal line input included in the control data, A logic simulation result editing device comprising: means for editing a multiplex waveform as an intermediate test pattern based on an output and a pin class indicating the difference between bidirectional signals. 6. Data of a logic simulation result of a logic circuit and control data necessary for editing a test pattern are input, and data of an intermediate test pattern for generating a test program corresponding to each tester is input. In a logical simulation result editing device for editing, a first means for storing a pattern for two cycles of a logical simulation result and a second means for comparing a pattern for two cycles stored by the first means. A third means for storing the pattern of the next cycle in place of the newer pattern stored by the first means when the comparison result by the second means is coincident; A fourth method for saving the newer pattern instead of the older pattern stored by the first means when the comparison result by the means does not match. When the logical simulation result editing apparatus is characterized in that a means for editing the older patterns of the first means has been stored as an intermediate test pattern.