JPH06348648A - Bus interface device - Google Patents

Abstract

PURPOSE:To simplify the connection beetween two processors which deal with M and N bits respectively by converting the data bus widths and the modes of transmission signals between both processors in regard of a bus interface device. CONSTITUTION:A bus interface device is provided with a transfer control means 11 which controls the transfer of M-bit data DM (M=1-M), (m) of control signals Sm (m=1-m), N-bit data DN (N=1-N), and (n) of control signals Sn (n=1-n) respectively, a 1st input/output means 12 which inputs and outputs the M-bit DM and (m) of control signals Sm, and a 2nd input/output means 13 which inputs and outputs the N-bit data DN and (n) of control signals Sn. Then the means 11 recognizes the input/output states of the signals Sm or Sn and decides the transfer direction of the data DM or DN to transfer the data in response to the data width of the transferred direction.

Description

Detailed Description of the Invention

[Table of Contents] Industrial Application Field of the Prior Art (FIG. 8) Problem to be Solved by the Invention (FIG. 9) Means for Solving the Problem (FIG. 1) Working Example (1) First Example Description of Embodiments (FIGS. 2 to 6) (2) Description of Second Embodiment (FIG. 7)

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface device, and more specifically to a SCSI interface device.
The present invention relates to a SCSI conversion unit that connects an M-bit compatible data processing device and an N-bit compatible data processing device in a (Small Computer System Interface) device.

In recent years, the amount of data processing in information processing systems has been increasing. In particular, in voice processing, image processing, etc., a large amount of data is processed, and naturally it becomes difficult to make the data resident in the memory in the host machine. Therefore, a large-capacity external storage device has come to be connected to the host machine, and the SCSI bus connecting the interfaces is becoming mainstream.

According to this, there are three types of versions of the SCSI bus, and at present, the SC equipped with only the SCSI-1 and SCSI-2 A cables (8-bit data transfer).
SI data bus is used. However, in order to shorten the data exchange time with the external storage device in the host machine, provision of 16-bit transfer by the SCSI-3 P cable is beginning to be adopted.

Therefore, an SCS equipped with an A cable
In the I device, the data bus width is converted between the 8-bit processing device and the 16-bit processing device, and the mode conversion of the transmission signal is performed to facilitate the connection between the devices. A device that can do this is desired.

[0006]

2. Description of the Related Art FIGS. 8 and 9 are explanatory views of a conventional example. FIG. 8 is an explanatory diagram of SCSI bus and data bus width conversion according to the conventional example, and FIG. 9 is a state diagram of a connector connection for explaining the problem. For example, 8
SCSI (Small Comput) connected to a bit signal cable (hereinafter referred to as A cable) 5 for various data processing
er System Interface) data system is shown in FIG.
In FIG. 1, it comprises a small microcomputer 1, a frame memory 2, a numerical data memory 3 and another processing device 4. In the A cable 5 connected between these information processing devices, 9 data lines and 9 control lines are incorporated into one signal cable according to the international ISO standard.

Table 1 is a standardized cable correspondence table for a SCSI bus. SCSI-1 is an international ISO standard, and SCSI-2 and SCSI-3 are ANSI standard proposals.

[0008]

[Table 1]

In Table 1, in addition to SCSI-1, SCS
I-2, SCSI-3 compatible cables are available, and SCSI
In -2, two control lines and 27 data / data buses are incorporated into one signal cable in the B cable. SCS
In I-3, the P cable has 9 control lines and 18 data / data buses built into one signal cable, and the Q cable has 2 control lines and 27 data / data buses into one signal cable. Some are built in.

FIG. 8B is a pin layout diagram of the connector for explaining the data bus width conversion. In FIG. 8A, S
The P cable compatible connector 6 for the CSI-3 bus has 68 input / output pins, and the A cable compatible connector 7 for the SCSI-1 bus has 50 input / output pins. In the ANSI standard proposal, the A cable compatible connector 7 can be connected to the P cable compatible connector 6 in order to increase the versatility of the device used. That is, FIG.
In (A), pin numbers 11 to 5 of the connector 6
A total of 50 pins of 9, 12 to 20 can be connected to a total of 50 pins of pin numbers 01 to 49, 02 to 50 of the A-cable compatible connector 7 via the SCSI-1 or SCSI-2 cable 8. . Thereby, for example, various data processing can be performed by connecting an 8-bit processing device to a 16-bit processing device.

[0011]

By the way, according to the conventional example, a 16-bit compatible processing device is provided with a P cable compatible connector 6 having 68 input / output pins, and an 8-bit compatible processing device is provided. An A-cable compatible connector 7 having 50 input / output pins is provided. Therefore, P
Provide a cable compatible connector 6 between processing devices compatible with 16 bits, and provide an A cable compatible connector 7 8
8-bit (hereinafter also referred to as M-bit) -compatible processing that provides an A-cable compatible connector 7 between bit-compatible processing devices and a 16-bit-compatible processing device (initiator side) that provides a P-cable compatible connector 6 When the device (target side) is connected, the data transfer process can be smoothly performed.

However, as shown in FIG. 9, an 8-bit processing device (initiator side) which provides an A-cable corresponding connector 7 and a 16-bit processing device (target-side which provides a P-cable corresponding connector 6). ), It is impossible to connect 68 input / output pins to 50 input / output pins, and data transfer processing cannot be performed.

This is the existing SCSI-1 or SCSI
-2, which is a high-end model for the data system
It is necessary when connecting a processing device compatible with 16 bits (hereinafter also referred to as N bits) of I-3, for example, an external storage device to increase the speed of various data processing and increase the memory capacity. Thereby, for example, when the initiator side such as a personal computer or a workstation provides the P cable 7, whether the device driver or the external storage device on the host machine side is compatible with the A cable 6, or the P cable 7 is used.
It is necessary to confirm that the specifications are compatible. Further, if it is attempted to improve it, there is a problem that each machine must be equipped with a device driver corresponding to each 8/16 bit.

The present invention was created in view of the problems of the conventional example, and converts the data bus width between the processing device compatible with M bits and the processing device compatible with N bits, and transmits the transmission signal. It is an object of the present invention to provide a bus interface device capable of simplifying the connection between these devices by performing the mode conversion of.

[0015]

FIG. 1 shows a principle diagram of a bus interface device according to the present invention. As shown in FIG. 1, the first bus interface device of the present invention includes M-bit data DM, [M = 1 to M] and m control signals Sm, [m = 1 to m] and N-bit data. D
N, [N = 1 to N] and n control signals Sn, [n = 1
~ N], a transfer control means 11 for controlling transfer, a first input / output means 12 for inputting / outputting the M-bit data DM and m control signals Sm, and the N-bit data DN and a second input / output means 13 for inputting / outputting n control signals Sn, and the transfer control means 11 recognizes the input / output state of the m control signals Sm or the n control signals Sn. , M-bit data DM or N-bit data D
It is characterized in that the transfer direction of N is determined and the data is transferred in conformity with the data width in the transferred direction.

In the first bus interface device of the present invention, the first and second input / output means 12, 1 are provided.
3 to each of two types of connection terminals T11, T12, T21, T
22 is provided, and a single end signal mode cable is connected to one of the connection terminals T11, T12 of the first and second input / output means 12, 13 according to the use mode. The other connecting terminal T2 of the input / output means 12, 13 of
A differential signal mode cable is connected to 1 and T22.

Further, in the first bus interface device of the present invention, the transfer control means 11 comprises at least a data transfer control section 11A and a data conversion section 11B, and the data transfer control section 11A has m control signals. The input / output state of Sm or n control signals Sn, [n = 1 to n] is recognized, and the data DM or data DN, [N = 1 to 1] is recognized.
N] is controlled based on the transfer control signals REQ and ACK, and the data converter 11B converts the M-bit data DM into the N-bit data DN in accordance with the data transfer direction, or the N-bit data DN. It is characterized in that the data DN is converted into M-bit data DM.

The second bus interface device of the present invention is the same as the first device, except that the transfer control means 11 is used.
A storage means 11C is provided in the storage means 11C, and the storage means 11C temporarily stores the M-bit data DM or the N-bit data DN associated with the data transfer, thereby achieving the above object.

[0019]

[Operation] According to the first bus interface device of the present invention, as shown in FIG.
The transfer control means 1 is provided with the second input / output means 12 and 13.
1 recognizes the input / output state of the m control signals Sm or the n control signals Sn, determines the transfer direction of the M-bit data DM or the N-bit data DN, and determines the data width in the transferred direction. Match and transfer data.

For example, a cable for single-end signal mode including M-bit data DM on the initiator side and m control signals Sm is connected to the connection terminal T11 of the first input / output unit 12 according to the usage mode, A differential signal mode cable including the target side N-bit data DM and n control signals Sn is connected to the connection terminal T22 of the second input / output unit 13.

Now, the operation when n-bit data DN on the target side is transferred to the initiator side (data in phase) and n = m will be described. First, the data transfer control unit 11A of the transfer control means 11 recognizes the input state of the N-bit data DN and the n control signals Sn as the differential signal as the transmission signal mode input from the target side. The transfer direction of the data DN, that is, the target side → the initiator side is determined.

Next, the data transfer control unit 11A identifies the transfer control signals REQ and ACK among the n control signals Sn. As a result, the data conversion unit 11B converts the N-bit data DN into the M-bit data DM, which is the data transfer direction determined in advance, that is, the M-bit data converted from the target side to the initiator side. The output of DM is controlled based on the transfer control signals REQ and ACK.

Therefore, it becomes possible to transfer M-bit data DM and m control signals Sm by a single end signal as a transmission signal mode to the initiator side connected to the first input / output means 12. In the case of transferring M-bit data DM of the initiator side to the target side (data out phase) and n = m, first, the data transfer control unit 11A of the transfer control means 11 As the transmission signal mode input from the initiator side, the input state of the M-bit data DM and the m control signals Sm is recognized by the single end signal, and the transfer direction of the M-bit data DM, that is, the initiator side → the target side is changed. It is determined.

Next, the data transfer control unit 11A identifies the transfer control signals REQ and ACK among the m control signals Sm. As a result, the data conversion unit 11B converts the M-bit data DM into the N-bit data DN, which is the previously determined data transfer direction, that is, the N-bit data converted from the initiator side to the target side. The output of DN is controlled based on the transfer control signals REQ and ACK.

Therefore, it becomes possible to transfer the M-bit data DM and the m control signals Sm by the differential signal as the transmission signal mode to the target side connected to the second input / output means 13. As a result, the data bus width can be converted between the M-bit compatible processing device and the N-bit compatible processing device, and the mode conversion of the transmission signal can be performed, and the connection between these devices can be simplified. Can be achieved.

According to the second bus interface device of the present invention, the transfer control means 1 is provided in the first device.
1 is provided with a storage means 11C. Therefore, M-bit data DM or N-bit data DN accompanying data transfer
Can be temporarily stored in the storage means 11C, and the data transfer time and the data bus occupation time can be shortened.

That is, in the case where the first input / output means 12 is connected to the initiator side and the second input / output means 13 is connected to the target side, the N-bit data DN on the target side is transferred to the initiator side. When transferring (data in phase), the data transfer control unit 11A of the transfer control unit 11 recognizes the input state of the N-bit data DN and the n control signals Sn input from the target side, and the N-bit data The transfer direction of the DN, that is, the target side → the initiator side is determined.

As a result, the data converter 11B converts the N-bit data DN into the M-bit data DM, which is stored in the storage means 11C. When this becomes a full state, the following control is performed. For example, output of the M-bit data DM, which has been data-converted in the previously determined data transfer direction (target side → initiator side), is controlled based on the transfer control signals REQ and ACK. Here, the data transfer control unit based on the control signal from the target side.
In response to the reselection, 11A sends M-bit data DM from the storage means 11C to the initiator side in response to the transfer control signal REQ from the target side. At the same time, the transfer control signal ACK is also transmitted. Further, when the storage means 11C becomes empty (empty), another control signal, for example, an attention signal is responded to the target side, and the data transfer control section 11A requests the transition to the message out phase and the data bus The second input / output unit 13 is instructed to disconnect and reconnect.

As a result, a processing device compatible with M bits and N
It is possible to achieve a connection and simplification with a bit-compatible processing device and to improve the performance of the information processing system.

[0030]

Embodiments of the present invention will now be described with reference to the drawings. 2 to 7 are diagrams illustrating a bus interface device according to an embodiment of the present invention. (1) Description of First Embodiment FIG. 2 is a configuration diagram of a SCSI bus conversion unit according to the first embodiment of the present invention. FIG. 3 is a configuration diagram of a signal mode switching unit according to each embodiment. FIG. 4 is a functional explanatory diagram of the SCSI phase detection unit according to each embodiment. 5 is a time chart of the transfer direction and the data-in phase according to each embodiment, and FIG. 6 is a time chart of the data-out phase thereof.

For example, an SC for connecting between an 8-bit data processing device and a 16-bit data processing device.
The SI conversion unit is, in FIG. 2, a transfer control system 21, signal mode switching units 22 and 23, and a connector 24 to.
It consists of 27. In the embodiment of the present invention, in order to simplify the description, a case where the number of control signals m = n will be described.

That is, the transfer control system 21 is an embodiment of the transfer control means 11, and includes, for example, 9-bit data DB7 to DB0, parity bit DP, [M = 9], and nine control signals (hereinafter referred to as CTRL signal). (Referred to as (9))
[M = 9], 18-bit data DB15 to DB0, parity bits DP, DP1, [N = 18], and nine control signals (hereinafter referred to as CTRL signal (9)), [n = 9].
The transfer control is performed between and.

The transfer control system 21 includes a phase detector 21.
1, a REQ / ACK control unit 212 and an 8 / 16-bit data conversion unit 21B. Phase detector 211 and REQ
The / ACK control unit 212 is an example of the data transfer control unit 11A, and the phase detection unit 211 recognizes the input / output state of the CTRL signal (9) and determines the data transfer direction. Further, an input / output control signal (hereinafter referred to as a D / I signal) is output from the phase detection unit 211 to the REQ / ACK control unit 212. The function of the phase detection unit 211 will be described in detail with reference to FIG.

In the data-in phase, the REQ / ACK control section 212 responds to the REQ signal transmitted from the initiator side with the data DB7 to DB based on the D / I signal.
It controls the output of 0 and DP, and responds with an ACK signal to the initiator side. In the data out phase, the output control of the data DB15 to DB0, DP, DP1 is performed based on the D / I signal in response to the REQ signal transmitted from the target side, and the target side is responded with the ACK signal.

The 8 / 16-bit data conversion unit 21B is an example of the data conversion unit 11B and is composed of two 8-bit registers. For example, the conversion unit 21B converts the 8-bit data DB7 to DB0, excluding the parity bit DP, into the 16-bit data DB1 in accordance with the data bus width in the transferred direction.
5 to DB0, or vice versa, 16-bit data D
B15 to DB0 are converted into 8-bit data DB7 to DB0.

The signal mode switching unit 22 is an embodiment of the first input / output means 12 and is composed of 9-bit data DB7-DB.
This is a selector for inputting / outputting 0, DP and CTRL signals (9). The signal mode switching unit 23 is an example of the second input / output unit 13 and includes the 18-bit data DB 7-.
It is a selector for inputting / outputting DB0, DP, DP1 and the CTRL signal (9).

For example, as shown in FIG. 3A, the signal mode switching units 22 and 23 are composed of a logic gate circuit 23A, and as shown in FIG. 3B, a tristate driver / receiver. Division (hereinafter simply referred to as DV / RV)
It may be configured to also serve as 26B or 27B. That is, in FIG. 3A, the logic gate circuit 23A has a 4-input AND circuit.
-OR circuit 231 and two two-input AND circuits 232 and 233
And selects either bidirectional DV / RV26A or DV / RV27A based on the mode switching signal S / D, and outputs the CTRL signal (9) in the single end signal mode or the differential signal mode to the phase detector.
Switch to 211 and input.

On the contrary, the logic gate circuit 23A sends the CTRLR signal (9) in the single end signal mode or the differential signal mode transferred from the phase detector 211 based on the mode switching signal S / D to the DV / RV 26A.
Alternatively, the output is switched to either DV / RV27A.
The mode switching signal S / D is generated by operating a manual switch provided in the conversion unit. The manual switch is operated based on the system specifications when constructing the SCSI bus.

Further, the DV / RV 26A is connected to the connector 26 and outputs and amplifies the CTRLR signal (9) in the single end signal mode or inputs and amplifies the CTRL signal (9). Similarly, DV / RV27A is connector 2
CTR connected to 7 and in differential signal mode
The LR signal (9) is output-amplified and the CTRL signal (9) is input-amplified.

Further, in FIG. 3B, in the case where the signal mode switching units 22 and 23 also serve as the tri-state type DV / RVs 26B and 27B, the mode switching signal S / D is used.
Either DV / RV26B or DV / RV27B is selected based on the above, and the CTRL signal (9) in the single end signal mode or the differential signal mode is switched and input to the phase detection unit 211. On the contrary, DV / RV
Based on the mode switching signal S / D, 26B and 27B switch the CTRLR signal (9) in the single end signal mode or the differential signal mode transferred from the phase detector 211 to either one of the connectors and output it.

The DV / RV 26B is connected to the connector 26 and amplifies the output of the CTRLR signal (9) in the single end signal mode or the input amplification of the CTRL signal (9). Similarly, DV / RV27B is connector 2
CTR connected to 7 and in differential signal mode
The LR signal (9) is output-amplified and the CTRL signal (9) is input-amplified.

Also, a tri-state type DV / RV26B
In the case where the signal mode switching units 22 and 23 which also serve as the switch 27 and the switch 27B are configured, the logic gate circuit 23A becomes unnecessary and the semiconductor integrated circuit device can be downsized. Here, returning to FIG. 2, the connector 24 is an example of the connection terminal T11, and a single-ended signal mode cable such as an A cable or a B cable compatible with SCSI-1 and SCSI-2 is connected according to the usage mode. It The connector 25 is an example of a connection terminal T21, and a differential signal mode cable such as an A cable or a B cable compatible with SCSI-1 and SCSI-2 is connected thereto.

Further, the connector 26 is an example of the connection terminal T12, and a single end signal mode cable such as a SCSI-3 compatible P cable or Q cable is connected thereto. The connector 27 is an example of the connection terminal T22, and the SCS
A differential signal mode cable such as an I-3 compatible P cable or Q cable is connected. Table 2
7 to 7 are pin arrangement tables of the connector of the SCSI bus conversion unit according to each embodiment of the present invention. Here, as shown in Tables 2 to 7, the CTRL signal (9) includes ATN, BSY, RST, MSG, SEL, in addition to REQ and ACK signals.
The contents are formed by nine control signals of C / D and I / O signals.

Table 2 shows the SCSI-A cable connector (SI
NGLE-ENDED type) pin layout for the single-ended signal mode connector.

[0045]

[Table 2]

Table 3 shows the SCSI-A cable connector (DI
FFRETIAL type) pin arrangement, and the pin arrangement for the differential signal mode connector.

[0047]

[Table 3]

Table 4 shows the SCSI-B cable connector (SI
NGLE-ENDED type) pin layout for the single-ended signal mode connector.

[0049]

[Table 4]

Table 5 shows the SCSI-B cable connector (DI
FFRETIAL type) pin arrangement, and the pin arrangement for the differential signal mode connector.

[0051]

[Table 5]

Table 6 shows the SCSI-P cable connector (SI
NGLE-ENDED type) pin layout for the single-ended signal mode connector.

[0053]

[Table 6]

Table 7 shows the SCSI-P cable connector (DI
FFRETIAL type) pin arrangement, and the pin arrangement for the differential signal mode connector.

[0055]

[Table 7]

Thus, the first SCSI of the present invention is
According to the bus conversion unit, the transfer control system 21 and the signal mode switching units 22 and 23 are provided as shown in FIG. 2, and the transfer control system 21 causes the CTRL signal (9).
9-bit data DB7-D
B0, DP or 18-bit data DB7 to DB0, D
It is possible to determine the transfer direction of P and DP1 and transfer the data while matching the data width in the transferred direction.

For example, as shown in FIG. 5B, a SCSI-1 compatible A cable is connected between an 8-bit compatible device 101 (initiator side) and the SCSI bus conversion unit 100, and a 16-bit compatible device is connected. 102 (Target side)
Between the SCSI bus conversion unit and the SCSI-3
Connect the corresponding P cable. Here, the operation in the case of transferring the 18-bit data DB15 to DB0, DP, and DP1 on the target side to the initiator side (data in phase) will be described. First, when the REQ signal from the A cable is received, the phase detection unit 211 of the transfer control system 21 sets the transmission signal mode input from the target side as a differential signal 18
Bit data DB15 to DB0, DP, DP1 and C
The input state of the TRL signal (9) is recognized.

As a result, it is recognized that the SCSI device connected to the conversion unit 100 of the present invention has been designated, and the DV / RV26 is selected in response to the mode switching signal S / D.
A, 27A direction control, its transfer direction, that is,
Target side → initiator side is determined. at the same time,
The instruction is stored. At this time, as shown in the state transition diagram of FIG. 4, the phase detection unit 211 identifies the bus-free state BF by the reset operation RS, and when it is identified, the arbitration operation AR of the data bus is performed. Transition. If the data bus arbitration operation AR fails, the process returns to the identification of the bus free state BF. When the arbitration operation AR is successful, the operation shifts to the selection operation SE, and the control signals required for the operation of the signal mode switching units 22 and 23 are selected.

Here, if the selection operation SE fails, the process returns to the identification of the bus free state BF, and the arbitration operation A again.
After R, the operation moves to the selection operation SE to select a control signal. Next, information phase operation i
The process proceeds to nF, and any one of the message out Mo, message in Mi, status St, data out Do, or data in Di control is selected. The phase operation inF goes through the cycling state, and if it fails, returns to the identification of the bus-free state BF.

As a result, the phase detector 211 detects the CTR.
When the REQ signal and the ACK signal in the L signal (9) are identified, the 8/16 data conversion unit 21B converts the 16-bit data DB15 to DB0 into the 8-bit data DB7 to DB0.
Is output to the initiator side from the target side, that is, the data transfer direction determined previously.

At this time, in the data in-phase time chart of FIG. 5B, when the A cable side is the initiator and the data DB 15 from the P cable is
When receiving ~ DB0, the data is held by the REQ signal from the P cable, and at the same time, two REQ signals for controlling the 9-bit data DB7 to DB0, DP to be output to the A cable are generated, and the first REQ signal is generated. Send the lower 9-bit data DB7 to DB0, DP to the A cable, and use the second REQ signal to send the upper 9-bit data D
B15 to DB8 and DP1 are sent to the A cable. After that, only the second ACK signal corresponding to the REQ signal from the A cable is transmitted as a signal of the P cable.

Therefore, the SCSI bus conversion unit concerned
Initiator-side 8-bit compatible device connected to 100 10
1, it becomes possible to transfer 9-bit data and CTRL signal (9) by a single end signal as a transmission signal mode. Also, regarding the operation in the case of transferring the 9-bit data on the initiator side to the target side (data out phase), first, when the REQ signal from the P cable is received, the phase detection unit 211
As the transmission signal mode input from the initiator side,
9-bit data DB7 to DB for single-ended signals
The input states of 0, DP, and CTRL signal (9) are recognized, and the transfer direction, that is, the initiator side → the target side is determined. At this time, the phase detection unit 211 follows the state transition diagram described above and follows the signal mode switching unit 2
The control signals necessary for the operations 2 and 23 are selected (see FIG. 4).

As a result, the phase detector 211 detects the CTR.
When the REQ signal and the ACK signal in the L signal (9) are identified, the 8/16 data converter 21B converts the 8-bit data DB7 to DB0 into the 16-bit data DB15 to DB.
0, which is the data transfer direction previously determined,
That is, it is output from the initiator side to the target side.

At this time, in the time chart of the data-out phase in FIG. 6, the case where the A cable side is the initiator and the data DB7 to DB from the A cable is
When 0 is received, two REQ signals for controlling the 9-bit data DB7 to DB0 received from the A cable are generated, and the lower 9-bit data DB7 to DB0 of the A cable is generated by the ACK signal corresponding to the first REQ signal. Hold
The ACK signal corresponding to the second REQ signal holds the upper 9-bit data DB15 to DB0 of the A cable, at the same time, sends it to the P cable and also sends the second ACK signal.

Therefore, the SCSI bus conversion unit concerned
16-bit compatible device on the target side connected to 100
Secondly, it becomes possible to transfer 18-bit data and CTRL signal (9) by a differential signal as a transmission signal mode. Further, when the A-cable side is the target, the operations are all reversed, and the description thereof is omitted.

As a result, when an 8-bit processing device (initiator side) that provides an A cable compatible connector is to be connected to a 16 bit processing device (target side) that provides a P cable compatible connector. In addition, 68 input / output pins can be connected to 50 input / output pins through the SCSI bus conversion unit.

The existing SCSI-1 or SCSI-
SCSI, which is a high-end model for the 2 data system
It is possible to increase the speed of various data processes and increase the memory capacity by connecting a 16-bit processing device such as -3, such as an external storage device. In addition, the data transfer process can be smoothly performed. From this, for example, if the initiator side such as a personal computer or a workstation provides the P cable, whether the device driver or the external storage device on the host machine side is the A cable compatible specification or the P cable compatible specification. The work of confirming is unnecessary. In addition, it is possible to easily connect existing processing devices without equipping each machine with a device driver corresponding to each 8/16 bit.

(2) Description of Second Embodiment FIG. 7 is a block diagram of a SCSI bus conversion unit according to the second embodiment of the present invention. In the second embodiment, the first
Unlike the above embodiment, a buffer memory 31C is provided in the transfer control system 31, and 9-bit data DB7 to DB0 or 18-bit data DB15 to DB associated with data transfer.
0 is temporarily stored.

That is, S according to the second embodiment of the present invention.
The CSI bus conversion unit is shown in FIG. 7 and includes a transfer control system 31, signal mode switching units 32 and 33, and a connector 3.
4 to 37. The transfer control system 31 comprises a phase detector 311, a REQ / ACK controller 312, an 8 / 16-bit data converter 31B and a buffer memory 31C. The phase detector 311 recognizes the input / output state of the CTRL signal (9) and determines the data transfer direction. In addition, the phase detector 311 includes a REQ / ACK controller 312 and a buffer memory 31.
D / I signal is output to C.

The REQ / ACK control section 312 receives a D / I signal and a memory over signal (hereinafter referred to as BF) in response to the REQ signal transmitted from the initiator side during the data in phase.
Data signals DB7 to DB0, D based on
The output of P is controlled and an ACK signal is returned to the initiator side. Further, in the data out phase, the D / I signal and the B signal are transmitted with respect to the REQ signal transmitted from the target side.
Data DB15 to DB0, DP, D based on the FL signal
It controls the output of P1 and responds with an ACK signal to the target side.

The buffer memory 31C is an example of the storage means 11C and includes a memory control signal (hereinafter referred to as BME signal), R
9-bit data DB based on EQ and ACK signals
7 to DB0 or 18-bit data DB15 to DB0 are temporarily stored. For example, buffer memory 31C
Is composed of a RAM (memory capable of writing / reading at any time) of about 0.2 [M bits], and the BME signal is generated by operating a manual switch provided in the conversion unit 100. The manual switch is operated when the SCSI bus is constructed and based on system specifications.

Since the configurations and functions of the signal mode switching units 33, 33 and the connectors 34 to 37 and the connecting method of the A cable and the P cable are the same as those in the first embodiment, the description thereof will be omitted. Thus, according to the SCSI bus conversion unit according to the second embodiment of the present invention,
As shown in FIG. 7, the transfer control system 31 is provided with a buffer memory 31C.

Therefore, at the time of data transfer, the BME signal,
9-bit data D based on REQ signal and ACK signal
B7 to DB0 or 18-bit data DB15 to DB0
Can be temporarily stored, and the data transfer time and the data bus occupation time can be shortened.
For example, when the signal mode switching unit 32 is connected to the initiator side and the signal mode switching unit 33 is connected to the target side, the target side 18-bit data D
When B15 to DB0, DP, DP1 are transferred to the initiator side (data in phase), the transfer control system 3
The 1-phase detector 311 recognizes the 18-bit data input from the target side and the input state of CTRL (9), and determines the transfer direction of the 18-bit data, that is, the target side → initiator side. As a result, in the 8/16 data conversion unit 31B, the 16-bit data DB15 to DB0 is converted to the 8-bit data DB7 to DB.
It is converted to 0 and stored in the buffer memory 31C. When this becomes full, the buffer memory
The BFL signal is output from the 31C to the REQ / ACK control unit 312, and the following control is performed.

That is, the 8-bit data DB7 to DB0 whose data has been converted in the previously determined data transfer direction (target side → initiator side) are output-controlled based on the REQ and ACK signals. For example, based on the control signal from the target side, the phase detection unit 311 responds to the reselection, and in response to the REQ signal from the target side, the 8-bit data D from the buffer memory 31C is received.
B7 to DB0 are sent to the initiator side. At the same time, an ACK signal is also sent. Also, the buffer memory 31C
When the status becomes empty (empty), another control signal such as an attention signal is responded to the target side, and the phase detection unit 311 requests transition to the message out phase, disconnects the data bus, and reconnects it. And the signal mode switching unit 33. When the A cable side is the target, the operations are all reversed.

As a result, an 8-bit processing device and 1
It is possible to simplify the connection with a 6-bit processing device and improve the performance of the information processing system.

[0076]

As described above, according to the bus interface device of the present invention, the transfer control means and the first and second input / output means are provided, and the transfer control means has m control signals or n control signals. By recognizing the input / output state of the control signal of the book, the transfer direction of the M-bit data or the N-bit data is determined, and the data transfer is performed in conformity with the data width in the transferred direction.

Therefore, the data bus width can be converted between the M-bit compatible processing device and the N-bit compatible processing device, and the mode of the transmission signal can be converted. Further, according to the bus interface device of the present invention, since the storage means is provided in the transfer control means, M-bit data or N-bit data accompanying the data transfer can be temporarily stored in the storage means, and the data transfer time can be increased. Can be shortened and the occupation time of the data bus can be shortened.

As a result, a processing device compatible with M bits and N
Simplification of connection with a bit compatible processor,
In addition, it greatly contributes to the improvement of the performance of the information processing system.

[Brief description of drawings]

FIG. 1 is a principle diagram of a bus interface device according to the present invention.

FIG. 2 is a configuration diagram of a SCSI bus conversion unit according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a signal mode switching unit according to each embodiment of the present invention.

FIG. 4 is a functional explanatory diagram of a SCSI phase detection unit according to each embodiment of the present invention.

FIG. 5 is a time chart of a transfer direction and a data-in phase according to each embodiment of the present invention.

FIG. 6 is a time chart of a data-out phase according to each embodiment of the present invention.

FIG. 7 is a configuration diagram of a SCSI bus conversion unit according to a second embodiment of the present invention.

FIG. 8 is an explanatory diagram of SCSI bus and data bus width conversion according to a conventional example.

FIG. 9 is a state diagram of a connector connection for explaining problems in the conventional example.

[Explanation of symbols]

 11 ... Transfer control means, 12 ... First input / output means, 13 ... Second input / output means, 11A ... Data transfer control section, 11B ... Data conversion section, 11C ... Storage means, T11, T12, T21, T22 ... Connection terminals, REQ, ACK ... Transfer control signals, Sm [m = 1 to m] ... m control signals, Sn [n = 1 to n] ... n control signals, DM [M = 1 to M] ... M-bit data, DN [N = 1 to N] ... N-bit data.

Claims (4)

[Claims] 1. M-bit data (DM, [M = 1 to 1
M]) and m control signals (Sm, [m = 1 to m]) and N-bit data (DN, [N = 1 to N]) and n control signals (Sn, [n = 1 to 1]). n]), and a first transfer control means (11) for controlling transfer with the first and second input / output of the M-bit data (DM) and m control signals (Sm).
Input / output means (12) and the N-bit data (D
N) and a second input / output unit (13) for inputting / outputting n control signals (Sn), wherein the transfer control unit (11) has m control signals (Sm).
Or by recognizing the input / output state of n control signals (Sn),
M-bit data (DM) or N-bit data (D
A bus interface device, characterized in that the transfer direction of N) is determined, and data is transferred in conformity with the data width in the transferred direction. 2. The bus interface device according to claim 1, wherein the first and second input / output means (12, 1)
3), two types of connection terminals (T11, T12, T2)
1, T22) are provided, and one of the connection terminals (T1) of the first and second input / output means (12, 13) is provided in accordance with the mode of use.
A cable for single-ended signal mode is connected to (1, T12), and the first and second input / output means (12, 1)
A bus interface device characterized in that a cable for differential signal mode is connected to the other connection terminal (T21, T22) of 3). 3. The bus interface device according to claim 1, wherein the transfer control unit (11) includes at least a data transfer control unit (11A) and a data conversion unit (11).
B), and the data transfer control unit (11A) has m control signals (S
m) or n input / output states of control signals (Sn) are recognized, the input / output control of the data (DM) or the data (DN) is performed based on the transfer control signals (REQ, ACK), and the data conversion is performed. Part (11B) is M according to the data transfer direction.
A bus interface device for converting bit data (DM) into N-bit data (DN) or converting N-bit data (DN) into M-bit data (DM). 4. The bus interface device according to claim 1, wherein the transfer control means (11) has a storage means (11).
C) is provided, and the storage means (11C) temporarily stores M-bit data (DM) or N-bit data (DN) accompanying data transfer.