JPH06338821A - Pll circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit by providing only one system for a PLL lock signal by employing such constitution that the PLL lock signal is outputted to a CPU only when both PLL lock signals of two systems on transmission and reception sides show locked states. CONSTITUTION:A cordless telephone set, etc., is constituted in such a way that a reception side RX-VCO and a transmission side TX-VCO are separated from the power source circuits 3, 4 of a PLL-IC so as to control input separately in transmission and reception, respectively. A diode D1 and a transistor TR2 comprise an AND circuit, and the PLL lock signal is outputted to the CPU when both the PLL lock signals on the transmission and reception sides are set at 'H'. Thereby, the transfer of information can be surely performed after a PLL is locked in both transmission and reception. Therefore, it is enough to set only one PLL lock line, which enables the circuit to be simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (phase locked loop) circuit such as a cordless telephone.

[0002]

2. Description of the Related Art FIG. 2 is a schematic configuration diagram of a conventional PLL integrated circuit, in which an X terminal is used for a reference oscillator for REF (circuit is not shown) to which Xtal is connected, and The signal is divided by the reference divider. RX
The receiving side VCO output is input from the terminal and programmable
Divided by divider RX. Transmitter VC from TX terminal
The O output is input and divided by the programmable divider TX. Data for frequency division ratio control is input to the decoder and frequency division ratio control is performed.

The divided VCO output on the receiving side and the divided reference signal are compared by the phase detector on the receiving side,
An output for controlling the VCO is output from the VCONT terminal on the receiving side to the VCO on the receiving side. In addition, VCO to CPU
The LOCK-R signal that indicates the locked or unlocked state of
Send from the X terminal. Similarly, the frequency-divided transmission-side VCO output and the frequency-divided reference signal are compared by the transmission-side phase detector, and the output for controlling the VCO is output from the transmission-side VCONT terminal to the transmission-side VCO. Also,
A signal indicating that the PLL on the transmitting side has been locked is also sent to the CPU from the LOCK-TX terminal when locked.

[0004]

However, in the prior art shown in FIG. 2, the PLL lock signal is transmitted to the transmitting TX side and the receiving RX side on separate lines A and B, respectively.
Since the data is input to the PU, there is a problem that the number of unnecessary CPU ports and PCB pattern routing increases.

The present invention has been made in view of the above-mentioned problems, and P of two systems of TX side and RX side input to the CPU.
An AND circuit is provided for the LL lock signal as one system, and the number of extra CPU ports, the number of connector pins between RF and logic, and the routing of PCB patterns can be reduced.
The purpose is to provide an LL circuit.

[0006]

In order to achieve the above object, the present invention provides a PLL circuit for a cordless telephone or the like which controls the communication by inputting PLL lock signals of two systems of a transmitting side and a receiving side to a CPU. Side PLL lock signal and transmitter side PLL lock signal as input, and transmitter side P
During the OFF period of the LL circuit, the state of the reception side PLL lock signal is output as it is to the CPU as a PLL lock signal, and when both the reception side PLL lock signal and the transmission side PLL lock signal are input, both signals are locked together. A feature is that the signal indicating that the PLL is locked is output to the CPU only when the signal indicates the state.

[0007]

With the above configuration, the AN receives the PLL lock signal on the receiving side and the PLL lock signal on the transmitting side as inputs.
The D circuit is the receiving side P when the transmitting side PLL circuit is OFF.
When only the LL circuit is operating, the states "H" and "L" of the PLL lock signal on the reception side are output to the CPU as PLL lock signals, and both the PLL lock signal on the reception side and the PLL lock signal on the transmission side are input. In this state, a signal indicating that the PLL is locked is output to the CPU only when both signals are lock signals.
The L lock signal can be output to the CPU by one system.

[0008]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a PLL circuit having an AND circuit of a PLL lock signal according to an embodiment of the present invention.

In this embodiment shown in FIG. 1, a diode 1 is provided between a PLL lock signal terminal LOCK-RX on the receiving side of a PLL integrated circuit and a PLL-LOCK signal line to a CPU.
And a transistor 2 provided between the transmission side PLL lock signal terminal LOCK-TX and the anode side of the diode 1 form an AND circuit. The resistor R1 on the RX-VCC power supply side and the resistor R2 on the TX-VCC power supply side are for signal levels. The other PLL-IC integrated circuit is the same as that of the conventional example, and includes RX-VCO (receiver side voltage controlled oscillator) and TX-V.
A CO (transmitter voltage controlled oscillator) is also shown in the conventional usage form.

Next, the operation will be described. Although not particularly limited to a cordless telephone, the case of a cordless telephone will be described below as an example. In a cordless telephone or the like, the power supply circuits 3 and 4 of the RX-VCO, TX-VCO and the PLL-IC are separately configured to control the ON / OFF of the transmitter and the receiver. During standby (waiting for reception), the power supply on the TX side is turned off to save power. With the TX circuit turned off, the RX-VCO output is first input to the RX terminal of the PLL-IC and divided. , The VCO control output by comparison with the divided reference signal is returned from the VCONT terminal and the pull-in operation is performed.

The PLL lock signal ("H" or "L") on the RX side is sent from the LOCK-RX terminal of the PLL-IC to the CPU via the diode 1 as the PLL-LOCK signal, but in the case of unlocking. , The transistor 2 is off now, so the cathode of the diode 1 is L
ow level, the anode of the diode 1 is also low level, and the PLL-LOCK signal to the CPU is "L".
Is. When locked, LOCK-RX of PLL-IC
Since the RX-PLL lock signal of High level "H" is output from the terminal, the cathode of the diode 1 is High.
Level, therefore the anode of diode 1 is applied via R1 RX-VCC (set value, around 3.8V)
Is high level, and PLL-LO to CPU
The CK signal becomes "H".

On the other hand, when the TX-PLL operates by starting the transmission, the L-IC is transmitted from the PLL-IC in the same procedure as the reception.
A PLL lock signal on the TX side is transmitted from the OCK-TX terminal. If the TX side PLL circuit is still unlocked,
Transistor 2 is turned on by TX-VCC (3.8V or so).
Since it becomes N, the PLL-LOCK signal to the CPU is "L" even if the PLL lock signal on the RX side is "H". When locked, “H” from LOCK-TX terminal
Since the transistor 2 is turned off by the output, RX-
Only when both the PLL lock signal and the TX-PLL lock signal are "H", the PLL-LOCK signal to the CPU is output "H".

If the above operation is shown as a truth table of the AND circuit, the signal LOCK-RX HL H HL LL LOCK-TX --- LL HL PLL-LOCK signal HL L H It becomes L L, and in the case of a and b in the table, LOC when TX is OFF
The operation of only K-RX is shown, and HA, D, E, and H are AND tables when both RX (reception) and TX (transmission) circuits are operating, and the AND of the present embodiment. Circuit is R
It operates as an AND circuit only when both X and TX circuits are operating.

In this way, the PLL-LOCK to the CPU
Even if the signal is set to one system C by the AND circuit, in the case of a cordless telephone or the like, there is no problem in the communication control procedure, rather the efficiency can be improved and extra ports and PCB patterns can be reduced. That is, in the case of a base unit or a handset of a cordless telephone, information is exchanged between them at different frequencies, so that actual exchange cannot be established unless the PLL is locked during transmission and reception.

[0015]

As described above, according to the present invention,
The receiver side PLL lock signal and the transmitter side PLL lock signal are input, and the state of the receiver side PLL lock signal is used as the PLL lock signal while the transmitter side PLL circuit is OFF.
When the lock signal for both output and reception is input to U and the lock signal for both transmission and reception is input, an AND circuit is provided to output the PLL lock signal of "H" to the CPU only when both signals are "H".
The number of LL-LOCK signal lines becomes one, the number of pins of the connector of the CPU port and the RF-logic is reduced, and there is an effect that the routing of the pattern becomes advantageous in the PCB of a limited area.

[Brief description of drawings]

FIG. 1A of a PLL lock signal according to an embodiment of the present invention
It is a block diagram of a PLL circuit with an ND circuit.

FIG. 2 is a schematic configuration diagram of a conventional PLL integrated circuit.

[Explanation of symbols]

 1 diode 2 transistor

Claims (1)

[Claims] 1. A PLL circuit, such as a cordless telephone, which controls the communication by inputting PLL lock signals of two systems of a transmission side and a reception side to a CPU, and transmits the PLL lock signal of the reception side and the PLL lock signal of the transmission side as inputs. While the side PLL circuit is OFF, the state of the reception side PLL lock signal is output as it is to the CPU as a PLL lock signal, and when both the reception side PLL lock signal and the transmission side PLL lock signal are input, both signals are input together. A PLL circuit that outputs a signal indicating that the PLL is locked to the CPU only when the signal indicates the locked state.