JPH06338597A - Method for formation of buried bit-line array of memory cell - Google Patents

Abstract

PURPOSE: To prevent an ohmic short circuit from occurring between bit lines by a method, wherein an active region composed of a first active region electrically connected to the capacitor of a memory cell and a second active region electrically connected to the bit lines is formed on a wafer adjacent to word lines to form a memory cell array. CONSTITUTION: A word line array, composed of word lines 36, 38, and 40 which are electrically insulated from each other, is formed on a wafer 35. Active regions 46 and 48 are provided around the word lines 36, 38, and 40. The active region 48 serves as a first active region, which is electrically connected to the capacitor of a memory cell. The active region 46 serves as a second active region electrically connected to a bit line. As a result, the active regions 46 and 48 form a memory cell FET array. By this setup, distance in silicides become minimum in the array, and a bit line can be decreased in resistance.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates generally to a method of forming a buried bit line array of storage cells.

[0002]

2. Description of the Related Art A conventional stack type DRAM memory array utilizes a structure of embedded bit lines or non-embedded bit lines. If the buried bit line structure is used, the bit line is placed in close proximity to the bit line contacts of the storage cell FET and the cell capacitor is horizontally oriented above the word line and the top of the bit line. It is formed. If the non-buried bit line structure is used, deep vertical contacts are formed through the thick insulating layer to the cell FET and the capacitor structure is provided above the word line and below the bit line. The disclosure herein relates to fabrication of memory arrays having embedded bit lines.

In the processing of semiconductor wafers, there is an ongoing goal to reduce the size of storage cells and thereby maximize density. At the time of making this specification, the industry is striving to develop a 64 megabyte DRAM with a typical chip size. DR
One concern in processing AM is the pitch or separation distance between adjacent bit lines and adjacent word lines. For example, with respect to bit lines, bit lines at various locations need to contact one of the active areas of each cell FET. Such a situation is commonly referred to as a bit line contact. An insulating layer is provided on the wafer to insulate the various active areas. Then, using photolithographic techniques, the bit line contacts to the desired active area are opened. At some later point in time, the bit line material is deposited on the wafer and patterned to form the desired array of bit lines.

However, a safety factor must be taken with respect to mask misalignment so that the bit line completely overlaps the bit contact. This is typically done by enlarging the area of the bit line around which the contact etch occurs, which allows mask misalignment in making proper contact of the bit line to the bit line contact.

Such a situation is illustrated in FIG. 1, which illustrates bit line 12 and bit line contact 14. If the bit line 12 overlaps the contact 14,
An enlarged bit line region 16 called "surround" is provided. This is the contact 14
An inadvertent mask misalignment of the patterning of the bit line 12 with respect to will cause the contact 14 to properly contact the bit line 12. However, this technique has the disadvantage that the overall enlargement of the bit lines requires the bit lines to be spaced farther apart from each other than if such surrounds were not present.

With respect to word lines, the problem of adversely affecting cell density for a buried bit line DRAM is illustrated in FIG. Shown is a wafer fragment 18 having a series of word lines 20, 22, 24. Bit line 26 is also shown. The cross section shown shows the array cut diagonally, so the bit lines 26 of FIG. 2 do not appear to extend at right angles to the word lines. In typical prior art fabrication, the word lines are first formed with respective spacers, such as spacer 28 shown. At some later point in time, bit line material is deposited on the wafer and etched to form respective bit lines 26. Insulating spacers must also be provided around the bit lines 26 for the purpose of electrical insulation. Reference numeral 32 is attached to the bit line spacer. The formation of spacers 32 has the disadvantage that additional spacers 34 are added around the word lines that are already insulated and spaced. Therefore, double spacers are formed around the word lines. This requires a greater separation of the word lines than is needed to provide the proper gap between each word line to form the desired contact to the active area for future storage capacitors. There is. Increasing the pitch of such word lines prevents density maximization.

Another problem with the formation of buried bit lines is the etching that produces the pattern of bit lines. The bit lines to be formed undulate vertically above and below the word lines, which results in widely varying topography or contours across the wafer. Etching layers with widely varying topography requires significant overetching and tends to leave resistive shorts between each bit line.

[0008]

SUMMARY OF THE INVENTION It is desirable to overcome the above and other prior art problems in forming a buried bit line array of storage cells.

In accordance with one aspect of the present invention, there is provided a method of forming a buried bit line array of storage cells, the method comprising a substantially electrically isolated conductive word on a semiconductor wafer. Providing an array of lines and separating conductive portions of adjacent word lines from each other by a selected separation distance; a first active region for electrically connecting with a capacitor of a storage cell; and a bit line. An active region formed by a second active region for electrically connecting with the word line is provided adjacent to the word line to form an array of storage cell FETs; and a first layer of material is selected. A thickness of the first material on the wafer, patterning and etching the layer of the first material to form a pattern of buried bit line trenches for forming buried bit lines therein. , Above bit line Providing a contact opening for the bit line to the second active region in the groove, and selecting sufficient to close the base of the groove of the bit line and make electrical contact with the second active region therein. Providing a layer of conductively doped polysilicon of a specified thickness on the wafer and having a higher conductivity than the conductively doped polysilicon in the trench of the bit line. Providing a conductive material over the polysilicon in the trench of the bit line, providing an insulating material over the conductive material, and electrically contacting the first active region. Providing an array of capacitors on the wafer.

The first material preferably comprises polyimide. It is also preferable to pattern the first material to form a first series of bit line trenches having a first selected width. A layer of insulating material is then provided on the wafer to a selected thickness above the layer that has been patterned and etched with the first material. The selected thickness of the insulating material is less than half of the first selected width, effectively reducing the width of the bit line trench to a smaller second width. After opening the bit line contacts through the insulating material, conductively doped polysilicon is deposited on the wafer and the process continues as described above. This has the effect of electrically insulating the side and top of the bit line in forming the groove of the bit line that forms the desired bit line pattern.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

Referring now to the drawings in detail, FIG. 3 shows a fragment of a semiconductor wafer, generally indicated at 35. The wafer 35 is provided with an array of substantially electrically isolated word lines, such as the word lines 36, 38, 40 shown. Such word lines comprise a normal bottom gate oxide, a polysilicon layer, an upper silicide layer such as tungsten silicide, an oxide cap and lateral oxide spacers. . The lateral oxide spacer is shown at 44 and the oxide cap is at 45.
The other features of the word lines 36, 38, 40 are not labeled for clarity of the drawing.

The conductive portions of adjacent word lines are separated from each other by a selected separation distance "F". According to one feature of the invention, the separation distance "F" can be the width of the selected smallest photofeature used in the photomasking process, thereby allowing the line used in the memory array. And the word line pitch that means the interval is 2 ×
Therefore, the circuit density is increased. It should be noted that with respect to the prior art of FIG. 2, the line separation distance on the side of the first storage node is about 1.5-2.0 F, considering the additional spacer 34.

Active regions are provided around the word lines to form an array of storage cell FETs such as the active regions 46, 48 shown around the word lines 38. Referring to transistor gate / wordline 38, the transistor gate / wordline is provided with a capacitor structure for defining a single storage cell. The active region 48 forms a first active region electrically connected to a storage cell capacitor (described later), and the active region 46 forms a second active region electrically connected to a bit line (described later). Form an active region.

A protective barrier layer 50 is provided on top of the wafer 35, the protective barrier layer having a thickness of about 100.
A thickness of angstroms to about 1000 angstroms is selected, with about 500 angstroms being most preferred. Layer 50 is preferably formed from a dielectric material, such as a SiO _x provided by chemical vapor deposition of TEOS or nitride material (CVD). The function of layer 50 is described in more detail below.

Referring to FIG. 4, a layer 52 of a first material is applied to the wafer, said layer of the first material comprising:
Provided on layer 50 at a selected thickness. The first material must be etchable selectively with respect to oxide and polysilicon. The polysilicon and oxide are preferably etchable selectively with respect to the first material. The first material also preferably provides a substantially flat top surface. The selected material is polyimide provided on the wafer 35. The preferred thickness of layer 52 is about 3,000 angstroms to about 12,000 angstroms on the top surface of oxide cap 45 (not visible in the cross-sectional view of FIG. 4),
Most preferably, it is about 5,000 Angstroms. If polyimide is used, the oxide layer 50 acts as a protective / barrier layer, preventing the polyimide from penetrating or migrating from the layer 50 into the substrate during various subsequent processing steps.

A nitride layer 54 is provided over the polyimide layer 52 to a thickness of about 200 angstroms to about 3,000 angstroms, with a thickness of about 1.
Most preferably, it is 500 Angstroms. The nitride layer 54 can be provided to form a hard protective mask over the polyimide layer 52 if desired. Such a mask serves in a later etching step to prevent unwanted polyimide removal at such stages of the process as described above. FIG. 4 illustrates layer 5 being patterned and etched to form buried bit line trenches 56 for forming buried bit lines.
2 and 54 are shown. Bit line groove 45 has a first selected width "A". For a 64 megabyte structure, "A" is expected to be about 4,000 angstroms to about 7,000 angstroms.
FIG. 5 is a plan view of the wafer 35 corresponding to the processing sequence of FIG. The etching to initially provide the bit line trenches 56 can be done by well known reactive ion etching techniques. The polyimide can be reactive ion etched in the presence of O ₂ (oxygen), which does not etch layer 50.

Immediately after the photoresist pattern, if desired, an isotropic O ₂ plasma etch can be used to widen the width of the bit line trench 56 beyond the lithographic capabilities of the lithographic exposure tool. An example of the technique is isotropic descum etching using oxygen plasma. It should also be noted that the perimeter and the grooves of the array preferably have the same width.

Referring to FIGS. 6 and 7, a layer 58 of insulating material, preferably SiO ₂ , is provided over the patterned and etched layers 52, 54 to a selected thickness. The selected thickness of layer 58 is less than half the first selected width "A", about 1,000.
It is preferably from angstroms to about 3,000 angstroms, most preferably about 1,500 angstroms. The insulating layer 58 is formed in the bit line groove 56.
Is narrowed to the smaller second width "B" to provide sidewall insulation between the bit line and future storage capacitors. During formation of the layers described above, the polyimide fills and remains between adjacent word lines above the first active region 48 (contact location of future storage capacitors) during oxide deposition, which , Prevent word line spacers from forming during such deposition.

With further reference to FIGS. 6 and 7, a photoresist layer 60 is applied, exposed and stripped as shown to form a first pattern of contacts 62 in the second active area of the bit line, The contacts overlap beyond the groove 56 of the bit line, both parallel to the word and bit lines. A first pattern single bit line second active area contact 62 is shown in FIG. These contacts, which are provided across the wafer of each future bit line contact, are shown clearly in the drawings. FIG. 7 also shows a single wide outline 61 of active area patterning that is repeated across the array.

Referring to FIG. 8, the photoresist layer 60 is RIE plasma etched to remove all resist on the top surface of the oxide layer 58 and only in the bit line trenches where no buried contacts are provided. The resist 60 is left.

Referring to FIG. 9, an oxide etch is performed to etch the insulating material from the base of the trench 56 of the second width bit line, exposing the second active region 46 upwards. This forms a second pattern (see plan view of FIG. 7) of contacts 64 in the second active area of the bit line, said contacts being the outlines 6 of the contacts of the second pattern.
It is inside 2. The boundary of the contact 64 is the groove 5 of the bit line.
6 (width "B") sidewalls and word line spacers of adjacent word lines. It should be noted that the first pattern of bit line contacts 62 is larger than the second pattern of bit line contacts 64 (FIG. 7). Such a technique has the advantage of forming the smaller bit line contact 64, which is subjected to additional photomasking beyond patterning (if possible) to form the contact outline 62. Without having to do so, it can have dimensions that are well below the dimensions of the smallest photo features.

After that, the resist is stripped from the wafer. Note that the oxide material on the nitride layer 54 is also preferably completely removed at this point in the process by the etch selected for nitride.

Referring to FIGS. 10 and 11, a conductively doped layer 66 is provided on the wafer,
The thickness of the layer is selected to be sufficient to fill the base of the trench 56 of the second width bit line and make electrical contact with the second active region 46 therein. The preferred thickness of polysilicon layer 66 is from about 2,000 angstroms to about 6,000 angstroms, and most preferably about 4,000 angstroms. A blanket-like polysilicon etchback is then performed, leaving approximately 1,000 angstroms of polysilicon above the word lines, filling the gaps between each word line with polysilicon, and locating such locations. The polysilicon in is thickened (see FIG. 11).

Thereafter, a conductive material having a higher conductivity than the conductively doped polysilicon, such as layer 68, is provided over the polysilicon layer 66. An example of a preferred material is a silicide such as WSi _x . The conductive material may be metallized is silicided, then either wet etching or thick CVD silicide or refractory metal deposition (e.g., WSi _x or W) is etched back and blanket, WSi the Poribitto line It can be deposited by leaving _x or W. Then, an insulating material such as oxide 68 is provided over the silicide in the trench,
The wafer is fully planarized again, preferably by a CMP process. Such treatment minimizes the distance of the silicides in the array, as opposed to the silicides on the bit lines that undulate between each word line (see Figure 11).
This reduces the resistance of the bit line.

An array of capacitors is then provided on the wafer in electrical contact with the first active area 48 (FIG. 3). In one technique for doing so, first the nitride layer 54 and the polyimide layer 52 are completely stripped from the wafer, then the storage node contacts are photoetched to deposit the storage node poly, and then Etching, dielectric deposition, then cell poly deposition, etc. However, such a technique is not very desirable because it etches the storage poly out of the deep trenches between each bit line,
Also, it is necessary to perform separate photo / etch steps for the definition of storage node contacts and storage node poly.

A more preferred technique for providing a capacitor is
It is described in the description of the US patent application filed at the same time as the US patent on which the present application is based. The above-mentioned U.S. patent application was filed by the inventor of the present application entitled "Method for forming bit line on capacitor array of memory cell", and the specification of the above-mentioned U.S. patent application is referred to herein. refer. Such a technique is shown in FIGS.
Will be described with reference to. Referring to FIGS. 12 and 13,
The nitride layer 54, the polyimide layer 52, and the layer 50 are subjected to a second patterning and etching, and the second active region 48 is
To form a buried contact opening 68. It is preferable to etch the least amount of oxide layers 69, 58 because the etch chemistry used to etch layers 54, 52 is chosen to be selective to oxide. Is. Sufficient thickness of layers 69, 58 is maintained and bit line 66 is completely insulated from storage cap (70). It should be noted that during such etching the active areas on the word line bit line contacts are not opened upwards. During such an etch, the nitride is first etched selective to the oxide, preventing etching of the oxide on top of the bit lines. After that, RIEO ₂ plasma etching is performed,
All exposed polyimide is removed and then the oxide (of layer 50) is etched to expose active area 48.

A layer of conductively doped polysilicon 70 is then applied to a selected thickness over the second patterned layer of polyimide and over the wafer in buried contact 68. Layer 70 is about 1,000
It preferably has a thickness of angstroms and can be roughened if necessary to maximize the surface area and thereby increase the capacitance.

Referring to FIG. 14, photoresist layer 71.
Is provided on the wafer and oxygen plasma etch back is performed to expose the poly outside the groove.
You can leave. Referring to FIGS. 13 and 15,
An RIE polysilicon etch is performed to form an isolated cell storage node 77 that contacts the first active area.
Alternatively, the CMP technique may be used to form the cell storage node 77 without RIE resist etchback. Such a technique is used for the polysilicon layer 7
Node 7 without any prior patterning of 0
Provides the advantage of forming 7. The remaining nitride in layer 54 is removed by a nitride etch, followed by an O ₂ plasma etch to remove the remaining polyimide layer 52. Next, all the resist is stripped from the wafer.

The dielectric layer of the capacitor cell is then provided over the individual storage nodes. Next, a polysilicon layer of the capacitor cells is applied over the dielectric layer of the capacitor cells to form an array of storage cell capacitors.

The techniques described above have various advantages. Such a technique eliminates the need for the bit line to wrap around the bit line contacts. No double spacers are formed around the word lines, resulting in a more closely packed word line. Also, patterning of storage nodes and bit lines is eliminated. Moreover, the two most difficult topological photo steps in the buried bit line flow can be done with a perfectly flat wafer. The overall stack height can be reduced without thickening the insulator below the bit lines or storage poly to withstand the long etch times associated with standard processes.

The present invention has been described in terms of particular structural and methodical features thereof. However, it should be understood that the means disclosed herein represent preferred modes for carrying out the invention, and therefore the invention is not limited to the specific features shown and described above. There is. Therefore, the present invention includes all forms or modifications that are properly interpreted based on the doctrine of equivalents.

[Brief description of drawings]

FIG. 1 is a plan view showing a bit line and a contact of the bit line on a conventional semiconductor wafer described in the section of the prior art.

FIG. 2 is a cross-sectional view of a wafer fragment processed according to the prior art described in the prior art section.

FIG. 3 is a cross-sectional view of a semiconductor wafer at one processing stage of the present invention.

4 is a cross-sectional view of the wafer of FIG. 3 at the next processing stage of FIG. 3 taken at 90 ° with respect to FIG. 3 and taken along line 4-4 of FIG.

5 is a plan view showing the wafer of FIG. 3 at the same processing stage as shown in FIG.

6 is a cross-sectional view of the wafer of FIG. 3 taken along line 6-6 of FIG. 7 in a position corresponding to FIG. 4, which is in the next processing stage of the processing stages shown in FIGS. 4 and 5; 4 shows the wafer of FIG.

7 is a processing stage corresponding to that of FIG. 6;
3 is a plan view of the wafer of FIG.

8 is a cross-sectional view of the wafer of FIG. 3 in a position corresponding to FIG. 4, showing the state in the next processing stage of the processing stage shown in FIGS. 5 and 6;

9 is a cross-sectional view of the wafer of FIG. 3 in a position corresponding to FIG. 4, showing a state in a processing stage subsequent to the processing stage shown in FIG. 8;

10 is a cross-sectional view of the wafer of FIG. 3 in a position corresponding to FIG. 4, showing the state in the next processing stage of the processing stage shown in FIG. 9;

11 is a cross-sectional view of the wafer of FIG. 3 taken along line 11-11 of FIG. 7, showing the wafer in the processing stage of FIG.

12 is a cross-sectional view of the wafer of FIG. 3 at a stage subsequent to the stage shown in FIG.
It is a figure shown along with -12.

13 is a plan view of the wafer of FIG. 3 at a processing stage corresponding to that shown in FIG.

14 is a cross-sectional view showing the wafer of FIG. 3 in a processing step subsequent to the processing steps shown in FIGS. 12 and 13,
Corresponds to position 0.

15 is a cross-sectional view of the wafer of FIG. 3 at a processing step subsequent to the processing step shown in FIG. 14, corresponding to the cross-sectional position of FIG.

[Explanation of symbols]

35 Semiconductor wafer 36, 38, 40
Word line 44 Oxide spacer 45 Oxide cap 46, 48 Active region 50 Protective barrier layer 52 First material layer 56 Groove of buried bit line 58 Insulating material layer 60 Photoresist layer 62, 64 Contact 66 Conductive doped polysilicon Layer 70 polysilicon layer 77 storage node

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 7210-4M 27/10 325 T

Claims (20)

[Claims] 1. A method of forming a buried bit line array of storage cells, wherein an array of substantially electrically isolated conductive word lines is provided on a semiconductor wafer, and the conductivity of adjacent word lines is provided. Separating the parts of the memory cell from each other by a selected separation distance, a first active region for electrically connecting with a capacitor of the memory cell, and a second active region for electrically connecting with a bit line. Forming an array of storage cell FETs by providing an active region formed by and adjacent to the word line, and selecting a first material layer that is selectively etchable with respect to oxide and polysilicon. A buried bit having a first selected width for patterning and etching the layer of first material to form a buried bit line therein. Forming a pattern of trenches in the step of: providing a layer of insulating material to a selected thickness on the wafer above the patterned and etched layer of the first material, the selected thickness being the first Smaller than the selected width of the bit line, narrowing the bit line groove to a smaller second width by the layer of insulating material, and providing a base in the smaller second width bit line groove. Applying a photoresist, exposing and stripping to form a first pattern of second active area contacts of the bit line which overlaps the groove of the bit line, and from the base of the groove of the bit line of the second width. Etching the insulating material to expose the second active region upwardly, thereby forming a second pattern of bit line second active region contacts in the first pattern; Width of 2 Received a conductive doping of a selected thickness sufficient to fill the base of the bit line trench and electrically contact the second active region therein to at least partially form the bit line. Providing a layer of polysilicon on the wafer, and depositing a conductive material having a higher conductivity than the conductively doped polysilicon in the trench of the bit line of the second width. Providing on the polysilicon in the trench of the bit line of width two, providing an insulating material on the conductive material, and electrically connecting the first active region and the electrical conductor on the bit line. Forming an array of capacitors in contact with each other, and a method of forming an embedded bit line array of storage cells. 2. The method of forming a buried bit line array of storage cells of claim 1, wherein the step of providing an insulating material over the patterned and etched layer of the first material comprises oxide. Performed by depositing, the layer of first material fills between adjacent wordlines over the first active region during the deposition, thereby allowing wordlines during the deposition. A method of forming a buried bit line array of storage cells, characterized in that spacers are prevented from being formed. 3. The method of forming a buried bit line array of storage cells according to claim 1, further comprising processing the wafer with a selected minimum photo characteristic width, the word line separation distance. A method of forming a buried bit line array of storage cells, wherein said method is equal to said minimum photo characteristic width. 4. The method of forming a buried bit line array of storage cells of claim 1, further comprising processing the wafer with a selected minimum photo characteristic width, the word line separation distance. Is equal to the minimum photo characteristic width,
Further, the step of patterning the first material and providing the insulating material on the etched layer is performed by depositing an oxide, the layer of the first material being provided during the deposition. Buried bit line of a storage cell, characterized in that it fills between adjacent word lines above the first active region, thereby preventing word line spacers from being formed during the deposition. Method of forming an array. 5. The method of forming a buried bit line array of storage cells of claim 1, wherein the selected thickness of the layer of first material is from about 3,000 angstroms to about 12,000 angstroms. A method of forming a buried bit line array of storage cells, characterized in that. 6. The method of forming a buried bit line array of storage cells according to claim 1, wherein the first pattern of bit line contacts is larger than the second pattern of bit line contacts. Etching to expose the second active region and form the second pattern,
A method of forming a buried bit line array of storage cells, which is performed without additional photomasking. 7. The method of forming a buried bit line array of memory cells of claim 1, prior to providing the layer of insulating material on the wafer within the trenches of the bit lines.
A method of forming a buried bit line array of memory cells, comprising a second etching step of patterning the first material and etching the etched layer to widen the width of the groove of the bit line. . 8. The method of forming a buried bit line array of storage cells according to claim 1, wherein the conductively doped polysilicon has a varying thickness across the wafer. Method of forming a buried bit line array of storage cells. 9. The method of forming a buried bit line array of storage cells according to claim 1, comprising the step of: providing a layer of conductively doped polysilicon in the second active region. Touching, (2) overlying the word lines, (3) filling the gap between the word lines,
A layer of conductively doped polysilicon on the wafer such that the surface of the conductively doped polysilicon is vertically above the word lines with a selected height difference. A method of forming a buried bit line array of storage cells, the method comprising the steps of: 10. A method of forming a buried bit line array of storage cells, wherein an array of substantially electrically isolated conductive word lines is provided on a semiconductor wafer, the conductivity of adjacent word lines being provided. Separating the parts of the memory cell from each other by a selected separation distance, a first active region for electrically connecting with a capacitor of the memory cell, and a second active region for electrically connecting with a bit line. Forming an array of storage cell FETs adjacent to the word lines by forming an active region formed by a. And providing a layer of a first material to a selected thickness on the wafer; Patterning and etching a layer of a first material to form a pattern of buried bit line trenches for forming buried bit lines therein; and a second active in the trenches of said bit lines. For the area The steps of providing a contact opening of Tsu DOO line, closing the base of the groove of the bit line and the second of them
A conductively doped polysilicon layer of a selected thickness sufficient to electrically contact the active region of the bit line to at least partially form a bit line on the wafer; Providing a conductive material having a higher conductivity than the conductively-doped polysilicon in the trench of the line above the polysilicon in the trench of the bit line; A method of forming a buried bit line array of storage cells, comprising: providing an insulating material on a material; and providing an array of capacitors on the bit line in electrical contact with the first active region. . 11. The method of forming a buried bit line array of storage cells according to claim 10, wherein the selected thickness of the layer of first material is from about 3,000 angstroms to about 12,000 angstroms. A method of forming a buried bit line array of storage cells, characterized in that. 12. The method of forming a buried bit line array of storage cells of claim 10, wherein the selected thickness of the layer of first material is about 5,000 angstroms. Method of forming a buried bit line array of cells. 13. The method of forming a buried bit line array of storage cells according to claim 10, wherein the conductively doped polysilicon has a varying thickness across the wafer. Method for forming a buried bit line array of storage cells. 14. The method of forming a buried bit line array of storage cells of claim 10, wherein the step of providing a layer of conductively doped polysilicon comprises (1) in the second active region. Touching, (2) overlying the word lines, (3) filling the gap between the word lines,
A layer of conductively doped polysilicon on the wafer such that the surface of the conductively doped polysilicon is vertically above the word lines with a selected height difference. A method of forming a buried bit line array of storage cells, the method comprising the steps of: 15. A method of forming a buried bit line array of storage cells, the method comprising: providing an array of substantially electrically isolated conductive word lines on a semiconductor wafer, the adjacent word lines being electrically conductive. Separating the parts of the memory cell from each other by a selected separation distance, a first active region for electrically connecting with a capacitor of the memory cell, and a second active region for electrically connecting with a bit line. Forming an array of storage cell FETs adjacent to the word lines by forming an active region formed by a. And providing a layer of a first material to a selected thickness on the wafer; Patterning and etching a layer of first material to form a pattern of buried bit line trenches having a first selected width to form a buried bit line therein; patterning and Providing a layer of insulating material on the wafer above the etched first layer of material to a selected thickness, the selected thickness of the insulating material being less than the first selected width. Narrowing the groove of the bit line to a smaller second width by the layer of insulating material and providing a base in the groove of the smaller second width bit, and the bit of the second width. Second in the groove of the wire and in the base
A contact opening for a bit line to the active region of the bit line, closing the base of the groove of the bit line, and
A conductively doped polysilicon layer of a selected thickness sufficient to electrically contact the active region of the bit line to at least partially form a bit line on the wafer; Providing a conductive material having a higher conductivity than the conductively-doped polysilicon in the trench of the line above the polysilicon in the trench of the bit line; A method of forming a buried bit line array of storage cells, comprising: providing an insulating material on a material; and providing an array of capacitors on the bit line in electrical contact with the first active region. . 16. The method of forming a buried bit line array of storage cells according to claim 15, wherein the selected thickness of the layer of first material is from about 3,000 angstroms to about 12,000 angstroms. A method of forming a buried bit line array of storage cells, characterized in that. 17. The method of forming a buried bit line array of storage cells according to claim 15, wherein the insulating material overlying the patterned and etched layer of the first material comprises SiO ₂ . A method of forming a buried bit line array of memory cells. 18. The method of forming a buried bit line array of storage cells according to claim 15, wherein said selected of said insulating material provided on said patterned and etched layer of said first material. Thickness is about 100
A method of forming a buried bit line array of storage cells, wherein the buried bit line array is from 0 to about 3000 angstroms. 19. The method of forming a buried bit line array of storage cells according to claim 15, wherein the conductively doped polysilicon has a varying thickness across the wafer. Method for forming a buried bit line array of storage cells. 20. The method of forming a buried bit line array of memory cells according to claim 15, wherein the step of providing a layer of conductively doped polysilicon comprises: (1) applying to the second active region. Touching, (2) overlying the word lines, (3) filling the gap between the word lines,
A layer of conductively doped polysilicon on the wafer such that the surface of the conductively doped polysilicon is vertically above the word lines with a selected height difference. A method of forming a buried bit line array of storage cells, the method comprising the steps of: