JPH06338512A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06338512A JPH06338512A JP12944593A JP12944593A JPH06338512A JP H06338512 A JPH06338512 A JP H06338512A JP 12944593 A JP12944593 A JP 12944593A JP 12944593 A JP12944593 A JP 12944593A JP H06338512 A JPH06338512 A JP H06338512A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- silicon nitride
- breakdown voltage
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 39
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000012360 testing method Methods 0.000 abstract description 14
- 230000015556 catabolic process Effects 0.000 description 48
- 150000002500 ions Chemical class 0.000 description 21
- 238000009792 diffusion process Methods 0.000 description 12
- 239000012535 impurity Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- -1 Na + ions Chemical class 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001953 sensory effect Effects 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- 230000001502 supplementing effect Effects 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に係り、特に
ＰＮＰ型の高耐圧プレーナトランジスタ等のＰ基板型高
耐圧半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a P-substrate type high breakdown voltage semiconductor device such as a PNP type high breakdown voltage planar transistor.
【０００２】[0002]
【従来の技術】従来の高耐圧プレーナトランジスタの構
造の一例が、例えば特公平１−３９６５８号公報に開示
されている。図５は、係る公報に開示されたＮＰＮ型の
高耐圧プレーナトランジスタの構造を示す（Ａ）は断面
図であり、（Ｂ）は平面図である。2. Description of the Related Art An example of the structure of a conventional high breakdown voltage planar transistor is disclosed in, for example, Japanese Patent Publication No. 1-39658. 5A and 5B show a structure of an NPN type high breakdown voltage planar transistor disclosed in the publication, and FIG. 5A is a sectional view and FIG. 5B is a plan view.
【０００３】Ｎ型のシリコン半導体基板１にはＰ型のベ
ース領域２及びベース領域２を取り囲むようにガードリ
ング領域５が形成されている。Ｐ型のベース領域２に
は、Ｎ + 型のエミッタ領域３が設けられ、エミッタ領域
３はエミッタ電極９とオーミック接触している。ベース
領域２はアルミ蒸着膜からなるベース電極８とオーミッ
ク接触している。コレクタ領域４の表面には、酸化膜６
が成長されており、コレクタ領域４の酸化膜６上にはシ
リコン窒化膜７が被着されている。チップの周辺には、
Ｎ+ 型のチャネルストップ領域１１が設けられ、アルミ
蒸着膜からなるシールド電極１０がチャネルストップ領
域１１にオーミック接触している。The N type silicon semiconductor substrate 1 has a P type base.
The base region 2 and the base region 2 are surrounded by guard lines.
A ring region 5 is formed. In P type base region 2
Is N + An emitter region 3 of the mold is provided, the emitter region
3 is in ohmic contact with the emitter electrode 9. base
Region 2 is the base electrode 8 made of aluminum vapor deposition film and ohmic
I'm in contact. An oxide film 6 is formed on the surface of the collector region 4.
Are grown on the oxide film 6 in the collector region 4, and
A recon nitride film 7 is deposited. Around the tip,
N+ Type channel stop region 11 is provided,
The shield electrode 10 made of a vapor deposition film is in the channel stop region.
It is in ohmic contact with the area 11.
【０００４】係る構成においてガードリング領域５は、
逆バイアス時の空乏層を均等に広がらせて高耐圧を得る
ためのものである。コレクタ領域４上の酸化膜６に設け
られたシリコン窒化膜７は、その緻密性から酸化膜６の
ピンホールによるＮ+ 型不純物の拡散を完全に防止する
ためのものである。又、シリコン窒化膜７により、Ｎａ
+ イオン等の汚染による界面の不安定性を抑えられ、空
乏層の均一な広がりを実現できる。従って、コレクタ・
ベース間耐圧およびリーク電流の劣化を防止でき、高耐
圧プレーナ型トランジスタを安定に量産できる。In such a structure, the guard ring region 5 is
This is for uniformly spreading the depletion layer during reverse bias to obtain a high breakdown voltage. The silicon nitride film 7 provided on the oxide film 6 on the collector region 4 is for completely preventing the diffusion of the N + -type impurity due to the pinhole of the oxide film 6 due to its denseness. In addition, the silicon nitride film 7 causes Na
+ Instability of the interface due to contamination with ions etc. can be suppressed, and a uniform depletion layer can be realized. Therefore, the collector
The breakdown voltage between bases and the leakage current can be prevented from deteriorating, and high breakdown voltage planar type transistors can be mass-produced in a stable manner.
【０００５】[0005]
【発明が解決しようとする課題】ＮＰＮ型の高耐圧プレ
ーナトランジスタは、上述の構造で良好な高耐圧特性が
得られる。しかしながら、ＰＮＰ型のトランジスタで
は、上述の構造を適用しても必ずしも良好な高耐圧特性
が得られない。製造直後の測定では設計値どおりの耐圧
が得られるものの、経時変化を確認するための試験、例
えば高温逆バイアス試験（ＢＴ）を行うと、耐圧の劣化
が著しく、信頼性に乏しいものとなる。これは、ＰＮＰ
型トランジスタの場合には、Ｐ型のコレクタ領域４の表
面にＮａ+ イオン等の可動イオンにより反転層が生じ、
この反転層が可動イオンの移動により状態が変化するた
めと考えられる。反転層は、逆バイアス時の空乏層を過
剰に広げる作用を有し、反転層の状態が変化すれば当然
空乏層の広がりにも影響を与える。The NPN type high breakdown voltage planar transistor can obtain good high breakdown voltage characteristics with the above-mentioned structure. However, in the PNP type transistor, good high breakdown voltage characteristics cannot always be obtained even if the above structure is applied. Although the withstand voltage according to the design value can be obtained by the measurement immediately after the manufacturing, if a test for confirming the change over time, for example, a high temperature reverse bias test (BT) is performed, the withstand voltage is significantly deteriorated and the reliability becomes poor. This is PNP
In the case of a p-type transistor, an inversion layer is generated on the surface of the p-type collector region 4 by mobile ions such as Na + ions,
It is considered that this state of the inversion layer changes due to the movement of mobile ions. The inversion layer has a function of excessively expanding the depletion layer at the time of reverse bias, and if the state of the inversion layer changes, naturally the expansion of the depletion layer is also affected.
【０００６】図４は、高温逆バイアス（ＢＴ）試験にお
ける可動イオンと反転層の移動を示す説明図である。高
温逆バイアス試験は、ＰＮＰトランジスタのコレクタ電
極１２に（−）電圧を、ベース電極８に（＋）電圧を印
加して、高温中に放置する試験である。FIG. 4 is an explanatory diagram showing the movement of mobile ions and the inversion layer in the high temperature reverse bias (BT) test. The high temperature reverse bias test is a test in which a (−) voltage is applied to the collector electrode 12 and a (+) voltage is applied to the base electrode 8 of the PNP transistor, and the PNP transistor is left at a high temperature.
【０００７】ところで、トランジスタのベース・コレク
タ間耐圧ＶCBO は、ＣＢ接合の拡散深さ、ガードリング
との距離および本数などで値が設計されている。即ち、
トランジスタの耐圧はＣＢ接合からコレクタ側へ広がる
空乏層の降伏電圧で決まり、その降伏電圧は電界集中が
生じる空乏層の湾曲部分で概ねその値が決まる。ＣＢ接
合のみの降伏電圧が例えば４００Ｖしかなく、このデバ
イスでそれ以上の耐圧を得るときは、逆バイアス電圧が
前記降伏電圧を越える直前に空乏層がガードリング５と
コレクタ４との空乏層に連結するような位置にガードリ
ング５を配置する設計とする。前記空乏層を連結するこ
とにより空乏層をコレクタ側へ一層広げることができ、
前記湾曲を緩和できるので前記ＣＢ接合だけの降伏電圧
より高い耐圧を得ることができる。より大きな耐圧を得
るときは、同様にガードリング５の本数を増加すること
になる。By the way, the value of the base-collector withstand voltage V CBO of the transistor is designed in accordance with the diffusion depth of the CB junction, the distance from the guard ring, the number of them, and the like. That is,
The breakdown voltage of the transistor is determined by the breakdown voltage of the depletion layer extending from the CB junction to the collector side, and the breakdown voltage is generally determined by the curved portion of the depletion layer where electric field concentration occurs. The breakdown voltage of only the CB junction is, for example, only 400 V, and when a higher breakdown voltage is obtained in this device, the depletion layer is connected to the depletion layer of the guard ring 5 and the collector 4 immediately before the reverse bias voltage exceeds the breakdown voltage. The guard ring 5 is designed to be placed at such a position. By connecting the depletion layer, the depletion layer can be further expanded to the collector side,
Since the bending can be relaxed, a breakdown voltage higher than the breakdown voltage of only the CB junction can be obtained. To obtain a higher breakdown voltage, the number of guard rings 5 is also increased.
【０００８】図４（Ａ）は、高温逆バイアス試験の初期
段階を示す。Ｎａ+、Ｃａ+等の可動イオン１３は酸化膜
中６に均等に存在する。コレクタ領域４の表面が理想状
態であると仮定すると、このトランジスタは上記設計値
どおりの耐圧を得ることができる。FIG. 4A shows the initial stage of the high temperature reverse bias test. Mobile ions 13 such as Na + and Ca + are evenly present in the oxide film 6. Assuming that the surface of the collector region 4 is in an ideal state, this transistor can obtain the breakdown voltage as designed above.
【０００９】しかしながら、高温逆バイアス（ＢＴ）試
験が進行すると、図４（Ｂ）に示すように、可動イオン
１３は、酸化膜６中において、コレクタ領域４との界面
側に移動してくる。これは、コレクタ領域４が（−）側
にバイアスされているため、正電荷であるＮａ+ 、Ｋａ
+ イオン等の可動イオン１３がコレクタ領域４側に引き
寄せられるためである。可動イオン１３のコレクタ領域
側への垂直方向の移動に伴い、コレクタ領域４に対する
正電荷の影響が強くなるので、コレクタ領域４表面に電
子が引き寄せられてＮ型の反転層が形成される。Ｎ型反
転層は空乏層を広げる作用を有するので、ＣＢ接合から
広がる逆バイアス時の空乏層を過剰に広げることにな
る。このことは、ＣＢ接合からコレクタ領域４側に広が
った空乏層が設計値より低い電圧で隣りのガードリング
領域５の空乏層と連結することを意味し、最終的な耐圧
は空乏層がチャネルストップ領域１１まで達した時の空
乏層が持つ降伏電圧であるから、空乏層が過剰に拡がる
ことはトランジスタの耐圧が劣化することを意味する。
従って、例えば（Ａ）の理想状態で、コレクタ・ベース
間のＶＣＢ耐圧が９００Ｖ程度であったものが、（Ｂ）
の段階では、ＶＣＢ耐圧が６００Ｖ程度に低下する。However, when the high temperature reverse bias (BT) test progresses, the movable ions 13 move to the interface side with the collector region 4 in the oxide film 6, as shown in FIG. 4B. This is because the collector region 4 is biased to the (−) side, so that positive charges of Na + and Ka are generated.
This is because the movable ions 13 such as + ions are attracted to the collector region 4 side. As the movable ions 13 move vertically to the collector region side, the influence of positive charges on the collector region 4 becomes stronger, so that electrons are attracted to the surface of the collector region 4 and an N-type inversion layer is formed. Since the N-type inversion layer has a function of expanding the depletion layer, the depletion layer at the time of reverse bias spreading from the CB junction is excessively expanded. This means that the depletion layer extending from the CB junction to the collector region 4 side is connected to the depletion layer of the adjacent guard ring region 5 at a voltage lower than the designed value, and the final breakdown voltage is the depletion layer channel stop. Since the breakdown voltage of the depletion layer reaches the region 11, the excessive expansion of the depletion layer means that the breakdown voltage of the transistor deteriorates.
Therefore, for example, in the ideal state of (A), the VCB breakdown voltage between the collector and the base was about 900 V, but (B)
At that stage, the VCB breakdown voltage drops to about 600V.
【００１０】更に高温逆バイアス（ＢＴ）試験が進行す
ると、図４（Ｃ）に示すように、可動イオン１３は酸化
膜６中をチップ周辺部のシールド電極１０に向かって移
動する。これは、シールド電極１０側にコレクタ電極１
２と同様な（−）電圧が与えられるためである。図示す
るように、可動イオン１３がシールド電極１０側の酸化
膜６中に集中してくると、それだけ正電荷の影響が強く
なるので、Ｎ型の反転層１４の状態、特に空乏層に影響
を与えることができる強さが増大する。尚、図４（Ｂ）
（Ｃ）において、反転層１４を示す点線は反転層の広が
りを示すものではなく、前記空乏層に与えることのでき
る”影響力の強さ”を感覚的に表したものである。例え
ば初段のガードリング領域５で１００Ｖ、次段で１００
Ｖ、次段からチャネル領域１１までの距離で３００Ｖの
耐圧を分担させるというように、通常はチップの最外周
部が耐圧の分担比率が高い。その分担比率の最も高い領
域に対して反転層１４の影響力が最も大きくなるので、
トランジスタ自体の耐圧が著しく劣化する。例えば、Ｖ
CB耐圧は（Ｂ）において６００Ｖ程度に劣化したもの
が、（Ｃ）の段階においては、更に４５０Ｖ程度に劣化
する。When the high temperature reverse bias (BT) test further progresses, the movable ions 13 move in the oxide film 6 toward the shield electrode 10 in the peripheral portion of the chip, as shown in FIG. 4 (C). This is the collector electrode 1 on the shield electrode 10 side.
This is because the same (-) voltage as that in 2 is applied. As shown in the figure, when the mobile ions 13 are concentrated in the oxide film 6 on the shield electrode 10 side, the influence of positive charges becomes stronger, so that the state of the N-type inversion layer 14, particularly the depletion layer, is affected. The strength that can be given increases. Incidentally, FIG. 4 (B)
In (C), the dotted line indicating the inversion layer 14 does not indicate the spread of the inversion layer, but is a sensory representation of the "influence strength" that can be given to the depletion layer. For example, 100 V in the guard ring area 5 in the first stage and 100 V in the second stage.
V, the withstand voltage of 300 V is shared by the distance from the next stage to the channel region 11, and the outermost peripheral portion of the chip usually has a high withstand voltage share. Since the influence of the inversion layer 14 is the largest on the region with the highest share,
The breakdown voltage of the transistor itself is significantly deteriorated. For example, V
The CB breakdown voltage deteriorates to about 600 V in (B), but further deteriorates to about 450 V in the stage of (C).
【００１１】本発明は、係る従来技術の問題点に鑑み、
高温逆バイアス（ＢＴ）試験においても耐圧の劣化を生
じ難い、高信頼性を有する高耐圧Ｐ基板型半導体装置を
提供することを目的とする。The present invention has been made in view of the above problems of the prior art.
It is an object of the present invention to provide a high breakdown voltage P substrate type semiconductor device having high reliability in which deterioration of breakdown voltage hardly occurs even in a high temperature reverse bias (BT) test.
【００１２】[0012]
【課題を解決するための手段】本発明の半導体装置は、
Ｐ型の半導体基板にＰＮ接合を形成するＮ型の素子拡散
領域および該素子拡散領域の周囲の基板表面に該素子拡
散領域を囲むＮ型のガードリング領域を備えた半導体装
置において、前記素子拡散領域の周囲のＰ型基板表面に
直接接触するシリコン窒化膜と、該シリコン窒化膜上に
配置された多結晶シリコン膜とを備えることを特徴とす
る。The semiconductor device of the present invention comprises:
A semiconductor device comprising an N-type element diffusion region for forming a PN junction on a P-type semiconductor substrate and an N-type guard ring region surrounding the element diffusion region on the substrate surface around the element diffusion region, It is characterized by comprising a silicon nitride film which is in direct contact with the surface of the P-type substrate around the region, and a polycrystalline silicon film arranged on the silicon nitride film.
【００１３】[0013]
【作用】シリコン窒化膜は、電子をトラップする性質を
有しているので、酸化膜と半導体基板のコレクタ領域と
の界面における可動イオンの影響を直接軽減することが
できる。シリコン窒化膜上に配置された多結晶シリコン
膜は、スペーサとしての役割を果たし、可動イオンのコ
レクタ領域近傍に移動することを防止することができ
る。係る構造により可動イオンによる反転層は発生せ
ず、高温逆バイアス試験等においても空乏層の広がり方
が変化することはない。従って、高温逆バイアス試験に
おいて高耐圧特性が劣化するという問題を生じない。Since the silicon nitride film has a property of trapping electrons, it is possible to directly reduce the influence of mobile ions at the interface between the oxide film and the collector region of the semiconductor substrate. The polycrystalline silicon film arranged on the silicon nitride film serves as a spacer and can prevent the movable ions from moving to the vicinity of the collector region. With such a structure, an inversion layer due to mobile ions does not occur, and the depletion layer spreads in the same manner even in a high temperature reverse bias test. Therefore, in the high temperature reverse bias test, the problem that the high breakdown voltage characteristic is deteriorated does not occur.
【００１４】[0014]
【実施例】以下、本発明をＰＮＰトランジスタに適用し
た場合の第１の実施例、第２の実施例を添付図１乃至図
３を参照しながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment and a second embodiment when the present invention is applied to a PNP transistor will be described below with reference to the attached FIGS.
【００１５】図１は本発明の第１の実施例のＰＮＰ型高
耐圧プレーナトランジスタの断面図であり、図２はその
チップの１／４の平面図である。このＰＮＰ型高耐圧プ
レーナトランジスタは、Ｐ+ 型の半導体基板１にＰ- 型
のコレクタ領域４及びＮ型のベース領域２を備え、ベー
ス領域にＰ+ 型のエミッタ領域３が拡散により形成され
ている。ベース領域２の周囲のＰ- 型のコレクタ領域４
には、１乃至数本のＮ型のガードリング領域５を備えて
いる。FIG. 1 is a sectional view of a PNP type high breakdown voltage planar transistor of a first embodiment of the present invention, and FIG. 2 is a plan view of a quarter of its chip. This PNP type high breakdown voltage planar transistor has a P + type semiconductor substrate 1 provided with a P − type collector region 4 and an N type base region 2, and a P + type emitter region 3 is formed in the base region by diffusion. There is. P − -type collector region 4 around the base region 2
Is provided with one to several N-type guard ring regions 5.
【００１６】該ＰＮＰトランジスタのベース領域２はコ
レクタ領域４の表面から拡散により形成されており、拡
散に伴う横方向拡散によってコレクタ・ベース間のＰＮ
接合はある曲率を持って湾曲する。この曲率によりガー
ドリング領域５がない状態でのＣＢ接合の耐圧（雪崩降
伏電圧）が概ね決定される。従って、前記ベース領域２
の拡散深さは前記ＣＢ接合の耐圧の目標値に応じた拡散
深さで設計され、例えばベース領域の拡散深さを１２μ
とすれば前記ＣＢ接合耐圧を４００Ｖ程度にできる。The base region 2 of the PNP transistor is formed by diffusion from the surface of the collector region 4, and the PN between the collector and the base is formed by the lateral diffusion accompanying the diffusion.
The joint bends with a certain curvature. This curvature generally determines the breakdown voltage (avalanche breakdown voltage) of the CB junction without the guard ring region 5. Therefore, the base region 2
Is designed to be a diffusion depth according to the target value of the breakdown voltage of the CB junction. For example, the diffusion depth of the base region is 12 μm.
Then, the CB junction breakdown voltage can be set to about 400V.
【００１７】一方、ガードリング領域５はＣＢ接合に４
００Ｖより少し低い逆バイアス電圧を印加した時に空乏
層が達する位置に配置してある。これによって、ＣＢ接
合の空乏層が降伏する直前に空乏層を外側へ拡大し、曲
率を緩和することによって耐圧を向上している。向上で
きる耐圧の値はガードリング領域５の拡散深さと幅に関
与する。ベース領域２とガードリング領域５との間隔を
約２５μとし、その幅を約３５μで形成すれば、前記Ｃ
Ｂ接合の耐圧を約１００Ｖ向上できる。同様にして次段
のガードリング領域５を間隔３５μ、幅３５μで形成し
てさらに約１００Ｖ増大させ、最終的にガードリング領
域５からチャネル領域１１までの距離を約１５０μとし
てさらに３００Ｖ向上させる。従って、最終的にこのト
ランジスタの耐圧ＶCBO は９００Ｖに設計される。On the other hand, the guard ring region 5 has four CB junctions.
It is arranged at a position where the depletion layer reaches when a reverse bias voltage slightly lower than 00V is applied. As a result, just before the depletion layer of the CB junction breaks down, the depletion layer is expanded to the outside and the curvature is relaxed, thereby improving the breakdown voltage. The value of the breakdown voltage that can be improved is related to the diffusion depth and width of the guard ring region 5. If the distance between the base region 2 and the guard ring region 5 is set to about 25 μ and the width thereof is set to about 35 μ, the above C
The breakdown voltage of the B junction can be improved by about 100V. Similarly, the guard ring region 5 of the next stage is formed with a space of 35 μ and a width of 35 μ to further increase it by about 100 V, and finally, the distance from the guard ring region 5 to the channel region 11 is set to about 150 μ to further improve it by 300 V. Therefore, the withstand voltage V CBO of this transistor is finally designed to be 900V.
【００１８】エミッタ電極９、ベース電極８、コレクタ
電極１２等の構成は、図５の従来の技術で説明した構成
と同様であり、同一部分には同一の符号を付してその説
明を省略する。The structure of the emitter electrode 9, the base electrode 8, the collector electrode 12 and the like is similar to the structure described in the prior art of FIG. 5, and the same parts are designated by the same reference numerals and the description thereof is omitted. .
【００１９】ベース領域・ガードリング領域間のコレク
タ領域４の表面には、コレクタ領域４に直接接触するシ
リコン窒化膜１５を備えている。同様に、ガードリング
領域・ガードリング領域間のコレクタ領域４の表面に直
接接触するシリコン窒化（Ｓｉ3Ｎ4）膜１５を備えてい
る。これらのシリコン窒化膜１５上にはそれぞれ多結晶
シリコン膜１６が配置されている。即ち図２に示すよう
に、ベース領域２を取り囲むＰ- 型のコレクタ領域４の
表面はすべてシリコン窒化膜１５及び多結晶シリコン膜
１６の二層膜に覆われている。The surface of the collector region 4 between the base region and the guard ring region is provided with a silicon nitride film 15 which is in direct contact with the collector region 4. Similarly, a silicon nitride (Si 3 N 4 ) film 15 is provided which is in direct contact with the surface of the collector region 4 between the guard ring regions. A polycrystalline silicon film 16 is arranged on each of these silicon nitride films 15. That is, as shown in FIG. 2, the surface of the P − type collector region 4 surrounding the base region 2 is entirely covered with a two-layer film of the silicon nitride film 15 and the polycrystalline silicon film 16.
【００２０】シリコン窒化膜１５は電子をトラップする
性質を有しているので、Ｐ- 型のコレクタ領域の表面に
おいて、半導体基板１中の電子をトラップして表面の電
子濃度を下げる。よってＮ型反転しにくくなる。多結晶
シリコン膜１６は、スペーサーとしての役割をはたし、
薄いシリコン窒化膜の厚みを補う役割を果している。従
って、酸化膜６中の正電荷を有する可動イオンは多結晶
シリコン膜１６及びシリコン窒化膜１５によりコレクタ
領域４の界面に影響を及ぼすことができず、コレクタ領
域４の表面には図４に示すようなＮ型の反転層は発生し
ない。Since the silicon nitride film 15 has a property of trapping electrons, the electrons in the semiconductor substrate 1 are trapped on the surface of the P -- type collector region to reduce the electron concentration on the surface. Therefore, it becomes difficult to invert the N type. The polycrystalline silicon film 16 serves as a spacer,
It plays a role of supplementing the thickness of the thin silicon nitride film. Therefore, the movable ions having a positive charge in the oxide film 6 cannot affect the interface of the collector region 4 by the polycrystalline silicon film 16 and the silicon nitride film 15, and the surface of the collector region 4 is shown in FIG. Such an N-type inversion layer does not occur.
【００２１】本実施例のトランジスタでは高温逆バイア
ス試験においても、前述の図４（Ｂ）、（Ｃ）に示すよ
うな酸化膜中の可動イオンのコレクタ領域界面への移動
が、多結晶シリコン膜１６及びシリコン窒化膜１５によ
って妨げられる。従って、図４（Ｂ）、（Ｃ）に示すよ
うな可動イオンの移動にともない反転層の状態（強さ）
が変化して空乏層が過剰に拡大し、耐圧の著しい劣化を
引き起こすという問題が生じない。In the transistor of this embodiment, even in the high temperature reverse bias test, the movement of the movable ions in the oxide film to the collector region interface as shown in FIGS. 4B and 4C is caused by the polycrystalline silicon film. 16 and the silicon nitride film 15. Therefore, the state (strength) of the inversion layer accompanying the movement of mobile ions as shown in FIGS.
Does not cause the problem that the depletion layer excessively expands due to the change of the temperature and causes the breakdown voltage to significantly deteriorate.
【００２２】図３は、本発明の第２の実施例のＰＮＰ型
高耐圧プレーナトランジスタの断面図である。本実施例
においては、シリコン窒化膜１５上に配置された多結晶
シリコン膜１６上に、更にシリコン窒化膜１７を配置す
る。多結晶シリコン膜１６を挟み込む構造のシリコン窒
化膜１７は、緻密な膜であるので酸化膜中の可動イオン
の界面への影響をより軽減することができる。シリコン
窒化膜１５，１７は、その膜の性質上厚く成長させるこ
とが困難である。このため、厚く成長させることが容易
な多結晶シリコン膜１６がスペーサーとしての役割を果
たす。従って、このサンドイッチ構造は、シリコン窒化
膜１５からシリコン窒化膜１７までを全てシリコン窒化
膜で形成した場合の構造と等しい機能を持つ。係るサン
ドイッチ構造によって、第１の実施例と比較して、より
強固に酸化膜中の可動イオンをコレクタ領域近傍に近づ
けないという効果を奏する。FIG. 3 is a sectional view of a PNP type high breakdown voltage planar transistor according to the second embodiment of the present invention. In this embodiment, a silicon nitride film 17 is further arranged on the polycrystalline silicon film 16 arranged on the silicon nitride film 15. Since the silicon nitride film 17 having a structure sandwiching the polycrystalline silicon film 16 is a dense film, it is possible to further reduce the influence of mobile ions in the oxide film on the interface. The silicon nitride films 15 and 17 are difficult to grow thick due to the nature of the films. For this reason, the polycrystalline silicon film 16 which can be easily grown thick serves as a spacer. Therefore, this sandwich structure has the same function as the structure in which all of the silicon nitride film 15 to the silicon nitride film 17 are formed by the silicon nitride film. With such a sandwich structure, there is an effect that the mobile ions in the oxide film are not brought closer to the vicinity of the collector region more firmly than in the first embodiment.
【００２３】本実施例のトランジスタの製造工程は、シ
リコン窒化膜１５、多結晶シリコン膜１６、或いはシリ
コン窒化膜１７の多層膜を形成する工程を除いて、通常
のＰＮＰ型高耐圧プレーナトランジスタの製造工程と同
じである。シリコン窒化膜１５と多結晶シリコン膜１６
の多層膜は、一例として、Ｐ+ 型のエミッタ領域等の形
成後、ベース・ガードリング間及びガードリング・ガー
ドリング間のコレクタ領域上の酸化膜をホトリソグラフ
ィにより開口する。そして、気相成長（ＣＶＤ）により
シリコン窒化膜、多結晶シリコン膜、或いは上面のシリ
コン窒化膜の２層乃至３層の多層膜を被着する。そして
図示するようなパターン形状１５，１６にホトリソグラ
フィにより形成する。全面をＣＶＤ酸化膜で被覆し、該
酸化膜に電極コンタクト孔を形成してベース、エミッタ
電極等を配置する。その後はシリコン窒化膜等のファイ
ナルパッシベーション被膜を形成して本実施例のトラン
ジスタが完成する。なお、シリコン窒化膜１５、多結晶
シリコン膜１６或いはシリコン窒化膜１７の形成は、ベ
ース領域等のＮ型領域の形成前に行っても良い。The manufacturing process of the transistor of this embodiment is the same as the manufacturing process of a normal PNP type high breakdown voltage planar transistor except for the process of forming a multilayer film of the silicon nitride film 15, the polycrystalline silicon film 16 or the silicon nitride film 17. The process is the same. Silicon nitride film 15 and polycrystalline silicon film 16
For example, after forming the P + -type emitter region, the oxide film on the collector region between the base and the guard ring and between the guard ring and the guard ring is opened by photolithography. Then, a silicon nitride film, a polycrystalline silicon film, or a multilayer film of two to three layers of a silicon nitride film on the upper surface is deposited by vapor phase epitaxy (CVD). Then, pattern shapes 15 and 16 as shown are formed by photolithography. The entire surface is covered with a CVD oxide film, an electrode contact hole is formed in the oxide film, and a base, an emitter electrode, etc. are arranged. After that, a final passivation film such as a silicon nitride film is formed to complete the transistor of this embodiment. The silicon nitride film 15, the polycrystalline silicon film 16, or the silicon nitride film 17 may be formed before the N-type region such as the base region is formed.
【００２４】以上の実施例はＰＮＰ型トランジスタにつ
いて述べてきたが、ダイオード、パワーＭＯＳＦＥＴ、
ＩＧＢＴなどの、基本がＰ型となりガードリング領域を
有するデバイスにも適用可能である。例えばダイオード
の場合は、Ｐ型基板表面にベース領域と同様にカソード
領域を形成し、基板をアノードとして構成するもので、
カソード領域周辺のガードリング部分のＰ型不純物層１
６の構成は図１と同等である。Although the above embodiments have described the PNP type transistor, the diode, the power MOSFET,
It is also applicable to devices such as IGBTs, which are basically P-type and have a guard ring region. For example, in the case of a diode, a cathode region is formed on the surface of a P-type substrate similarly to the base region, and the substrate is configured as an anode.
P-type impurity layer 1 in the guard ring part around the cathode region
The configuration of 6 is the same as that of FIG.
【００２５】パワーＭＯＳＦＥＴに前記第１の実施例を
適用した場合は、図６に示すように、基板１０１を共通
ドレインとし、基板表面にＭＯＳ素子を形成するための
Ｎ型ベース領域１０２、Ｐ＋型ソース領域１０３を形成
し、ベース領域１０２のチャネル領域１０４の上にゲー
ト酸化膜１０５を介してポリシリコンゲート電極１０６
を配置し、ベース領域１０２とソース領域１０３との両
方にコンタクトするＡ１ソース電極を形成したものであ
る。そして、ベース領域１０２の周囲にＮ型ガードリン
グ領域を形成し、本発明の特徴となるシリコン窒化膜１
５、多結晶シリコン膜１６或いはシリコン窒化膜１７を
設ける。ＩＧＢＴの場合は、基板がＰ＋／Ｎ＋／Ｎ型構
造となり、Ｎ型層の表面にＭＯＳ素子が作り込まれる。
いずれにしろ異なるのは素子構造の部分であり、空乏層
が拡がるＰＮ接合周囲に設けたガードリング領域５とＰ
型不純物層１６、ガードリング領域５の上の膜構造は同
一であるWhen the first embodiment is applied to the power MOSFET, as shown in FIG. 6, the substrate 101 is used as a common drain, and an N-type base region 102 for forming a MOS element on the surface of the substrate and a P + type are formed. A source region 103 is formed, and a polysilicon gate electrode 106 is formed on a channel region 104 of the base region 102 with a gate oxide film 105 interposed therebetween.
And the A1 source electrode that contacts both the base region 102 and the source region 103 is formed. Then, an N-type guard ring region is formed around the base region 102 to form the silicon nitride film 1 which is a feature of the present invention.
5. A polycrystalline silicon film 16 or a silicon nitride film 17 is provided. In the case of the IGBT, the substrate has a P + / N + / N type structure, and a MOS element is formed on the surface of the N type layer.
In any case, the difference is the part of the device structure, that is, the guard ring regions 5 and P provided around the PN junction in which the depletion layer extends.
The film structures on the type impurity layer 16 and the guard ring region 5 are the same.
【００２６】[0026]
【発明の効果】以上に説明したように、本発明はＰ基板
型高耐圧素子のガードリング上に酸化膜を分断するベー
ス領域の周囲のコレクタ領域の表面に直接接触するシリ
コン窒化膜と、シリコン窒化膜上に配置された多結晶シ
リコン膜を備えるものである。これにより、酸化膜中の
可動イオンの移動をコレクタ領域界面に近づけないよう
に阻止することができる。コレクタ領域表面には、反転
層が形成されず、耐圧の劣化という問題を生じない、高
信頼性のＰ基板型半導体装置を提供することができる。As described above, according to the present invention, the silicon nitride film, which directly contacts the surface of the collector region around the base region that divides the oxide film on the guard ring of the P substrate type high breakdown voltage element, and the silicon It is provided with a polycrystalline silicon film arranged on the nitride film. As a result, the movement of mobile ions in the oxide film can be blocked so as not to approach the collector region interface. It is possible to provide a highly reliable P substrate type semiconductor device in which the inversion layer is not formed on the surface of the collector region and the problem of deterioration of breakdown voltage does not occur.
【図１】本発明の第１の実施例のＰＮＰ型高耐圧プレー
ナトランジスタの断面図。FIG. 1 is a sectional view of a PNP type high breakdown voltage planar transistor according to a first embodiment of the present invention.
【図２】本発明の一実施例のＰＮＰ型高耐圧プレーナト
ランジスタのチップの１／４の平面図。FIG. 2 is a quarter plan view of a chip of a PNP type high breakdown voltage planar transistor according to an embodiment of the present invention.
【図３】本発明の第２の実施例のＰＮＰ型高耐圧プレー
ナトランジスタの断面図FIG. 3 is a sectional view of a PNP type high breakdown voltage planar transistor according to a second embodiment of the present invention.
【図４】高温逆バイアス（ＢＴ）試験における可動イオ
ンと反転層の移動を示す説明図。FIG. 4 is an explanatory diagram showing movement of mobile ions and an inversion layer in a high temperature reverse bias (BT) test.
【図５】従来のＮＰＮ型高耐圧プレーナトランジスタの
断面図。FIG. 5 is a cross-sectional view of a conventional NPN type high breakdown voltage planar transistor.
【図６】本発明を適用したパワーＭＯＳＦＥＴを示す断
面図。FIG. 6 is a sectional view showing a power MOSFET to which the present invention is applied.
Claims (2)
び該ベース領域の周囲のコレクタ領域に該ベース領域を
取囲むＮ型のガードリング領域を備えた半導体装置にお
いて、前記コレクタ領域の表面に直接接触するシリコン
窒化膜と、該シリコン窒化膜上に配置された多結晶シリ
コン膜とを備えることを特徴とする半導体装置。1. A semiconductor device comprising a P-type semiconductor substrate and an N-type base region and an N-type guard ring region surrounding the base region in a collector region around the base region, the surface of the collector region. A semiconductor device comprising: a silicon nitride film that is in direct contact with the silicon nitride film; and a polycrystalline silicon film disposed on the silicon nitride film.
晶シリコン膜上には、更にシリコン窒化膜が配置されて
いることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein a silicon nitride film is further arranged on the polycrystalline silicon film arranged on the silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12944593A JPH06338512A (en) | 1993-05-31 | 1993-05-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12944593A JPH06338512A (en) | 1993-05-31 | 1993-05-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06338512A true JPH06338512A (en) | 1994-12-06 |
Family
ID=15009654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12944593A Pending JPH06338512A (en) | 1993-05-31 | 1993-05-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06338512A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999052150A1 (en) * | 1998-04-03 | 1999-10-14 | Zetex Plc | Guard structure for bipolar semiconductor device |
| US8390069B2 (en) | 2008-11-13 | 2013-03-05 | Mitsubishi Electric Corporation | Semiconductor device |
-
1993
- 1993-05-31 JP JP12944593A patent/JPH06338512A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999052150A1 (en) * | 1998-04-03 | 1999-10-14 | Zetex Plc | Guard structure for bipolar semiconductor device |
| GB2340660A (en) * | 1998-04-03 | 2000-02-23 | Zetex Plc | Guard structure for bipolar semiconductor device |
| GB2340660B (en) * | 1998-04-03 | 2002-11-27 | Zetex Plc | Guard structure for bipolar semiconductor device |
| US8390069B2 (en) | 2008-11-13 | 2013-03-05 | Mitsubishi Electric Corporation | Semiconductor device |
| US8853737B2 (en) | 2008-11-13 | 2014-10-07 | Mitsubishi Electric Company | Semiconductor device |
| US9276094B2 (en) | 2008-11-13 | 2016-03-01 | Mitsubishi Electric Corporation | Semiconductor device |
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