JPH06334967A - Digital video signal recording and reproducing devices - Google Patents

Abstract

PURPOSE:To use a circuit in common for the case of recording of a current television(TV) signal and the case of recording of a digital HDTV signal and to obtain superior picture quality even in the case of executing the variable speed reproduction of the HDTV signal by dividing the HDTV signal into three coding buses to perform processing of the divided signals and making two channels of respective data. CONSTITUTION:A serial parallel conversion circuit 7 divides a screen consisting of (1080 the effective number of samples X1024 the effective number of lines) into three coding buses CP-A to CP-C. The transmission rate of data consisting of a luminance signal Y and color difference signals PR, PB in one of the coding buses CP-A to CP-C is reduced to 1/3, which is equal to current sampling frequency. Thereby the processing circuit is used in common. Data coded by the three coding buses CP-A to CP-C are divided into two channels and recorded in a magnetic tape by four rotary heads 20A, 20B, 21A, 21B. In this case, collected data are obtained at the time of variable speed reproduction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal recording apparatus and a reproducing apparatus suitable for use in a digital VTR which compresses a digital video signal by DCT conversion and records it on a magnetic tape by a rotary head.
In particular, the present invention relates to standardization of processing when recording and reproducing HDTV signals and improvement of image quality during variable speed reproduction.

[0002]

2. Description of the Related Art A digital video signal is converted into a DCT (Disc
Development of a digital VTR for converting a signal in the frequency domain by rete cosine transform), compressing by a variable length code, and recording on a magnetic tape by a rotary head is in progress. FIG. 33 shows such a conventional digital VT.
2 shows the configuration of an R recording system. In this example, the video signal of the current television system such as NTSC system or PAL system is recorded by the component system.

In FIG. 33, 101 is an input terminal for the luminance signal Y, and 102 and 103 are color difference signals RY and BY.
Input terminal, 104 is an A / D converter for digitizing an analog luminance signal, and 105 is an analog color difference signal R-
It is an A / D converter that digitizes Y and BY. The luminance signal from the input terminal 101 is digitized by the A / D converter 104 at a sampling frequency of 13.5 MHz. Color difference signal R from the input terminal 102
-Y and BY are digitized by the A / D converter 105 at a sampling frequency of 6.75 MHz. Therefore, the amount of information of the luminance signal Y is 4 and the amount of information of the color difference signals U and V is 2 as the so-called (4, 2, 2) component video signals.

Reference numeral 106 is a thinning-out and line-sequencing circuit.
The thinning-out and line-sequencing circuit 106 uses the A / D converter 1
The number of samples of the color difference signals R-Y and B-Y digitized in 05 is thinned out to 1/2 in the vertical direction to obtain the color difference signal R-Y.
Y and BY are line-sequential. Therefore, the so-called 4:
The sampling structure is 2: 0.

Reference numeral 107 is a blocking and shuffling circuit. The blocking and shuffling circuit 107 performs shuffling in units called macroblocks. That is, 8 pixels in the horizontal direction and 8 pixels in the vertical direction
One DCT block which is a unit of T conversion is configured. Furthermore, four DCT blocks of the luminance signal and 1 of each of the RY signal and the BY signal at the same position as the DCT block.
1 from a total of 6 DCT blocks with one DCT block
One macroblock is constructed. Shuffling is performed for each macro block. Shuffling is performed so that the image is compressed uniformly over the entire screen.

Reference numeral 108 is a DCT conversion circuit, 109 is a buffer circuit, 110 is a quantizer, and 111 is an estimator. The output of the blocking and shuffling circuit 108 is supplied to the DCT conversion circuit 108. DCT conversion circuit 1
08 transforms the time domain sample data consisting of 8 pixels in the horizontal direction and 8 pixels in the vertical direction into data in the frequency domain by the two-dimensional discrete cosine transform. The DCT-converted data is supplied to the buffer 109 and
It is supplied to the estimator 111.

The buffer 109 has a buffer amount of a predetermined buffer unit. Here, this buffer 10
The buffer unit of 9 is equivalent to 5 macroblocks (equal to 5 sync blocks). The estimator 111 quantizes the data in the predetermined buffer unit with a quantizer and estimates how much the code amount will be when variable length coding is performed. Then, the optimum quantization table is determined.

The quantizer 110 is provided with various quantization tables. From these quantization tables, the estimator 111 sets the optimum quantization table for keeping the total code amount in the buffer unit to a predetermined amount or less. The DCT conversion data stored in the buffer 109 is quantized by the quantizer 110.

Reference numeral 112 is a variable length coding circuit. The variable length coding circuit 112 is for variable length coding the data. A two-dimensional Huffman code is used as the variable length code.

Reference numeral 113 is a framing circuit. The framing circuit 113 attaches a sync of a predetermined pattern to the head of the recording data, performs error correction coding processing, and expands the recording data into frames. The output of the variable length coding circuit 112 is framed by the framing circuit 113. In this example, data for one macrobook is mainly arranged in one sync block.

Reference numeral 114 is a channel encoder. The data framed by the framing circuit 113 is supplied to the channel encoder 114 and modulated by a predetermined modulation method. The output of the channel encoder 114 is output to the rotary head 1 via the recording amplifiers 115A and 115B.
16A and 116B. Rotating head 116A
And 116B, the video signal is compressed and recorded on a magnetic tape (not shown).

The rotary heads 116A and 116B are shown in FIG.
As shown in FIG. 4, it is arranged so as to face the rotary drum 117. The rotary head 116A and the rotary head 116B have different azimuth angles. The rotary drum 117 is
It is rotated at 150 Hz. Therefore, for example, when an NTSC video signal with a field frequency of 60 Hz is recorded, the number of tracks per frame is 10. Further, for example, when a PAL video signal having a field frequency of 50 Hz is recorded, the number of tracks per frame is 12 tracks.

[0013]

The above-mentioned conventional example is based on NT.
A video signal of a current television system such as an SC system or a PAL system is DCT-converted, variable-length coded, and recorded. With such a digital VTR,
It has been proposed to be able to record DTV (High Definition Television) signals. Two rotary heads 116A and 116B are used to record a video signal of the current television system, but the number of rotary heads arranged on the rotary drum is increased to four in order to record the HDTV signal. . When the HDTV signal is recorded, the tape traveling speed is set to be twice the tape traveling speed when the video signal of the current television system is recorded.

As described above, when the HDTV signal can be recorded, the circuit scale can be reduced if it can be shared with the circuit part for recording the current NTSC or PAL video signal.

Further, in such a digital VTR,
It is required that variable speed reproduction with good image quality can be performed. Therefore, when an HDTV signal is recorded by such a digital VTR, it is necessary to consider the data arrangement on the track so that a good image quality can be obtained during variable speed reproduction.

Therefore, an object of the present invention is to provide a digital video signal recording apparatus and a reproducing apparatus in which circuits can be made common when recording a current television signal and when recording an HDTV signal. To provide.

Another object of the present invention is to provide a digital video signal recording apparatus and a reproducing apparatus capable of obtaining a good image quality even when a variable speed reproduction of an HDTV signal is performed.

[0018]

SUMMARY OF THE INVENTION The present invention collects digital video signals in a predetermined buffer unit, compresses and codes so that the code amount in a predetermined buffer unit becomes a predetermined value or less, and compression-encodes the signal. In a digital video signal recording apparatus having a coding path for framing a frame and a recording means for recording a signal compression-coded by the coding path on a magnetic tape by a rotary head, a plurality of coding paths are provided and an input digital video signal is input. When recording a digital HDTV signal, it has means for dividing into a plurality of coding paths and means for converting the outputs of the plurality of coding paths into two channels.
A digital video signal recording apparatus, characterized in that a digital HDTV signal is divided into a plurality of coding paths, compression-encoded by the plurality of coding paths, and then recorded into two channels.

In the present invention, the coding path is composed of three coding paths, and the digital HDTV signal is divided into three coding paths and compression-coded.

According to the present invention, when the data compressed and encoded by a plurality of coding passes is converted into two channels, the data collected on the screen in the range on the tape corresponding to the portion to be reproduced in burst at the time of variable speed reproduction. The data is allocated so that are arranged.

The present invention comprises means for reproducing the compressed digital video signal recorded on the magnetic tape, and a decoding path for deframing the reproduced signal, expanding the compressed digital video signal, and decoding the digital video signal. In the digital video signal reproducing apparatus having the above, a plurality of decoding paths are provided, a means for outputting a reproduced signal of two channels to the plurality of decoding paths, and a signal decoded by the plurality of decoding paths is combined into a signal for one screen. When reproducing a digital HDTV signal, the reproduction signal of 2 channels is divided into a plurality of decoding paths and output, and the reproduction signal is divided into a plurality of pieces by a plurality of decoding paths and decoded. And combine signals decoded by multiple decoding paths It has to reproduce a picture signal Te is a digital video signal reproducing apparatus according to claim.

[0022]

When the digital HDTV signal is recorded, 3
The processing is performed by dividing it into one coding pass. As a result, in each coding pass, NTSC or PA
The compression encoding can be performed by the same processing as in the case of recording the current television signal such as the L system.

The digital video signal compression-coded in the three coding passes is converted into two channels and recorded on the magnetic tape by the four rotary heads. At this time, the data is allocated so that the adjacent portions on the screen are also on the tape. For this reason, the screen of the portion fixed on the screen can be reproduced from the signal reproduced in the variable speed reproduction, and the image quality in the variable speed reproduction can be improved.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In one embodiment of the present invention, a baseband digital HDTV signal is DCT-converted, variable-length coded, and recorded / reproduced.

The development of HDTV is being advanced in each country. This HDTV system is different in Japan, America and Europe. The HDTV system in Japan has 1125 scanning lines and a field frequency of 60 Hz. In Japan, the MUSE method of band-compressing an HDTV signal and transmitting it in analog has been realized. Such an HDTV baseband signal is hereinafter referred to as (1125/60) HDT
Let's call it V signal.

In the United States, an AT that performs all signal processing and transmission of HDTV signals digitally and transmits by terrestrial waves.
The V method is under consideration. In the US ATV, the number of scanning lines is 1050 and the field frequency is 59.94 Hz. Hereinafter, such a HDTV baseband signal will be referred to as a (1050/60) HDTV signal.

In Europe, an HD-MAC system for compressing an HDTV signal and transmitting it in analog is being studied. In Europe's HD-MAC system, the number of scanning lines is 1.
The number of lines is 250 and the field frequency is 50 Hz.
Such an HDTV signal is referred to below as (1250/50)
It will be called an HDTV signal.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, reference numeral 1 is an input terminal for an HDTV luminance signal Y, and 2 and 3 are input terminals for an HDTV color difference signals PR and PB.

Reference numeral 4 is an A / D converter for digitizing the analog luminance signal, and 5 is the analog color difference signals PR and PB.
Is an A / D converter that digitizes the. The luminance signal Y from the input terminal 1 is digitized by the A / D converter 4 at a sampling frequency of 40.5 MHz. The color difference signals PR and PB from the input terminal 2 are A / D
Sampling frequency of 20.25MHz with converter 5
Digitized in.

Reference numeral 6 is a thinning-out and line-sequencing circuit. The thinning-out and line-sequencing circuit 6 thins out the number of samples of the color difference signals PR and PB digitized by the A / D converter 5 in the vertical direction to 1/2, and line-sequentializes the color difference signals PR and PB. The output of the A / D converter 5 is supplied to the thinning-out and line-sequencing circuit 6.

Reference numeral 7 is a serial-parallel conversion circuit. The serial-parallel conversion circuit 7 receives the luminance signal Y from the A / D converter 4 and the color difference signals PR and PB from the thinning-out and line-sequencing circuit 6 into three coding paths CP-A, CP-B and CP, respectively. -C. That is, as described later, for example, (1125
/ 60) For HDTV signals, the number of effective samples per line is 1080 and the number of effective lines is 102, as shown in FIG.
Processed as 4. The serial-parallel conversion circuit 7 divides this (1080 × 1024) screen into three coding paths CP-A, CP-B, and CP-C. 3A shows a sub-screen of the coding path CP-A at this time, FIG. 3B shows a sub-screen of the coding path CP-B, and FIG. 3C shows a sub-screen of the coding path CP-C. In FIG. 2, “A” indicates a portion processed by the coding path CP-A, and “B” indicates a coding path CP.
The part processed in -B, and shown as "C" is the part processed in coding path CP-C.

Thus, the three coding paths CP-
By dividing into A, CP-B, and CP-C, the data transmission rate of the luminance signal Y and the color difference signals PR and PB in one coding path CP-A, CP-B, and CP-C is 1.
It can be lowered to / 3. That is, each coding pass CP
The transmission rate of the luminance signal Y in the -A, CP-B, and CP-C paths is 13.5 MHz, and the color difference signals PR and PB
The data transmission rate is 1/4. Since the transmission rate can be reduced, it is not necessary to use high speed elements.
At the same time, the transmission rate of 13.5 MHz is equal to the sampling frequency for component recording of the current television signal. Therefore, the processing circuit can be shared.

In FIG. 1, 8A, 8B and 8C are blocking and shuffling circuits. The blocking and shuffling circuits 8A, 8B and 8C are for performing shuffling. That is, one pixel of the DCT conversion, which is a unit of DCT conversion, is composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction.
Blocks are constructed. Furthermore, the four DCs of the luminance signal Y
A total of 6 DCT of the T block and one DCT block of each of the color difference signals PR and PB at the same position as the T block
One macroblock (MB) is composed of blocks. Usually, shuffling is performed in units of this macroblock. Shuffling is performed so that the image is compressed uniformly over the entire screen.

For example, (1125)
/ 60) HDTV signals, the number of macroblocks in one screen is (67.5 × 64), which is 1 when processed with three coding paths CP-A, CP-B, and CP-C.
The number of macroblocks in one sub-screen is (22.5 × 64), as shown in FIGS. 3A to 3C.

As will be described later, (1125 /
60) In case of HDTV signal, 5 sync blocks (S
B) corresponds to 8 macroblocks, and (1050/6
0) HDTV signal and (1250/50) HD
In the case of a TV signal, 5 sync blocks correspond to 7.5 macro blocks. Then, 5 sync blocks have a fixed code length. Therefore, in the block formation and shuffling circuits 8A, 8B, and 8C, (1125/60) HDT
In the case of V signal, 8 macroblocks are shuffled and collected for every 5 sync blocks. In addition, (1
050/60) HDTV signal, and (1250 /
50) For HDTV signals, 7.5 macroblocks are shuffled and collected for every 5 sync blocks.

9A, 9B and 9C are DCT conversion circuits and 10
A, 10B, 10C are buffer circuits, 11A, 11B,
Reference numeral 11C is a quantizer, and 12A, 12B and 12C are estimators. Blocking and shuffling circuit 8A-
The outputs of 8C are supplied to the DCT conversion circuits 9A to 9C, respectively. The DCT transform circuits 9A to 9C use a two-dimensional discrete cosine transform to transform one block of sample data in the time domain consisting of 8 pixels in the horizontal direction and 8 pixels in the vertical direction.
Convert to frequency domain data. The DCT-converted data is zigzag-scanned and read, supplied to the buffers 10A to 10C, and supplied to the estimators 12A to 12C, respectively.

The buffers 10A to 10C have a predetermined buffer amount. The buffer capacity of each of the buffers 10A to 10C is set to 5 sync blocks so as to be equal to the buffer capacity when recording a signal of the current television system.

The number of macroblocks corresponding to these 5 sync blocks depends on the (1125/60) HDTV signal, the (1050/60) HDTV signal, and the (1250/50) HDTV signal. , Each is different. As explained later, (1125/60)
In the case of an HDTV signal, 5 sync blocks correspond to 8 macro blocks. In the case of (1050/60) HDTV signal and in the case of (1250/50) HDTV signal, 5 sync blocks correspond to 7.5 macroblocks.

The estimators 12A to 12C store the data of the predetermined buffer unit (5 sync blocks),
Quantization is performed by a certain quantizer, and the amount of code when variable length coding is performed is estimated, and an optimum quantization table is determined so that a predetermined buffer unit has a code of a predetermined amount or less. Various quantizer tables are prepared for the quantizers 11A to 11C. Among these quantization tables, the quantization tables for making the total code amount of each buffer unit a predetermined amount or less are estimators 12A to 12A-1.
Set by 2C. The DCT conversion data stored in the buffers 10A to 10C are stored in the quantizers 11A to 11A.
It is quantized by 11C.

Reference numerals 13A to 13C are variable length coding circuits. The variable length coding circuits 13A to 13C are for variable length coding data. A two-dimensional Huffman code is used as the variable length code.

14A to 14C are framing circuits.
The framing circuits 14A to 14C add a predetermined pattern sync to the head of the recording data, perform error correction coding processing, and expand the recording data into frames. The outputs of the variable length coding circuits 13A to 13C are the framing circuits 14A to 14C.
Framed at 14C.

Reference numerals 15A, 15B and 15C are deshuffling circuits. Deshuffling circuits 15A, 15B, 15
By C, each sync block is deshuffled before recording.

Reference numeral 16 is a 3-channel / 2-channel conversion circuit. This 3 channel / 2 channel conversion circuit 1
6 includes three coding paths CP-A, CP-B and CP framed by the framing circuits 14A to 14C.
-C data is provided. The 3-channel / 2-channel conversion circuit 16 uses these three coding paths CP.
-A, CP-B, CP-C data is converted into data of two channels.

3 channel / 2 channel conversion circuit 16
Is supplied to the channel encoders 17A and 17B. 3 with channel encoders 17A and 17B
The output of the channel / 2 channel conversion circuit 16 is modulated by a predetermined modulation method. The output of the channel encoder 17A is supplied to the rotary heads 20A and 21A via the recording amplifiers 18A and 19A. The output of the channel encoder 17B is supplied to the rotary heads 20B and 21B via the recording amplifiers 18B and 19B.

As shown in FIG. 4, the rotary heads 20A and 2
0B is arranged closer to the double azimuth head structure, and rotary heads 21A and 21B are arranged closer to each other due to the double azimuth head structure. Rotating head 2
0A and 20B and rotary heads 21A and 21B face each other. The rotary heads 20A and 21A and the rotary heads 21A and 21B have different azimuth angles. Rotating heads 20A and 20B, 21A and 21B
Thus, the video signal is compressed and recorded on the magnetic tape (not shown).

The rotary drum 22 is rotated at 150 Hz. The magnetic tape is run twice as fast as when recording a signal of the current television system. When a (1125/60) HDTV signal and a (1050/60) HDTV signal with a field frequency of 60 Hz are recorded,
The number of tracks per frame is 20 tracks.
In addition, the field frequency of 50Hz (1250/50)
When an HDTV signal is recorded, the number of tracks per frame is 24 tracks.

First, used in Japan (1125/6
0) A case of recording an HDTV signal will be described. In this method, the number of effective samples per line is 108
When the number is 0, the number of effective lines per frame is 1024. As shown in FIG. 5, one macroblock is composed of 4DCT blocks of luminance signals Y0, Y1, Y2 and Y3 and 1DCT blocks of color difference signals Pr and Pb at the same position, and each 1DCT block is (8 × 8) Pixels. From this, the number of macroblocks arranged in one frame is calculated as follows: 1080/16 = 67.5 1024/16 = 64. Therefore, in the case of a (1125/60) HDTV signal, the number of macroblocks per frame is (6
7.5 × 64).

For (1125/60) HDTV signals, 1
The number of tracks per frame is 20 tracks. As described above, when recording the current television signal, 135 sync blocks are arranged per track. In order to make it common with the processing at this time, (1125 /
60) The number of sync blocks per track is set to 135 even when an HDTV signal is recorded. Further, when recording a current television signal, the buffer unit having a fixed length is 5 sync blocks. (1125/60) HDTV for common processing
Even when the signal is recorded, the buffer unit having a fixed length is set to 5 sync blocks.

As described above, in order to record 5 sync blocks in a buffer unit and record 135 sync blocks in one track, how many macro blocks should be collected to collect data for 5 sync blocks in a buffer unit. Ask for.

For (1125/60) HDTV signals, 1
There are 20 tracks per frame, 1
Since the number of macroblocks per frame is 64 × 67.5 = 4320, the number of macroblocks per track is 4320/20 = 216. The number of sync blocks per track is 135
Since the number of macro blocks per track is 216, the number of macro blocks per 5 sync blocks is 8. From this, (1125/60) HDTV
For the signal, processing may be performed so as to collect 8 macro blocks per 5 sync blocks.

Thus, (1125/60) HDTV
With respect to the signal, shuffling processing for collecting 8 macroblocks per 5 sync blocks is performed by the blocking and shuffling circuits 8A, 8B and 8C. Then, 8 macroblocks are fixed in length. The processing at this time will be described.

In this embodiment, the processing is divided into three coding paths CP-A, CP-B and CP-C. In the (1125/60) HDTV signal, the number of macroblocks is (67.5 × 64). When this is divided into three coding paths CP-A, CP-B, and CP-C and processed in parallel, one sub-screen is as shown in FIG.
It becomes a (22.5 × 64) macro block. As shown in FIG. 7, this sub-screen is divided into 10 parts in the vertical direction and 8 parts in the horizontal direction. As a result, super macroblocks indicated by the diagonal lines in the figure are obtained. As shown in FIG. 8, one super macroblock is composed of 18 macroblocks. The supermacroblock at the right end of the screen is combined with the upper and lower areas of the screen to form one supermacroblock. That is, as shown in FIG. 9, the super macro block is configured by combining the right end (FIG. 9A) and the upper and lower areas of the screen (FIG. 9B, 9C, or 9D). 9B and 9B are displayed in the upper and lower areas of the screen.
C or three types occur as shown in FIG. 9D.

At the time of shuffling, one macroblock is collected from each super macroblock in the order shown by the arrow in FIG. However, the super-macro block on the right end is shown in Fig. 9 from the area combined with the upper and lower areas.
They are collected in the order shown in. In this way, 8
One macroblock is collected from each of the super macroblocks at a certain location, and a fixed length is formed with a total of 8 macroblocks.
FIG. 11 shows the relationship between these 8 macroblocks and sync blocks.

Frame forming circuits 14A, 14B, 14C
Expands data of 8 macroblocks per 5 sync blocks into a frame, as shown in FIG. As shown in FIG. 12, a sync S having a fixed pattern is provided at the head of each sync block, followed by an ID data ID and a quantization table number QNO. Following this, luminance signal data Y and color difference signal data Pr and Pb are provided and parity is added.

Next, it is used in the United States (1050 /
50) A case of recording an HDTV signal will be described.
In this method, the number of effective samples per line is 10
At 80, the number of effective lines per frame is set to 960. From this, the number of macroblocks arranged in one frame is calculated as follows: 1080/16 = 67.5 960/16 = 60. Therefore, the number of macroblocks per frame is (67.5 × 60).

For (1050/60) HDTV signals, 1
The number of tracks per frame is 20 tracks. When recording a current television signal, 135 sync blocks are arranged per track. In order to be common to the processing at this time, the number of sync blocks per track is set to 135 even when a (1050/60) HDTV signal is recorded. Further, when recording a current television signal, the buffer unit having a fixed length is 5 sync blocks. In order to standardize the processing, even when a (1050/60) HDTV signal is recorded, the buffer unit having a fixed length is 5 sync blocks.

As described above, in order to record 5 sync blocks per buffer as 135 sync blocks per track, how many macro blocks should be collected to collect data for 5 sync blocks per buffer. Ask.

For (1050/60) HDTV signals, 1
There are 20 tracks per frame, 1
Since the number of macroblocks per frame is 60 × 67.5 = 4050, the number of macroblocks per track is 4050/20 = 202.5. The number of sync blocks per track is 135
The number of macroblocks per track is 202.5
Therefore, the number of macroblocks per 5 sync blocks is 7.5. From this, (1050/60)
For HDTV signals, processing may be performed so that 7.5 macroblocks are collected per 5 sync blocks.

Thus, (1050/60) HDTV
With respect to the signal, the shuffling process for collecting 7.5 macro blocks per 5 sync blocks is performed by the blocking and shuffling circuits 8A, 8B, and 8C. And
7.5 macroblocks have a fixed length. The processing at this time will be described.

In the (1050/60) HDTV signal, the number of macroblocks is (67.5 × 60). This 3
When divided into one screen, as shown in FIG. 13, one sub-screen is configured as 22.5 × 60 (macro book). The fixed length unit is 7.5 macroblocks per 5 sync blocks, and 1.5 macroblocks per sync block. Therefore, as shown in FIG. 14, one macroblock is divided into ½. Define as a half macroblock. In addition, the half macroblock is, as shown in FIGS. 14A and 14B,
Two types occur. When such a half macroblock is used, one sub-screen is composed of (45 × 60) half macroblocks, as shown in FIG.
As shown in FIG. 16, one area obtained by dividing the sub-screen into 10 in the vertical direction and 5 in the horizontal direction is a super macro block. As shown in FIG. 18, 3 × 5 = 15 half macroblocks = 7.5 macroblocks, which are three half macroblocks collected from each of the five super macroblocks indicated by diagonal lines, are fixed length units. Each super macroblock is composed of 54 half macroblocks as shown in FIGS. 17A and 17B.
7C and 17D are arranged in this order. 54 × 5 = 270 half macroblocks = 135 macroblocks in a coding pass in five super macroblocks 270 × 3 = 810 half macroblocks in one screen = 405 macroblocks / screen is 2 tracks (135 × 2 = 270 sync blocks)
Recorded in. That is, 405 macroblocks / 270 syncblocks = 1.5 macrobook / syncblocks 1.5 × 5 = 7.5 macroblocks / syncblocks (5 syncblocks).

Here, the arrangement of the super macrobooks shown by diagonal lines in FIG. 18 corresponds to the shuffling pattern. When collecting 3 half macrobooks (1.5 macroblocks) from each super macrobook, start from the upper left of the supermacrobook, then 3 halfblocks below the screen, and so on. Collected to connect above. Furthermore, how to divide the 3 half macro books in the super macro book is
Two types of patterns shown in FIGS. 17A and 17B are prepared.

Then, the framing circuits 14A, 14B,
As shown in FIG. 19, the 14C develops 7.5 macroblocks of data per 5 sync blocks into a frame.

Furthermore, it is used in Europe (1250
/ 50) The case of recording an HDTV signal will be described. When recording a (1250/50) HDTV signal, the number of effective samples per line is 1080
The number of effective lines per frame is 1152. From this, the number of macroblocks arranged in one frame is calculated as follows: 1080/16 = 67.5 1152/16 = 72. Therefore, the number of macroblocks per frame is (67.5 × 72).

In the HDTV signal, the number of tracks per frame is 24 tracks. When recording a current television signal, 135 sync blocks are arranged per track. In order to make it common with the processing at this time,
Even when (1250/50) HDTV signals are recorded,
The number of sync blocks per track is set to 135. Further, when recording a current television signal, the buffer unit having a fixed length is 5 sync blocks. In order to standardize the processing, (1250/5
0) Even when an HDTV signal is recorded, the buffer unit having a fixed length is set to 5 sync blocks.

As described above, in order to record 135 sync blocks per track with 5 sync blocks as a buffer unit, how many macro blocks should be collected to collect data for 5 sync blocks in a buffer unit. Ask.

For (1250/50) HDTV signals, 1
There are 24 tracks per frame, 1
Since the number of macroblocks per frame is 72 × 67.5 = 4860, the number of macroblocks per track is 4860/24 = 202.5. The number of sync blocks per track is 135
The number of macroblocks per track is 202.5
Therefore, the number of macroblocks per 5 sync blocks is 7.5. From this, (1250/50)
For HDTV signals, processing may be performed so that 7.5 macroblocks are collected per 5 sync blocks. This processing is similar to the above-mentioned (1050/60) HDTV signal.

However, in the case of (1250/50) HDTV signal, one sub-screen is 45 × 72 (half macro book). Therefore, in the case of (1050/60) HDTV signal, the sub-screen is divided into 10, whereas in the case of (1250/50) HDTV signal, the sub-screen is divided into 12 in the vertical direction, as shown in FIG. A super macro block.

As described above, the compressed data packed in the sync block is output from each coding pass. As described above, when actually recording, two channels are simultaneously recorded on the tape by the double azimuth heads 20 and 20B, 21A and 21B.

As described above, (1125/60) HDT
In the case of the V signal, 8 macroblocks are packed into 5 sync blocks and recorded. At this time, the 8 macroblocks compressed by the pre-recording deshuffling circuits 15A, 15B, and 15C are separated by 5 sync blocks. Arranged in blocks. Similarly, a (1050/60) HDTV signal,
In the (1250/50) HDTV signal, 7.5 macroblocks are packed into 5 sync blocks, but the compressed 7.5 macroblocks are arranged in 5 sync blocks separated from each other.

FIG. 21A shows (1125/60) HDTV.
FIG. 21B shows to which sync block the macro block on the sub screen is arranged, in the case of a signal. In addition, FIG. 22A shows (1050/6
0) shows a sub-screen in the case of an HDTV signal or a (1250/50) HDTV signal, and FIG. 22B shows to which sync block a macro block on the sub-screen is arranged. In the case of the (1125/60) HDTV signal, since only 4 sync blocks out of 5 sync blocks have the fixed area of the macro block, the fifth sync block is arranged at the end of the track.

FIG. 23 shows an example of the configuration of the 3-channel / 2-channel conversion circuit 16 for converting 3-parallel processing into 2-parallel processing. In FIG. 23, 31, 32,
33 is a memory. The memories 31, 32, and 33 store data for three sync blocks, respectively. Memory 3
1, 32, 33 are connected to the input terminals 34, 35, 36 from
Three coding paths CP-A and CP-, respectively
Signals coded by B and CP-C are supplied.

Reference numeral 37 is a switch circuit. The outputs of the memories 31, 32, and 33 are supplied to the switch circuit 37, respectively. An RF switching pulse is supplied to the switch circuit 37. The outputs of the memories 31 to 33 are sequentially switched by this RF switching pulse. With this switch circuit 37, three coding paths C
The signals coded by PA, CP-B, and CP-C are converted into two channels CH1 and CH2.
The outputs of the channels CH1 and CH2 are output from the output terminals 38 and 39.

As described above, the memories 31, 32 and 33 store data for 3 sync blocks, respectively.
That is, the memory 31 has memory areas 31A, 31B, 31 for storing data for one sync block, respectively.
Composed of C. The memory 32 has memory areas 32A and 32A for storing data of one sync block, respectively.
It is composed of B and 32C. Memory 33,
Memory area 33 that stores data for one sync block
It is composed of A, 33B and 33C.

Memory areas 31A and 31 of the memory 31
For B and 31C, first, the coding channel CP-
Sync blocks A1, A2, coded with A,
Data of A3, ... Is stored. In the memory areas 32A, 32B and 32C of the memory 32, the sync block B coded by the coding channel CP-B is written.
Data of 1, B2, B3, ... Are stored. Memory 33
Of the sync blocks C1, C2, C3, ... Coded on the coding channel CP-C are stored in the memory areas 33A, 33B, 33C of the.

The switch circuit 37 uses the channel CH1.
, The sync blocks A1, B1, C1, ... Are sequentially output, and the channel CH2 is sequentially output with A2, B2, C2. The signal of the channel CH1 is supplied to the rotary heads 20A and 21A. The signal of the channel CH2 is supplied to the rotary heads 20B and 21B. The rotary heads 20A and 21A and the rotary heads 21A and 21B have different azimuth angles as described above.

In FIG. 24, in the period T ₁ , the memory 31,
In the memory areas 31A, 32A and 33A of 32 and 33,
Compressed data of sync blocks A1, B1, and C1 are stored. In the period T ₂ , the sync blocks A2 and B are stored in the memory areas 31B, 32B and 33B of the memories 31, 32 and 33.
2, C2 compressed data is stored. Memory areas 31C, 32C, 33 of the memories 31, 32, 33 in the period T ₃
Compressed data of sync blocks A3, B3, and C3 is stored in C.

At the same time, in the period T ₃ , the channel CH1
, CH2 outputs the compressed data of sync blocks A1 and A2, then outputs the compressed data of sync blocks B1 and B2 to channels CH1 and CH2, and then the compressed data of sync blocks C1 and C2 to channels CH1 and CH2. It

Output of channel CH1 and channel CH
2 outputs heads 20A and 21 with different azimuth angles.
A and 20B and 21B simultaneously record. FIG. 25 shows a track pattern of a (1125/60) HDTV signal recorded in this manner. In FIG. 25, the track TR1 is the head 20.
This is the pattern of channel CH1 recorded in A and 21A. The track TR2 is a pattern of the channel CH2 recorded by the heads 20B and 21B. The position of each block on the screen is as shown in FIG. In addition,
In FIG. 26, blocks without diagonal lines are recorded on channel CH1 and blocks with diagonal lines are recorded on channel CH2.

FIG. 27 shows a (1050/60) HDTV signal or a (1250/50) HDTV signal when recorded in this way, and FIG. 28 shows a position on the screen at this time. Is.

As shown in FIG. 25 and FIG. 26, FIG. 27 and FIG. 28, when recording is carried out in this way, the lumps on the screen are also lumped on the tape pattern. During variable speed reproduction, as shown in FIG. 29, the head scans over the track, and the reproduction signal becomes burst. At this time, it is assumed that the portion indicated by P in FIG. 29 can be picked up. The position on the screen corresponding to the P portion picked up at this time is shown in FIG. 3 in the case of a (1125/60) HDTV signal.
When it is 0, it becomes the part indicated by Q ₁ and Q ₂ , and (1250/50)
In the case of the HDTV signal and the (1050/60) HDTV signal, the part indicated by R in FIG. In this way, the concentrated portion of the screen can be picked up during variable speed reproduction, and the image quality during variable speed reproduction can be improved.

FIG. 32 shows the structure of a reproducing system of a digital VTR to which the present invention is applied. In FIG. 32, the signals reproduced by the rotary heads 20A, 20B, 21A, 21B are reproduced amplifiers 51A, 51B, 52A,
Channel decoders 53A and 53B via 52B
Is supplied to. Channel decoders 53A and 53B
Is a channel encoder 17A and 1 in the recording system.
The reproduced signal is demodulated by the modulation method corresponding to 7B.

Reference numeral 55 is a 2-channel / 3-channel conversion circuit. The outputs of the channel decoders 53A and 53B are supplied to the 2-channel / 3-channel conversion circuit 55. The 2-channel / 3-channel conversion circuit outputs the reproduction outputs of the channels CH1 and CH2.
Three decoding paths DCP-A, DCP-B, D
Divide into CP-C.

Reference numerals 56A, 56B and 56C denote shuffling circuits, and the shuffling circuits 56A, 56B and 56.
C is the deshuffling path 15A, 15 in the recording system.
It corresponds to B and 15C.

Reference numerals 57A, 57B and 57C are deframing circuits. The deframe circuits 57A, 57B and 57C are
Framer circuits 14A, 14B, 14C in recording system
It corresponds to. Shuffling circuits 56A, 56B, 5
The output of 6C is the deframing circuit 57A, 57B, 57C.
Is supplied to. Deframe circuit 57A, 57B, 5
By 7C, the compressed data is decomposed from the frame and the error correction process is performed.

58A, 58B and 58C are variable length code decoding circuits, 59A, 59B and 59C are inverse quantizers, and 60.
A, 60B, and 60C are inverse DCT conversion circuits. The outputs of the variable length code decoding circuits 58A, 58B and 58C are supplied to the inverse quantizers 59A, 59B and 59C, respectively. The outputs of the inverse quantizers 59A, 59B and 59C are supplied to the inverse DCT conversion circuits 60A, 60B and 60C, respectively.

Variable length code decoding circuits 58A, 58B, 5
8C is for decoding a two-dimensional Huffman code and corresponds to the variable length coding circuits 13A, 13B, 13C in the recording system. The inverse quantizers 59A, 59B and 59C are
Inverse quantization is performed corresponding to the quantizers 11A, 11B and 11C in the recording system. Inverse DCT conversion circuit 6
Reference numerals 0A, 60B, and 60C correspond to the DCT conversion circuits 9A, 9B, and 9C in the recording system, and perform DCT inverse conversion to convert the reproduced frequency-domain digital video signal into a time-domain digital video signal.

Reference numerals 61A, 61B and 61C denote deshuffling circuits. Deshuffling circuits 61A, 61B, 61
The outputs of the inverse DCT conversion circuits 60A, 60B, and 60C are supplied to C, respectively. Deshuffling circuit 61A,
61B and 61C are shuffling circuits 8 in the recording system.
Data is rearranged in units of macroblocks corresponding to A, 8B, and 8C.

Reference numeral 62 is a parallel-serial conversion circuit.
The parallel-serial conversion circuit 62 is for dividing the data divided into three decoding paths DCP-A, DCP-B, and DCP-C, and decoding the data for each sub-screen into a single pass screen. . The parallel-serial conversion circuit 62 includes deshuffling circuits 61A and 61B,
The outputs of 61C are respectively supplied. The parallel-serial conversion circuit 62 outputs a digital luminance signal Y and line-sequential digital color difference signals PR and PB.

The digital luminance signal Y is supplied to the D / A converter 63. The D / A converter 63 converts the digital luminance signal into an analog luminance signal. This signal is output from the output terminal 64.

The line-sequentialized digital color difference signals PR and PB are supplied to the interpolation circuit 65. Interpolation circuit 65
Then, from the line-sequential color difference signal, two digital color difference signals P
R and PB are taken out. The digital color difference signals PR and PB are supplied to D / A converters 66 and 67. The D / A converters 66 and 67 convert the digital color difference signals PR and PB into analog color difference signals PR and PB. The color difference signals PR and PB are output from the output terminal 68.
And 69.

[0091]

According to the present invention, a digital HDTV is provided.
When a signal is recorded, it is divided into three coding passes for processing. As a result, in each coding pass, coding can be performed by the same processing as in the case of recording a current television signal such as the NTSC system or the PAL system. Also, during playback, the processing is performed by dividing it into three decoding paths.
It is possible to perform the same processing as in the case of reproducing a current television signal such as the standard method or the PAL method.

The data coded by the three coding passes is converted into two channels and recorded on the magnetic tape by the four rotary heads. When converting the data of three coding paths into two channels, the data is allocated so that the data collected on the screen is arranged in the range on the tape corresponding to the part that is played back in a burst manner at the time of variable speed playback. . For this reason, the screen of the fixed part on the screen can be reproduced during variable speed reproduction, and the image quality during variable speed reproduction can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a recording system of a digital VTR to which the present invention is applied.

FIG. 2 is a schematic diagram used for explaining a three-division processing in a digital VTR to which the present invention is applied.

FIG. 3 is a schematic diagram used for explaining a sub-screen in a digital VTR to which the present invention is applied.

FIG. 4 is a plan view used for explaining a head arrangement in a digital VTR to which the present invention is applied.

FIG. 5 is a schematic diagram used for explaining a macroblock in a digital VTR to which the present invention is applied.

FIG. 6 is a schematic diagram used for explaining a case of recording a (1125/60) HDTV signal in a digital VTR to which the present invention is applied.

FIG. 7 is a schematic diagram used for explaining a case of recording a (1125/60) HDTV signal in a digital VTR to which the present invention is applied.

FIG. 8 is a schematic diagram used for explaining a case of recording a (1125/60) HDTV signal in a digital VTR to which the present invention is applied.

FIG. 9 is a schematic diagram used for explaining a case of recording a (1125/60) HDTV signal in a digital VTR to which the present invention is applied.

FIG. 10 is a schematic diagram used for explaining a case of recording a (1125/60) HDTV signal in a digital VTR to which the present invention is applied.

FIG. 11 is a schematic diagram used for explaining a case of recording a (1125/60) HDTV signal in a digital VTR to which the present invention is applied.

FIG. 12 is a schematic diagram showing a frame structure when a (1125/60) HDTV signal is recorded in a digital VTR to which the present invention is applied.

FIG. 13 shows a (1250/50) HDTV signal and a (1050/50) HDTV signal in a digital VTR to which the present invention is applied.
60) A schematic diagram used for description when recording an HDTV signal.

FIG. 14 is a schematic diagram used for explaining a half macroblock in a digital VTR to which the present invention is applied.

FIG. 15 shows a (1250/50) HDTV signal and a (1050/50) HDTV signal in a digital VTR to which the present invention is applied.
60) A schematic diagram used for description when recording an HDTV signal.

FIG. 16 shows a (1250/50) HDTV signal and (1050/50) HDTV signal in a digital VTR to which the present invention is applied.
60) A schematic diagram used for description when recording an HDTV signal.

FIG. 17 shows a (1250/50) HDTV signal and a (1050/50) HDTV signal in a digital VTR to which the present invention is applied.
60) A schematic diagram used for description when recording an HDTV signal.

FIG. 18 is a schematic diagram used for explaining a case of recording a (1050/60) HDTV signal in a digital VTR to which the present invention is applied.

FIG. 19 shows a (1250/50) HDTV signal and (1050/50) HDTV signal in a digital VTR to which the present invention is applied.
FIG. 60 is a schematic diagram showing a frame structure for recording an HDTV signal.

FIG. 20 is a schematic diagram used for explaining a case of recording a (1250/50) HDTV signal in a digital VTR to which the present invention is applied.

FIG. 21 is a schematic diagram showing a relationship between a sub-screen and sync blocks when a (1125/60) HDTV signal is recorded in a digital VTR to which the present invention is applied.

FIG. 22 shows a (1250/50) HDTV signal and a (1050/50) HDTV signal in a digital VTR to which the present invention is applied.
60) A schematic diagram showing the relationship between a sub-screen and a sync block when recording an HDTV signal.

FIG. 23 is a block diagram showing an example of a 3-channel / 2-channel conversion circuit in a digital VTR to which the present invention is applied.

FIG. 24 is a timing chart used for explaining a 3-channel / 2-channel conversion circuit in a digital VTR to which the present invention is applied.

FIG. 25 is a schematic diagram showing a track pattern when a (1125/60) HDTV signal is recorded in a digital VTR to which the present invention is applied.

FIG. 26 is a schematic diagram showing positions on the screen when a (1125/60) HDTV signal is recorded in a digital VTR to which the present invention is applied.

FIG. 27 shows a (1250/50) HDTV signal and a (1050/50) HDTV signal in a digital VTR to which the present invention is applied.
60) A schematic diagram showing a track pattern when an HDTV signal is recorded.

FIG. 28 is a digital VTR to which the present invention is applied, in which (1250/50) HDTV signal and (1050/50)
60) A schematic diagram showing the position on the screen when an HDTV signal is recorded.

FIG. 29 is a schematic diagram used for explaining variable speed reproduction in a digital VTR to which the present invention is applied.

FIG. 30 is a schematic diagram used for explaining variable speed reproduction when a (1125/60) HDTV signal is recorded in a digital VTR to which the present invention is applied.

FIG. 31 shows a (1250/50) HDTV signal and a (1050/50) HDTV signal in a digital VTR to which the present invention is applied.
60) A schematic diagram used for explaining variable speed reproduction when an HDTV signal is recorded.

FIG. 32 is a block diagram showing the structure of a reproducing system of a digital VTR to which the present invention is applied.

FIG. 33 is a block diagram showing a configuration of a recording system of a conventional digital VTR.

FIG. 34 is a plan view used for explaining a head arrangement of a conventional digital VTR.

[Explanation of symbols]

 7 serial-parallel conversion circuit 8A, 8B, 8C blocking and shuffling circuit 9A, 9B, 9C DCT conversion circuit 10A, 10B, 10C buffer circuit 11A, 11B, 11C quantizer 14A, 14B, 14C framing circuit 163 3 channels / 2 channel conversion circuit

Claims (4)

[Claims] 1. A coding path for collecting digital video signals in a predetermined buffer unit, compressing and coding such that the code amount in the predetermined buffer unit becomes a predetermined value or less, and framing the compression-coded signal. And a recording means for recording a signal compressed and encoded by the coding path on a magnetic tape by a rotary head, wherein a plurality of the coding paths are provided and an input digital video signal is coded by the plurality of coding paths. And a means for dividing the outputs of the plurality of coding paths into two channels. When recording a digital HDTV signal, the digital HDTV signal is divided into the plurality of coding paths, After compression coding with the coding path of Digital video signal recording apparatus characterized in that so as to record the tunnel of. 2. The digital video signal recording apparatus according to claim 1, wherein the coding path comprises three coding paths, and the digital HDTV signal is divided into the three coding paths and compression-coded. 3. When the data coded by the plurality of coding passes is converted into two channels, the data collected on the screen in a range on the tape corresponding to a portion to be reproduced in burst at the time of variable speed reproduction. 2. The digital video signal recording device according to claim 1, wherein the data is allocated so as to be arranged. 4. A digital device having means for reproducing a compressed digital video signal recorded on a magnetic tape, and a decoding path for deframing the reproduced signal, expanding the compressed digital video signal, and decoding the digital video signal. In a video signal reproducing apparatus, a plurality of decoding paths are provided, a means for outputting a reproduction signal of 2 channels to a plurality of decoding paths, and a signal decoded by the plurality of decoding paths is combined into a signal for one screen. And reproducing the digital HDTV signal by dividing the reproduced signal of the two channels into a plurality of decoding paths and outputting the reproduced signal into a plurality of pieces by the plurality of decoding paths. Decoded and then decoded by the above multiple decoding passes. The signal combined to 1
A digital video signal reproducing device characterized in that a signal on a screen is reproduced.