JPH06334935A - Video compressing circuit - Google Patents

Abstract

PURPOSE:To obtain a horizontal data compression ratio equal to a horizontal compression ratio for a screen in respect to a video compressing circuit for a slave screen. CONSTITUTION:The video compressing circuit is constituted of an Y/C separator circuit 10 for inputting a digitized video signal and separating the video signal into a luminance signal and a carrier chrominance signal, a decoder 11 for inputting the carrier chrominance signal and outputting an R-Y signal and a B-Y signal, plural LPFs 12 to 14 for respectively inputting the luminance signal, the R-Y signal and the B-Y signal and moving a high frequency component from each input, compressing circuits 15 to 17 for respectively inputting the output signals of the LPFs 12 to 14 and executing horizontal time base compression, plural vertical filters 18 to 20 for inputting the output signals of the circuits 15 to 17 and compressing the vertical directions of respective input signals, an encoder 21 for inputting output signals from the filters 19, 20 and remodulating a new carrier chrominance signal, and an adder 22 for inputting the output signal of the filter 18 and the output signal of the encoder 21 and adding both the inputs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a picture compression circuit for a child screen in a digital color television receiver.

[0002]

2. Description of the Related Art In recent years, the trend toward digitalization in the signal processing of televisions has been increasing with the improvement in image quality and multifunctionality of television receivers. When this is done, a video compression circuit for the child screen is required.

A conventional picture compression circuit for a child screen will be described below with reference to FIG. FIG. 3 shows the configuration of a conventional image compression circuit for a child screen. In FIG. 3, reference numeral 30 is a separation circuit (hereinafter referred to as YC separation circuit) for inputting a digitized video signal and separating it into a luminance signal component and a carrier color signal component. Reference numeral 31 is an input of the carrier color signal of the YC separation circuit, and an RY color difference signal (hereinafter referred to as an RY signal)
A Y-color difference signal (hereinafter referred to as BY signal) is a decoder for separating the signals. Reference numeral 32 is a first low-pass filter (hereinafter, referred to as LPF) that inputs a luminance signal and removes high frequency components. A second LPF 33 receives the RY signal and removes high frequency components. A third LPF 34 receives the BY signal and removes high frequency components. Reference numeral 35 is a first compression circuit that receives the output signal of the first LPF and performs horizontal time axis compression. A second compression circuit 36 receives the output signal of the second LPF as input and performs horizontal time axis compression. A third compression circuit 37 receives the output signal of the third LPF as input and performs horizontal time axis compression. 38 is the first
The first vertical filter receives the output signal i of the compression circuit and performs image compression in the vertical direction. A second vertical filter 39 receives the output signal j of the second compression circuit and performs image compression in the vertical direction.

Reference numeral 40 is a third vertical filter which receives the output signal k of the third compression circuit and performs image compression in the vertical direction. 41 inputs the output signals of the first vertical filter, the second vertical filter, and the third vertical filter, and with respect to the effective data number 4 of the output signal 1 of the first vertical filter, It is a multiplex circuit for time-division multiplexing the output signal m of 1 and the output signal n of the third vertical filter at a ratio of 1.

The operation of the video compression circuit for a child screen configured as described above will be described below with reference to FIGS. 3 and 4. First, as shown in FIG. 3, the digitized video signal a is input to the YC separation circuit 30, and the luminance signal component b is input.
And the carrier color signal component c. The decoder 31 inputs the carrier color signal c which is the output signal of the YC separation circuit 30, and outputs R
-Y signal d and BY signal e are separated. First LPF3
The luminance signal b is input to 2 to reduce aliasing noise of high frequency components due to the horizontal compression operation in the next stage. Similarly,
The RY signal d is input to the second LPF 33, and the high frequency component of the RY signal d is removed. B for the third LPF 34
The -Y signal e is input and the high frequency component of the BY signal e is removed.

The first compression circuit 35 receives the output signal f of the first LPF 32 and performs horizontal time axis compression. The second compression circuit 36 inputs the output signal g of the second LPF 33,
Performs horizontal time axis compression. The third compression circuit 37 has a third L
The output signal h of the PF 34 is input to perform horizontal time axis compression. The first vertical filter 38 inputs the output signal i of the first compression circuit 35 and performs vertical time-axis compression. The second vertical filter 39 inputs the output signal j of the second compression circuit 36 and performs vertical time axis compression. The third vertical filter 40 receives the output signal k of the third compression circuit 37 and performs vertical time axis compression. The multiplex circuit 41 receives the output signals l, m, and n of the first vertical filter 38, the second vertical filter 39, and the third vertical filter 40 as input, and outputs valid data of the output signal l of the first vertical filter 38. For number 4,
The output signal m of the second vertical filter 39 and the output signal n of the third vertical filter 40 are time-division multiplexed at a ratio of 1.

Horizontal time axis compression and time division multiplexing will be described below with reference to FIG. FIG. 4 shows the timing of a conventional picture compression circuit for a small screen. The video signal a is input to the YC separation circuit 30 and is separated into a luminance signal component b and a carrier color signal component c, and the carrier color signal component c is decoded by the decoder 31 to have a data rate R of a quarter of the luminance signal b.
It is output as a -Y signal d and a BY signal e. The luminance signal b, the RY signal d, and the BY signal e are respectively band-limited by being input to the LPF, and the luminance signal is resampled by the Y compression pulse for the luminance signal compression in the horizontal compression circuit in the next stage to obtain the color difference. The signal is resampled by C compression pulse for color difference signal compression,
Horizontally compress the data.

In the example of FIG. 4, a compression pulse is generated for the data 3 at intervals of one shot so that the compression rate becomes 1/3. The compressed signals i, j, k are input to the vertical filter and are vertically compressed into l, m, n. The vertical filter outputs l, m, and n are the first luminance signal (Y0 ′), the RY signal ((RY) 0 ′), the second luminance signal (Y1 ′), and the Three
Luminance signal (Y2 '), BY signal ((BY)
0 ′) and the fourth luminance signal (Y4 ′) are multiplexed in this order and output as the output signal o of the multiplex circuit output 41.

[0009]

However, in the above configuration, for example, when the composite video signal is horizontally compressed to ⅓, the compressed data of 6 samples is output from the data of 12 samples. Therefore, the data amount does not become 1/3, but remains at 1/2 the data compression rate which is 1.5 times the horizontal compression rate, and there is a problem in terms of memory usage.

The present invention has been made in consideration of the above problems, and it is an object of the present invention to provide a video compression circuit for a sub-screen in which data compression equal to the horizontal compression rate can be performed.

[0011]

In order to solve the above problems, a sub-picture video compression circuit of the present invention is a YC separation circuit for inputting a digitized video signal and separating it into a luminance signal and a carrier color signal. And a decoder that inputs the carrier color signal of the YC separation circuit and outputs an RY signal and a BY signal, and a first LPF that inputs a luminance signal and removes high frequency components.
And a second LPF for inputting the RY signal and removing the high frequency component, a third LPF for inputting the BY signal and removing the high frequency component, and an output signal of the first LPF as input ,
A first compression circuit that performs horizontal time axis compression and a second LPF
Of the first compression circuit, and a second compression circuit for inputting the output signal of 1) for horizontal time axis compression, and a third compression circuit for inputting the output signal of the third LPF for horizontal time axis compression, and the first compression circuit. A first vertical filter that inputs an output signal and performs compression in the vertical direction, a second vertical filter that inputs an output signal of the second compression circuit and performs compression in the vertical direction, and a third compression circuit A third vertical filter that inputs the output signal and performs vertical compression, an encoder that receives the output signals of the second vertical filter and the third vertical filter, and re-modulates to a new carrier color signal; The output signal of the vertical filter of No. 1 and the output signal of the encoder are input, and it is comprised from the adder which carries out addition.

[0012]

With the above-described structure, the present invention can obtain the compression rate of the data amount equal to the horizontal compression rate of the video signal, and can reduce the memory capacity required for the child screen processing.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An image compression circuit for a child screen according to an embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows the configuration of a video compression circuit for a child screen in an embodiment of the present invention. In FIG.
A YC separation circuit 10 receives the digitized video signal a and separates it into a luminance signal component b and a carrier color signal component c. A decoder 11 receives the carrier color signal c of the YC separation circuit 10 and separates it into an RY signal d and a BY signal e. Reference numeral 12 is a first LPF which receives the luminance signal b and removes high frequency components. 13 inputs the RY signal d,
It is a second LPF that removes high frequency components. 14 is a third LPF which receives the BY signal e and removes high frequency components
Is.

Reference numeral 15 is a first compression circuit which receives the output signal f of the first LPF 12 and performs horizontal time axis compression.
Reference numeral 16 is a second compression circuit which receives the output signal g of the second LPF 13 and performs horizontal time axis compression. A third compression circuit 17 receives the output signal h of the third LPF 14 and performs horizontal time axis compression. 18 is the first compression circuit 15
Is a first vertical filter for inputting the output signal i of the above and performing data compression in the vertical direction. The second signal 19 receives the output signal j of the second compression circuit 16 and performs data compression in the vertical direction.
Is a vertical filter of. Reference numeral 20 is a third vertical filter which receives the output signal k of the third compression circuit 17 and performs data compression in the vertical direction. 21 is the second vertical filter and the third
It is an encoder for inputting the output signals m and n of the vertical filter, and re-modulating to output a new color difference signal. 22 is the output signal 1 of the first vertical filter 18 and the encoder 2
It is an adder that receives the output signal o of 1 and adds them together.

The operation of the video compression circuit for a child screen configured as described above will be described below with reference to FIGS. 1 and 2.

First, as shown in FIG. 2, the digitized video signal is input to the YC separation circuit 10 and separated into a luminance signal component and a carrier color signal component. Decoder 11 is Y
The carrier color signal which is the output signal of the C separation circuit 10 is input,
Separated into RY and BY signals. First LPF 12
A luminance signal is input to the input terminal to reduce aliasing noise of high frequency components due to the horizontal compression operation in the next stage. The RY signal is input to the second LPF 13, and the high frequency component of the RY signal is removed. The BY signal is input to the third LPF 14, and the high frequency component of the BY signal is removed.

The first compression circuit 15 receives the output signal of the first LPF 12 and performs horizontal time axis compression. The second compression circuit 16 receives the output signal of the second LPF 13 and performs horizontal time axis compression. The third compression circuit 17 is a third LPF.
The output signal of 14 is input and horizontal time axis compression is performed. The vertical filter 18 receives the output signal i of the first compression circuit 15 and performs data compression in the vertical direction. The vertical filter 19 inputs the output signal j of the second compression circuit 16 and performs data compression in the vertical direction. The vertical filter 20 inputs the output signal k of the third compression circuit 17 and performs data compression in the vertical direction.

The encoder 21 receives the output signals m and n of the second vertical filter and the third vertical filter, remodulates them, and outputs a new carrier color signal o. The adder 22 is the first
The output signal l of the vertical filter 18 and the output signal o of the encoder 21 are input, and both are added.

The horizontal time axis compression and time division multiplexing will be described below with reference to FIG. FIG. 2 shows the timing of the image compression circuit for a small screen of the present invention. The video signal a is input to the YC separation circuit 10 and is separated into a luminance signal component b and a carrier color signal color difference signal component c, and the carrier color signal c is decoded by the decoder 11 at a data rate R which is a quarter of the luminance signal b. It is output as a -Y signal d and a BY signal e.

Luminance signal b, RY signal d, and BY signal e
Are respectively input to the LPF and band-limited, and in the horizontal compression circuit of the next stage, the luminance signal is resampled by a Y compression pulse for luminance signal compression, and the color difference signal is resampled by a C compression pulse for color difference signal compression. , Horizontally compress the data. In the example of FIG. 2, the compression pulse is generated for the data 3 at intervals of one shot so that the compression rate becomes 1/3. The compressed signals i, j, k are input to the vertical filter and are vertically compressed into l, m, n. The second vertical filter output m and the third vertical filter output n are supplied to the encoder 21.
, And is re-modulated in accordance with the output signal l of the first vertical filter 18 and output as an encoder output o (CRMx). Finally, the compressed luminance signal 1 and the encoder output o are added by the adder 22 and output as the final data p.

As described above, according to this embodiment, the compression rate of the data amount equal to the horizontal compression rate of the video signal can be obtained, and the memory capacity required for the child screen processing can be reduced.

[0023]

As described above, according to the present invention, the compression rate of the data amount equal to the horizontal compression rate of the video signal can be obtained, and the memory capacity required for the child screen processing can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a video compression circuit for a child screen according to an embodiment of the present invention.

FIG. 2 is a timing diagram of a video compression circuit for a child screen in an embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional video compression circuit for a child screen.

FIG. 4 is a timing diagram of a conventional image compression circuit for a child screen.

[Explanation of symbols]

 10 YC Separation Circuit 11 Decoder 12 First LPF 13 Second LPF 14 Third LPF 15 First Compression Circuit 16 Second Compression Circuit 17 Third Compression Circuit 18 First Vertical Filter 19 Second Vertical Filter Filter 20 Third Vertical Filter 21 Encoder 22 Adder

Claims (1)

[Claims] 1. A separation circuit for inputting a digitized video signal and separating it into a luminance signal and a carrier color signal, and a carrier color signal of the separation circuit as an input, and an RY color difference signal and a BY color difference signal. A first low-pass filter that receives the luminance signal and removes high-frequency components;
A second low-pass filter that inputs the −Y color difference signal and removes high-frequency components; a third low-pass filter that inputs the BY color-difference signal and removes high-frequency components; and an output signal of the first low-pass filter. A first compression circuit that receives the horizontal time axis compression as an input, a second compression circuit that receives the output signal of the second low pass filter as an input and performs the horizontal time axis compression, and an output signal of the third low pass filter A third compression circuit for inputting and performing horizontal time axis compression, and a first compression circuit for inputting the output signal of the first compression circuit and performing vertical compression
And a second vertical filter for inputting the output signal of the second compression circuit and performing compression in the vertical direction, and a third vertical filter for receiving the output signal of the third compression circuit and performing compression in the vertical direction. Of the vertical filter, the encoder for inputting the output signals of the second vertical filter and the third vertical filter and re-modulating to a new carrier color signal, the output signal of the first vertical filter and the encoder A video compression circuit, comprising: an adder for inputting and adding output signals.