JPH06334167A - Photo-semiconductor element integrated circuit device - Google Patents
Photo-semiconductor element integrated circuit deviceInfo
- Publication number
- JPH06334167A JPH06334167A JP5147012A JP14701293A JPH06334167A JP H06334167 A JPH06334167 A JP H06334167A JP 5147012 A JP5147012 A JP 5147012A JP 14701293 A JP14701293 A JP 14701293A JP H06334167 A JPH06334167 A JP H06334167A
- Authority
- JP
- Japan
- Prior art keywords
- circuit device
- semiconductor element
- optical semiconductor
- integrated circuit
- element integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、光半導体素子集積回路
装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor element integrated circuit device.
【０００２】[0002]
【従来の技術】従来、図４を伴って次に述べる光半導体
素子集積回路装置が提案されている。2. Description of the Related Art Conventionally, an optical semiconductor element integrated circuit device described below with reference to FIG. 4 has been proposed.
【０００３】すなわち、平らな絶縁性主面１ａを有する
支持体１を有する。That is, it has a support 1 having a flat insulating main surface 1a.
【０００４】また、相対向する平らな絶縁性主面２ａ及
び２ｂと平らな絶縁性前端面２ｃとを有し、そして、一
方の絶縁性主面２ａを支持体１の絶縁性主面１ａ側とし
た状態で、支持体１の主面１ａ上に配されている基板２
を有する。Further, it has flat insulating main surfaces 2a and 2b facing each other and a flat insulating front end surface 2c, and one insulating main surface 2a is located on the insulating main surface 1a side of the support 1. The substrate 2 arranged on the main surface 1a of the support 1 in this state
Have.
【０００５】また、相対向する主面３ａ及び３ｂと相対
向する絶縁性前後端面３ｃ及び３ｄとを有し、そして、
一方の絶縁性主面３ｂを基板２側とした状態で、基板２
上に配されている駆動用回路装置３を有する。Further, it has main surfaces 3a and 3b facing each other and insulating front and rear end surfaces 3c and 3d facing each other, and
With one insulating main surface 3b facing the substrate 2 side, the substrate 2
It has a driving circuit device 3 arranged above.
【０００６】この場合、駆動用回路装置３は、前端面３
ｃから前方に突出延長している、信号用の端子片４ａ及
びそれを挟むように配された対の接地用の端子片４ｂ
と、後端面３ｄから後方に突出延長している、端子片４
ａ及び４ｂと同様の端子片（図示せず）とを有し、そし
て、信号端子片４ａ及び接地端子片４ｂ間に、第２の駆
動用信号を、後端面３ｄ側の端子片４ａ及び４ｂと同様
の端子片を用いて入力される第１の駆動用信号の入力に
応じて出力する構成を有する。In this case, the driving circuit device 3 has the front end face 3
A signal terminal piece 4a extending forward from c and a pair of grounding terminal pieces 4b arranged so as to sandwich the signal terminal piece 4a.
And the terminal piece 4 extending rearward from the rear end face 3d.
a and 4b and a terminal piece (not shown) similar to the above, and a second driving signal is supplied between the signal terminal piece 4a and the ground terminal piece 4b on the rear end face 3d side. It has a configuration to output in response to the input of the first drive signal input using the same terminal piece.
【０００７】また、駆動用回路装置３は、後端面３ｄ側
の端子片４ａ及び４ｂと同様の端子片を用いて入力され
る第１の駆動用信号に対する入力インピ―ダンスと等し
い、前端面３ｃ側の端子片４ａ及び４ｂ間に出力される
第２の駆動用信号に対する出力インピ―ダンスを有して
いる。Further, the driving circuit device 3 has a front end face 3c having the same input impedance with respect to the first driving signal inputted using the terminal strips 4a and 4b on the rear end face 3d side. It has an output impedance for the second drive signal output between the terminal pieces 4a and 4b on the side.
【０００８】この場合、第１の駆動用信号に対する入力
インピ―ダンスは、５０Ωであるのを普通とし、従っ
て、第２の駆動用信号に対する出力インピ―ダンスも、
５０Ωであるのを普通とする。In this case, the input impedance for the first drive signal is usually 50Ω, and therefore the output impedance for the second drive signal is also
It is usually 50Ω.
【０００９】また、相対向する導電性主面５ａ及び５ｂ
と、相対向する導電性前後端面５ｃ及び５ｄとを有し、
そして、一方の主面５ｂ側を支持体１側として、支持体
１上に、基板２が配されている位置よりも前方位置にお
いて、それと近接して、固定して配されているヒ―トシ
ンク用板体５を有する。Further, the conductive main surfaces 5a and 5b facing each other are provided.
And opposite conductive front and rear end surfaces 5c and 5d,
A heat sink that is fixedly arranged on the support body 1 at a position in front of the position where the substrate 2 is arranged, in close proximity to the main surface 5b side as the support body 1 side. It has a plate body 5.
【００１０】さらに、相対向する主面上にそれぞれ設け
られた電極６ａ及び６ｂと、前端面による光出射面６ｃ
とを有し、そして、一方の電極６６をヒ―トシンク用板
体５側として、ヒ―トシンク用板体５上に固定して配さ
れている光半導体素子６を有する。Furthermore, electrodes 6a and 6b respectively provided on the main surfaces facing each other, and a light emitting surface 6c formed by the front end surface.
And has one of the electrodes 66 on the heat sink plate 5 side, and the optical semiconductor element 6 fixedly arranged on the heat sink plate 5.
【００１１】この場合、光半導体素子６は、４〜７Ωと
いうような、駆動用回路装置３の第２の駆動用信号に対
する出力インピ―ダンスに比し十分低い入力インピ―ダ
ンスを有するのを普通とする。In this case, the optical semiconductor element 6 usually has an input impedance of 4 to 7Ω, which is sufficiently lower than the output impedance of the drive circuit device 3 for the second drive signal. And
【００１２】また、一端を駆動用回路装置３の端子片４
ａに連結して基板２の主面２ａ上に前後方向に延長して
設けられている導体層７ａと、一端を駆動用回路装置３
の対の端子片４ｂに連結して基板２の主面２ａ上に前後
方向に、導体層７ａを挟み且つ導体層７ａと平行に延長
して配されている対の導体層７ｂとで形成されたコプレ
ナ型の伝送線路７を有する。The terminal piece 4 of the driving circuit device 3 has one end.
a conductor layer 7a which is connected to a and is provided on the main surface 2a of the substrate 2 so as to extend in the front-rear direction, and one end of which is the drive circuit device 3
And a pair of conductor layers 7b which are connected to the pair of terminal pieces 4b and are arranged on the main surface 2a of the substrate 2 in the front-rear direction so as to sandwich the conductor layer 7a and extend in parallel to the conductor layer 7a. It also has a coplanar transmission line 7.
【００１３】この場合、伝送線路７は、駆動用回路装置
３の第２の駆動信号に対する出力インピ―ダンスと等し
い特性インピ―ダンスを有し、従って、５０Ωの特性イ
ンピ―ダンスを有するのを普通とする。In this case, the transmission line 7 has a characteristic impedance equal to the output impedance of the driving circuit device 3 with respect to the second drive signal, and thus it usually has a characteristic impedance of 50Ω. And
【００１４】さらに、前後端部の周りにそれぞれ設けら
れた対の電極８ａ及び８ｂを有し、そして、一方の電極
８ｂを伝送線路７の前方遊端部に上方から連結し、他方
の電極８ａを前方に位置させた状態で、基板２の主面２
ａ上の前方端部上に固定して配されているインピ―ダン
ス整合用抵抗素子５を有する。Further, it has a pair of electrodes 8a and 8b respectively provided around the front and rear ends, and one electrode 8b is connected to the front free end of the transmission line 7 from above and the other electrode 8a. Main surface 2 of the substrate 2 with the
It has a resistance element 5 for impedance matching fixedly arranged on the front end portion on a.
【００１５】また、インピ―ダンス整合用抵抗素子８の
電極８ａと、光半導体素子６の電極６ａを連結している
リボン状接続用導体９ａと、伝送線路７の対の導体層７
ｂとヒ―トシンク用板体５とを連結している対のリボン
状接続用導体９ｂとを有する。Further, the electrode 8a of the impedance matching resistance element 8 and the ribbon-shaped connecting conductor 9a connecting the electrode 6a of the optical semiconductor element 6 and the pair of conductor layers 7 of the transmission line 7 are connected.
b and a pair of ribbon-shaped connecting conductors 9b connecting the heat sink plate 5 to each other.
【００１６】この場合、インピ―ダンス整合用抵抗素子
６は、インピ―ダンス整合用抵抗素子８の電極５ｂの伝
送線路７の導体層７との連結点とリボン状接続導体９ｂ
の伝送線路７の導体層７ｂとの連結点との間から、光半
導体素子６側をみたインピ―ダンスが、伝送線路７の特
性インピ―ダンスと等しくなる値を有する。すなわち、
インピ―ダンス整合用抵抗素子８と光半導体素子６とが
近接して配され、従って、リボン状接続用導体９ａ及び
９ｂがその抵抗を無視し得るに十分なだけ短いものとし
て、伝送線路７の５０Ωの特性インピ―ダンスから光半
導体素子６の入力インピ―ダンスを引いた値を有し、従
って、４３〜４６Ω（（５０Ω−７Ω）〜（５０Ω−４
Ω））の値を有するのを普通とする。In this case, in the impedance matching resistance element 6, the connection point between the electrode 5b of the impedance matching resistance element 8 and the conductor layer 7 of the transmission line 7 and the ribbon-shaped connecting conductor 9b.
The impedance seen from the optical semiconductor element 6 side from the connection point of the transmission line 7 with the conductor layer 7b has a value equal to the characteristic impedance of the transmission line 7. That is,
The impedance matching resistance element 8 and the optical semiconductor element 6 are arranged close to each other, so that the ribbon-shaped connecting conductors 9a and 9b are short enough so that their resistance can be ignored. It has a value obtained by subtracting the input impedance of the optical semiconductor element 6 from the characteristic impedance of 50Ω, and therefore 43 to 46Ω ((50Ω-7Ω) to (50Ω-4
It is normal to have a value of Ω)).
【００１７】以上が、従来提案されている光半導体素子
集積回路装置の構成である。The above is the configuration of the conventionally proposed optical semiconductor element integrated circuit device.
【００１８】このような構成を有する従来の光半導体素
子集積回路装置によれば、駆動用回路装置３に、その後
端面３ｄ側の、端子片４ａ及び４ｂと同様の端子片を用
いて、第１の駆動用信号を、外部から供給させれば、そ
れに応じて、駆動用回路装置３から、第２の駆動用信号
が、前端面３ｃ側の端子片４ａ及び端子片４ｂ間に出力
し、そして、その第２の駆動用信号が、伝送線路７を介
し、次でインピ―ダンス整合用抵抗素子８、リボン状接
続導体９ａ及び９ｂを通じて、光半導体素子１に供給さ
れ、よって、光半導体素子６の光出射面６ｃから、第２
の駆動用信号に応じた光が外部に出射する、という光半
導体素子集積回路装置としての機能を呈する。According to the conventional optical semiconductor element integrated circuit device having such a structure, the driving circuit device 3 uses the terminal pieces similar to the terminal pieces 4a and 4b on the rear end face 3d side. If the driving signal is supplied from the outside, the second driving signal is output from the driving circuit device 3 between the terminal piece 4a and the terminal piece 4b on the front end face 3c side, and The second driving signal is supplied to the optical semiconductor element 1 through the transmission line 7, and then through the impedance matching resistance element 8 and the ribbon-shaped connecting conductors 9a and 9b, and thus, the optical semiconductor element 6 From the light emitting surface 6c of the second
The optical semiconductor element integrated circuit device has a function of emitting light according to the driving signal to the outside.
【００１９】[0019]
【発明が解決しようとする課題】図４に示す従来の光半
導体素子集積回路装置の場合、駆動用回路装置３が、そ
れに外部から供給される第１の駆動用信号に対する入力
インピ―ダンスと等しい、端子片４ａ及び４ｂ間に出力
される第２の駆動用信号に対する出力インピ―ダンスを
有し、そして、入力インピ―ダンが５０Ωであるのを普
通とすることから、出力インピ―ダンスが５０Ωである
のを普通とし、従って出力インピ―ダンスが比較的高い
値を有する。In the case of the conventional optical semiconductor element integrated circuit device shown in FIG. 4, the driving circuit device 3 has an input impedance equal to the first driving signal supplied from the outside. , Has an output impedance for the second drive signal output between the terminal pieces 4a and 4b, and since the input impedance is normally 50Ω, the output impedance is 50Ω. , And thus the output impedance has a relatively high value.
【００２０】このため、伝送線路７が、駆動用回路装置
３の出力インピ―ダンスと等しい特性インピ―ダンスを
有するが、その特性インピ―ダンスが高い値を有し、一
方、光半導体素子６が、４〜７Ωというような駆動用回
路装置３の第２の駆動用信号に対する出力インピ―ダン
スに比し十分低い入力インピ―ダンスしか有しないこと
から、インピ―ダンス整合用抵抗素子８が４６〜４３Ω
というような十分高い値を有する。Therefore, the transmission line 7 has a characteristic impedance equal to the output impedance of the driving circuit device 3, but the characteristic impedance has a high value, while the optical semiconductor element 6 has The impedance matching resistance element 8 has a value of 46 to 7Ω because it has an input impedance that is sufficiently lower than the output impedance for the second driving signal of the driving circuit device 3 such as 4 to 7Ω. 43Ω
It has a sufficiently high value such as.
【００２１】従って、光半導体素子集積回路装置として
の機能を得るとき、インピ―ダンス整合用抵抗素子８に
無視し得ない発熱を伴う。Therefore, when the function as the optical semiconductor element integrated circuit device is obtained, the resistance element 8 for impedance matching is accompanied by heat generation which cannot be ignored.
【００２２】一方、インピ―ダンス整合用抵抗素子８が
光半導体素子６に近い位置に配されている。On the other hand, the impedance matching resistance element 8 is arranged at a position close to the optical semiconductor element 6.
【００２３】以上のことから、図４に示す従来の光半導
体素子集積回路装置の場合、光半導体素子６が、インピ
―ダンス整合用抵抗素子８からの熱によって悪影響を受
け、よって、光半導体素子集積回路装置としての機能を
十分発揮しない、という欠点を有していた。From the above, in the case of the conventional optical semiconductor element integrated circuit device shown in FIG. 4, the optical semiconductor element 6 is adversely affected by the heat from the impedance matching resistance element 8, and therefore, the optical semiconductor element. It has a drawback that the function as an integrated circuit device is not fully exhibited.
【００２４】また、図４に示す従来の光半導体素子集積
回路装置の場合、インピ―ダンス整合用抵抗素子８を必
要とする、という欠点を有していた。Further, the conventional optical semiconductor element integrated circuit device shown in FIG. 4 has a drawback that the impedance matching resistance element 8 is required.
【００２５】さらに、図４に示す従来の光半導体素子集
積回路装置の場合、光半導体素子６が、基板２上にでは
なく、ヒ―トシンク用板体５を用いて、支持体１上に配
されているので、光半導体素子集積回路装置を構成する
のに多くの工程を要するなどの欠点を有していた。Further, in the case of the conventional optical semiconductor element integrated circuit device shown in FIG. 4, the optical semiconductor element 6 is arranged not on the substrate 2 but on the support 1 using the heat sink plate 5. Therefore, it has a drawback that many steps are required to construct an optical semiconductor element integrated circuit device.
【００２６】よって、本発明は、上述した欠点のない、
新規な光半導体素子集積回路装置を提案せんとするもの
である。Therefore, the present invention does not have the above-mentioned drawbacks.
A new optical semiconductor element integrated circuit device is proposed.
【００２７】[0027]
【課題を解決するための手段】本発明による光半導体素
子集積回路装置は、図４で上述した従来の光半導体素子
集積回路装置の場合と同様に、（ｉ）基板と、（ｉｉ）
光半導体素子と、（ｉｉｉ）上記基板上に配され、且つ
光半導体素子を駆動するための第１の駆動用信号の入力
に応じて第２の駆動用信号を出力する駆動用回路装置
と、（ｉｖ）上記基板上に形成され、且つ上記駆動用回
路装置から出力される上記駆動用信号を上記光半導体素
子に伝達させる伝送線路とを有する。An optical semiconductor element integrated circuit device according to the present invention has an (i) substrate and (ii) as in the case of the conventional optical semiconductor element integrated circuit device described above with reference to FIG.
An optical semiconductor element; and (iii) a driving circuit device which is arranged on the substrate and which outputs a second driving signal in response to input of a first driving signal for driving the optical semiconductor element, (Iv) a transmission line formed on the substrate and transmitting the drive signal output from the drive circuit device to the optical semiconductor element.
【００２８】しかしながら、本発明による光半導体素子
集積回路装置は、このような構成を有する光半導体素子
集積回路装置において、（ｖ）上記駆動用回路装置が、
上記第１の駆動用信号に対する入力インピ―ダンスに比
し十分低い上記第２の駆動用信号に対する出力インピ―
ダンスを有し、また、（ｖｉ）上記半導体素子が、上記
基板上に配されている構成を有する。However, an optical semiconductor element integrated circuit device according to the present invention is an optical semiconductor element integrated circuit device having such a configuration, in which (v) the driving circuit device is:
An output impedance for the second driving signal, which is sufficiently lower than an input impedance for the first driving signal.
And (vi) the semiconductor element is arranged on the substrate.
【００２９】[0029]
【作用・効果】本発明による光半導体素子集積回路装置
によれば、図４で前述した従来の光半導体素子集積回路
装置の場合と同様に、駆動用回路装置に、外部から第１
の駆動用信号を供給させれば、それに応じて、駆動用回
路装置３から、第２の駆動用信号が出力し、そして、そ
の第２の駆動用信号が、伝送線路を介して光半導体素子
に供給され、よって、光半導体素子から第２の駆動用信
号に応じた光が外部に出射する、という光半導体素子集
積回路装置としての機能を呈する。According to the optical semiconductor element integrated circuit device of the present invention, as in the case of the conventional optical semiconductor element integrated circuit device described above with reference to FIG.
Drive signal is supplied from the drive circuit device 3, a second drive signal is output from the drive circuit device 3, and the second drive signal is transmitted via the transmission line to the optical semiconductor element. Is supplied to the optical semiconductor element, and thus the light corresponding to the second drive signal is emitted from the optical semiconductor element to the outside, thus exhibiting a function as an optical semiconductor element integrated circuit device.
【００３０】しかしながら、本発明による光半導体素子
集積回路装置の場合、駆動用回路装置が、第１の駆動用
信号に対する入力インピ―ダンスに比し十分低い第２の
駆動用信号に対する出力インピ―ダンスを有することか
ら、伝送線路を、駆動用回路装置の出力インピ―ダンス
と等しい、図４で前述した従来の光半導体素子集積回路
装置の場合に比し十分低い特性インピ―ダンスを有する
ものとすることができる。However, in the case of the optical semiconductor element integrated circuit device according to the present invention, the driving circuit device has an output impedance for the second driving signal which is sufficiently lower than the input impedance for the first driving signal. Therefore, the transmission line has a characteristic impedance equal to the output impedance of the driving circuit device, which is sufficiently lower than that of the conventional optical semiconductor element integrated circuit device described above with reference to FIG. be able to.
【００３１】このため、駆動用回路装置からの第２の駆
動用信号を、光半導体素子に、インピ―ダンス整合用抵
抗素子を介して供給するようにしても、そのインピ―ダ
ンス整合用抵抗素子の値を、光半導体素子の同じ入力イ
ンピ―ダンスで、図４で前述した従来の光半導体素子集
積回路装置の場合に比し格段的に小さくすることがで
き、従って、光半導体素子集積回路装置としての機能を
得るとき、インピ―ダンス整合用抵抗素子に発熱がほと
んど伴わないか、伴ってもわずかであり、または、イン
ピ―ダンス整合用抵抗素子を省略することができる。Therefore, even if the second driving signal from the driving circuit device is supplied to the optical semiconductor element through the impedance matching resistance element, the impedance matching resistance element is provided. Can be significantly reduced with the same input impedance of the optical semiconductor device as compared with the conventional optical semiconductor device integrated circuit device described in FIG. When obtaining the function as, the impedance matching resistance element generates little or no heat, or the impedance matching resistance element can be omitted.
【００３２】よって、光半導体素子が、外部からの熱に
よって悪影響を受ける、ということを有効に回避させる
ことができ、従って、光半導体素子集積回路装置として
の機能を十分発揮する。Therefore, it is possible to effectively avoid that the optical semiconductor element is adversely affected by heat from the outside, and therefore, the function as an optical semiconductor element integrated circuit device can be sufficiently exerted.
【００３３】また、本発明による光半導体素子集積回路
装置の場合、上述したように、インピ―ダンス整合用抵
抗素子を省略することができる。In the case of the optical semiconductor element integrated circuit device according to the present invention, the impedance matching resistance element can be omitted as described above.
【００３４】さらに、本発明による光半導体素子集積回
路装置の場合、光半導体素子が、基板上に、駆動用回路
装置とともに並置して配列されているので、光半導体素
子集積回路装置を構成するのに、図４で前述した従来の
光半導体素子集積回路装置の場合に比し少ない工程しか
必要としない。Further, in the case of the optical semiconductor element integrated circuit device according to the present invention, since the optical semiconductor elements are arranged side by side on the substrate together with the driving circuit device, the optical semiconductor element integrated circuit device is constructed. In addition, fewer steps are required than in the case of the conventional optical semiconductor element integrated circuit device described above with reference to FIG.
【００３５】[0035]
【実施例１】次に、図１を伴って、本発明による光半導
体素子集積回路装置の第１の実施例を述べよう。First Embodiment Next, a first embodiment of an optical semiconductor element integrated circuit device according to the present invention will be described with reference to FIG.
【００３６】図１において、図４との対応部分には同一
符号を付し、詳細説明を省略する。In FIG. 1, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.
【００３７】図１に示す本発明による光半導体素子集積
回路装置は、（ａ）駆動用回路装置３が、後端面３ｄ側
の端子片４ａ及び４ｂと同様の端子片を用いて入力され
る第１の駆動用信号に対する入力インピ―ダンスに比し
十分低い、従って、図４で前述した従来の光半導体素子
集積回路装置の場合に比し十分低い、端子片４ａ及び４
ｂに出力される第２の駆動用信号に対する出力インピ―
ダンスを有し、また、（ｂ）これに応じて、インピ―ダ
ンス整合用抵抗素子８が、図４で前述した従来の光半導
体素子集積回路装置の場合に比し十分低い値を有し、さ
らに、（ｃ）ヒ―トシンク用板体５が省略され、また、
（ｄ）これに応じて、伝送線路７を構成している接地用
の対の導体層７ｂの前方遊端が、基板２の前端部上にお
い連結するように延長され、そして、それら導体層７ｂ
の延長部上に、光半導体素子６が、その電極６ｂを導体
層７ｂの遊端部に連結して配され、さらに、（ｅ）これ
に応じて、リボン状接続導体９ｂが省略されていること
を除いて、図４で前述した従来の光半導体素子集積回路
装置と同様の構成を有する。In the optical semiconductor element integrated circuit device according to the present invention shown in FIG. 1, (a) the driving circuit device 3 is input using terminal pieces similar to the terminal pieces 4a and 4b on the rear end face 3d side. 1 is sufficiently lower than the input impedance for the driving signal of 1, and is therefore sufficiently lower than the case of the conventional optical semiconductor element integrated circuit device described above with reference to FIG.
Output impedance for the second drive signal output to b
And (b) accordingly, the impedance matching resistance element 8 has a sufficiently low value as compared with the case of the conventional optical semiconductor element integrated circuit device described above with reference to FIG. Further, (c) the plate 5 for heat sink is omitted, and
(D) Correspondingly, the forward free ends of the pair of grounding conductor layers 7b constituting the transmission line 7 are extended so as to be connected on the front end portion of the substrate 2, and the conductor layers 7b
The optical semiconductor element 6 is arranged on the extended portion of the above, connecting the electrode 6b to the free end portion of the conductor layer 7b, and further, (e) accordingly, the ribbon-shaped connecting conductor 9b is omitted. Except for this, it has the same configuration as the conventional optical semiconductor element integrated circuit device described above with reference to FIG.
【００３８】以上が、本発明による光半導体素子集積回
路装置の第１の実施例の構成である。The above is the configuration of the first embodiment of the optical semiconductor element integrated circuit device according to the present invention.
【００３９】このような構成を有する本発明による光半
導体素子集積回路装置によれば、上述した事項を除い
て、図４で前述した従来の光半導体素子集積回路装置と
同様の構成を有するので、詳細説明は省略するが、図４
で前述した従来の光半導体素子集積回路装置の場合と同
様の、光半導体素子集積回路装置としての機能を呈す
る。The optical semiconductor element integrated circuit device according to the present invention having such a configuration has the same configuration as that of the conventional optical semiconductor element integrated circuit device described above with reference to FIG. 4, except for the above matters. Although detailed description is omitted, FIG.
The same function as the optical semiconductor element integrated circuit device as in the case of the conventional optical semiconductor element integrated circuit device described above is exhibited.
【００４０】しかしながら、図１に示す本発明による光
半導体素子集積回路装置の場合、駆動用回路装置３が、
第１の駆動用信号に対する入力インピ―ダンスに比し十
分低い第２の駆動用信号に対する出力インピ―ダンスを
有することから、伝送線路７を、駆動用回路装置３の出
力インピ―ダンスと等しい、図４で前述した従来の光半
導体素子集積回路装置の場合に比し十分低い特性インピ
―ダンスを有するものとすることができる。However, in the case of the optical semiconductor element integrated circuit device according to the present invention shown in FIG. 1, the driving circuit device 3 is
Since the output impedance for the second driving signal is sufficiently lower than the input impedance for the first driving signal, the transmission line 7 is equal to the output impedance of the driving circuit device 3. It can have a characteristic impedance sufficiently lower than that of the conventional optical semiconductor element integrated circuit device described with reference to FIG.
【００４１】このため、駆動用回路装置３からの第２の
駆動用信号を、光半導体素子６に、インピ―ダンス整合
用抵抗素子８を介して供給するようにしているが、その
インピ―ダンス整合用抵抗素子８の値を、光半導体素子
６の同じ入力インピ―ダンスで、図４で前述した従来の
光半導体素子集積回路装置の場合に比し格段的に小さく
することができ、従って、光半導体素子集積回路装置と
しての機能を得るとき、インピ―ダンス整合用抵抗素子
８に発熱がほとんど伴わないか、伴ってもわずかであ
る。For this reason, the second driving signal from the driving circuit device 3 is supplied to the optical semiconductor element 6 via the impedance matching resistance element 8. The value of the matching resistance element 8 can be significantly reduced with the same input impedance of the optical semiconductor element 6 as compared with the case of the conventional optical semiconductor element integrated circuit device described above with reference to FIG. When the function as the optical semiconductor element integrated circuit device is obtained, the impedance matching resistance element 8 hardly generates heat, or even slightly.
【００４２】よって、光半導体素子６が、インピ―ダン
ス整合用抵抗素子８からの熱によって悪影響を受けれ
る、ということを有効に回避することができ、従って、
光半導体素子集積回路装置としての機能を十分発揮す
る。Therefore, it is possible to effectively prevent the optical semiconductor element 6 from being adversely affected by the heat from the impedance matching resistance element 8, and thus,
The function as an optical semiconductor element integrated circuit device is sufficiently exhibited.
【００４３】さらに、本発明による光半導体素子集積回
路装置の場合、光半導体素子６が、基板２上に、駆動用
回路装置３とともに並置して配列されているので、光半
導体素子集積回路装置を構成するのに、図４で前述した
従来の光半導体素子集積回路装置の場合に比し少ない工
程しか必要としない。Further, in the case of the optical semiconductor element integrated circuit device according to the present invention, since the optical semiconductor element 6 is arranged side by side on the substrate 2 together with the driving circuit device 3, the optical semiconductor element integrated circuit device is The configuration requires fewer steps than the conventional optical semiconductor element integrated circuit device described with reference to FIG.
【００４４】[0044]
【実施例２】次に、図２を伴って、本発明による光半導
体素子集積回路装置の第２の実施例を述べよう。Second Embodiment Next, a second embodiment of an optical semiconductor element integrated circuit device according to the present invention will be described with reference to FIG.
【００４５】図２において、図１との対応部分には同一
符号を付し、詳細説明を省略する。2, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.
【００４６】図２に示す本発明による光半導体素子集積
回路装置は、（ａ）インピ―ダンス整合用抵抗素子８が
省略され、また、（ｂ）これに応じて、リボン状接続導
体９ａの、光半導体素子６側とは反対側の一端が、伝送
線路７を構成している導体層７ａの前方遊端に連結され
ていることを除いて、図１に示す本発明による光半導体
素子集積回路装置と同様の構成を有する。In the optical semiconductor element integrated circuit device according to the present invention shown in FIG. 2, (a) the impedance matching resistance element 8 is omitted, and (b) accordingly, the ribbon-shaped connecting conductor 9a is The optical semiconductor element integrated circuit according to the present invention shown in FIG. 1 except that one end on the side opposite to the optical semiconductor element 6 side is connected to the forward free end of the conductor layer 7a forming the transmission line 7. It has the same configuration as the device.
【００４７】以上が、本発明による光半導体素子集積回
路装置の第２の実施例の構成である。The above is the configuration of the second embodiment of the optical semiconductor element integrated circuit device according to the present invention.
【００４８】このような構成を有する本発明による光半
導体素子集積回路装置によれば、上述した事項を除い
て、図１に示す本発明による光半導体素子集積回路装置
と同様の構成を有するので、詳細説明は省略するが、図
１に示す本発明による光半導体素子集積回路装置の場合
と同様の作用効果を得ることができる。The optical semiconductor element integrated circuit device according to the present invention having such a configuration has the same configuration as the optical semiconductor element integrated circuit device according to the present invention shown in FIG. 1 except for the above matters. Although detailed description is omitted, it is possible to obtain the same effects as those of the optical semiconductor element integrated circuit device according to the present invention shown in FIG.
【００４９】ただし、図２に示す本発明による光半導体
素子集積回路装置の場合、図１に示す本発明による光半
導体素子集積回路装置で用いているインピ―ダンス整合
用抵抗素子８を必要としないとともに、インピ―ダンス
整合用抵抗素子８を有しない分、図１に示す本発明によ
る光半導体素子集積回路装置の場合に比し、熱的にも、
優れている。However, the optical semiconductor element integrated circuit device according to the present invention shown in FIG. 2 does not require the impedance matching resistance element 8 used in the optical semiconductor element integrated circuit device according to the present invention shown in FIG. At the same time, since the impedance matching resistance element 8 is not provided, compared with the case of the optical semiconductor element integrated circuit device according to the present invention shown in FIG.
Are better.
【００５０】[0050]
【実施例３】次に、図３を伴って、本発明による光半導
体素子集積回路装置の第３の実施例を述べよう。Third Embodiment Next, a third embodiment of an optical semiconductor element integrated circuit device according to the present invention will be described with reference to FIG.
【００５１】図３において、図２との対応部分には同一
符号を付し、詳細説明を省略する。3, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.
【００５２】図３に示す本発明による光半導体素子集積
回路装置は、（ａ）伝送線路７を構成している接地用の
対の導体層８ｂが、基板２の主面２ａ上の面状の１つの
導体層８ｂとなされ、そして、その面状の導電性層８ｂ
上に、誘電体層１０が配され、その誘電体層１０上に信
号用の導体層８ａが配されていることによって、伝送線
路７がコプレナ型の構成であるのに代え、マイクロスト
リップ型に構成されていることを除いて、図２に示す本
発明による光半導体素子集積回路装置の場合と同様の構
成を有する。In the optical semiconductor element integrated circuit device according to the present invention shown in FIG. 3, (a) the pair of grounding conductor layers 8b forming the transmission line 7 are planar on the main surface 2a of the substrate 2. One conductor layer 8b, and its planar conductive layer 8b
By disposing the dielectric layer 10 on the dielectric layer 10 and the conductor layer 8a for signal on the dielectric layer 10, the transmission line 7 has a microstrip type instead of the coplanar type configuration. Except for being configured, it has the same configuration as the case of the optical semiconductor element integrated circuit device according to the present invention shown in FIG.
【００５３】以上が、本発明による光半導体素子集積回
路装置の第３の実施例の構成である。The above is the configuration of the third embodiment of the optical semiconductor element integrated circuit device according to the present invention.
【００５４】このような構成を有する図３に示す本発明
による光半導体素子集積回路装置によれば、上述した事
項を除いて、図２の場合と同様の構成を有するので、詳
細説明は省略するが、図２の場合と同様の作用効果が得
られることは明らかである。The optical semiconductor element integrated circuit device according to the present invention shown in FIG. 3 having such a configuration has the same configuration as that of FIG. 2 except for the matters described above, and therefore detailed description thereof will be omitted. However, it is clear that the same operational effect as in the case of FIG. 2 can be obtained.
【００５５】なお、上述においては本発明のわずかな例
を示したに留まり、本発明の精神を脱することなしに、
種々の変型、変更をなし得るであろう。In the above description, only a few examples of the present invention are shown, and without departing from the spirit of the present invention,
Various modifications and changes could be made.
【図１】本発明による光半導体素子集積回路装置の第１
の実施例を示す略線的斜視図である。FIG. 1 is a first optical semiconductor element integrated circuit device according to the present invention.
FIG. 3 is a schematic perspective view showing the embodiment of FIG.
【図２】本発明による光半導体素子集積回路装置の第２
の実施例を示す略線的斜視図である。FIG. 2 is a second optical semiconductor element integrated circuit device according to the present invention.
FIG. 3 is a schematic perspective view showing the embodiment of FIG.
【図３】本発明による光半導体素子集積回路装置の第３
の実施例を示す略線的斜視図である。FIG. 3 is a third view of an optical semiconductor element integrated circuit device according to the present invention.
FIG. 3 is a schematic perspective view showing the embodiment of FIG.
【図４】従来の光半導体素子集積回路装置を示す略線的
斜視図である。FIG. 4 is a schematic perspective view showing a conventional optical semiconductor element integrated circuit device.
１ 支持体 ２ 基板 ３ 駆動用回路装置 ４ａ、４ｂ 端子片 ５ ヒ―トシンク用板体 ６ 光半導体素子 ６ａ、６ｂ 電極 ７ 伝送線路 ８ インピ―ダンス整合用抵抗素子 ９ａ、９ｂ リボン状接続導体 １０ 誘電体層 1 Support 2 Substrate 3 Driving Circuit Device 4a, 4b Terminal Piece 5 Heat Sink Plate 6 Optical Semiconductor Element 6a, 6b Electrode 7 Transmission Line 8 Impedance Matching Resistance Element 9a, 9b Ribbon Connection Conductor 10 Dielectric Body layer
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成５年７月７日[Submission date] July 7, 1993
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】全図[Correction target item name] All drawings
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図１】 [Figure 1]
【図２】 [Fig. 2]
【図３】 [Figure 3]
【図４】 ─────────────────────────────────────────────────────
[Figure 4] ─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成６年８月１８日[Submission date] August 18, 1994
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】全文[Correction target item name] Full text
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【書類名】 明細書[Document name] Statement
【発明の名称】 光半導体素子集積回路装置Title: Optical semiconductor element integrated circuit device
【特許請求の範囲】[Claims]
【発明の詳細な説明】Detailed Description of the Invention
【０００１】[0001]
【産業上の利用分野】本発明は、光半導体素子集積回路
装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor element integrated circuit device.
【０００２】[0002]
【従来の技術】従来、図４を伴って次に述べる光半導体
素子集積回路装置が提案されている。2. Description of the Related Art Conventionally, an optical semiconductor element integrated circuit device described below with reference to FIG. 4 has been proposed.
【０００３】すなわち、平らな絶縁性主面１ａを有する
支持体１を有する。That is, it has a support 1 having a flat insulating main surface 1a.
【０００４】また、相対向する平らな絶縁性主面２ａ及
び２ｂと平らな絶縁性前端面２ｃとを有し、そして、一
方の絶縁性主面２ｂを支持体１の絶縁性主面１ａ側とし
た状態で、支持体１の絶縁性主面１ａ上に配されている
基板２を有する。Further, it has flat insulating main surfaces 2a and 2b facing each other and a flat insulating front end surface 2c, and one insulating main surface 2b is located on the insulating main surface 1a side of the support 1. In this state, the substrate 2 is provided on the insulating main surface 1a of the support 1.
【０００５】また、相対向する絶縁性主面３ａ及び３ｂ
と相対向する絶縁性前端面３ｃ及び絶縁性後端面３ｄと
を有し、そして、一方の絶縁性主面３ｂを基板２側とし
た状態で、基板２上に配されている駆動用回路装置３を
有する。Further, the insulating main surfaces 3a and 3b facing each other are provided.
A driving circuit device having an insulative front end face 3c and an insulative rear end face 3d facing each other, and one insulative main face 3b being on the substrate 2 side and arranged on the substrate 2. Have three.
【０００６】この場合、駆動用回路装置３は、絶縁性前
端面３ｃから前方に突出延長している、信号用端子片４
ａ及びそれを挟むように配された対の接地用端子片４ｂ
と、後端面３ｄから後方に突出延長している、信号用端
子片４ａ及び接地用端子片４ｂとそれぞれ同様の信号用
端子片及び接地用端子片（いずれも図示せず）とを有
し、そして、後端面３ｄ側の信号用端子片４ａ及び接地
用端子片４ｂとそれぞれ同様の信号用端子片及び接地用
端子片を用いて入力される第１の駆動用信号の入力に応
じて、信号用端子片４ａ及び接地用端子片４ｂ間に、第
２の駆動用信号を出力する構成を有する。In this case, the driving circuit device 3 has a signal terminal piece 4 extending forward from the insulating front end surface 3c.
a and a pair of grounding terminal pieces 4b arranged so as to sandwich it
And a signal terminal piece 4a and a grounding terminal piece 4b, which are projectingly extended rearward from the rear end surface 3d, and are similar to the signal terminal piece and the grounding terminal piece (both not shown), Then, in response to the input of the first driving signal input using the signal terminal piece and the grounding terminal piece similar to the signal terminal piece 4a and the grounding terminal piece 4b on the rear end face 3d side, respectively, A second driving signal is output between the power terminal piece 4a and the grounding terminal piece 4b.
【０００７】また、駆動用回路装置３は、後端面３ｄ側
の信号用端子片４ａ及び接地用端子片４ｂとそれぞれ同
様の信号用端子片及び接地用端子片からみたそれらを用
いて入力される第１の駆動用信号に対する入力インピ―
ダンスと等しい、前端面３ｃ側の信号用端子片４ａ及び
接地用端子片４ｂ間からみたそれら間から出力される第
２の駆動用信号に対する出力インピ―ダンスを有してい
る。Further, the driving circuit device 3 is input by using those similar to the signal terminal piece 4a and the grounding terminal piece 4b on the rear end face 3d side as seen from the signal terminal piece and the grounding terminal piece, respectively. Input impedance for the first drive signal
The output impedance is equal to the dance and for the second driving signal output from between the signal terminal piece 4a and the grounding terminal piece 4b on the front end face 3c side as seen from between them.
【０００８】この場合、第１の駆動用信号に対する入力
インピ―ダンスは、５０Ωであるのを普通とし、従っ
て、第２の駆動用信号に対する出力インピ―ダンスも、
５０Ωであるのを普通とする。In this case, the input impedance for the first drive signal is usually 50Ω, and therefore the output impedance for the second drive signal is also
It is usually 50Ω.
【０００９】また、相対向する導電性主面５ａ及び５ｂ
と、相対向する導電性前端面５ｃ及び導電性後端面５ｄ
とを有し、そして、一方の導電性主面５ｂ側を支持体１
側として、支持体１上に、基板２が配されている位置よ
りも前方位置において、それと近接して、固定して配さ
れているヒ―トシンク用板体５を有する。Further, the conductive main surfaces 5a and 5b facing each other are provided.
And a conductive front end surface 5c and a conductive rear end surface 5d which face each other.
And having one conductive main surface 5b side on the support 1
On the side, the heat sink plate 5 is fixedly arranged on the support 1 at a position in front of the position where the substrate 2 is arranged, in close proximity thereto.
【００１０】さらに、相対向する主面上にそれぞれ設け
られた電極６ａ及び６ｂと、前端面による光出射面６ｃ
とを有し、そして、一方の電極６ｂをヒ―トシンク用板
体５側として、ヒ―トシンク用板体５上に固定して配さ
れている光半導体素子６を有する。Furthermore, electrodes 6a and 6b respectively provided on the main surfaces facing each other, and a light emitting surface 6c formed by the front end surface.
And an optical semiconductor element 6 fixedly arranged on the heat sink plate 5 with one of the electrodes 6b as the heat sink plate 5 side.
【００１１】この場合、光半導体素子６は、電極６ａ及
び６ｂでみて、４〜７Ωというような、駆動用回路装置
３の第２の駆動用信号に対する出力インピ―ダンスに比
し十分低い入力インピ―ダンスを有するのを普通とす
る。In this case, the optical semiconductor element 6 has an input impedance that is sufficiently low as compared with the output impedance of the drive circuit device 3 for the second drive signal, such as 4 to 7 Ω as viewed from the electrodes 6a and 6b. -It is normal to have a dance.
【００１２】また、一端を駆動用回路装置３の信号用端
子片４ａに連結して基板２の絶縁性主面２ａ上に前後方
向に延長して設けられている導体層７ａと、一端を駆動
用回路装置３の対の接地用端子片４ｂに連結して基板２
の主面２ａ上に前後方向に、導体層７ａを挟み且つ導体
層７ａと平行に延長して配されている対の導体層７ｂと
で形成されたコプレナ型の伝送線路７を有する。Further, a conductor layer 7a, which has one end connected to the signal terminal piece 4a of the driving circuit device 3 and extends in the front-rear direction on the insulating main surface 2a of the substrate 2, and one end is driven. Circuit board 3 is connected to a pair of grounding terminal pieces 4b and connected to substrate 2
A coplanar transmission line 7 is formed on the main surface 2a in the front-rear direction and is formed by a pair of conductor layers 7b sandwiching the conductor layer 7a and extending in parallel with the conductor layer 7a.
【００１３】この場合、伝送線路７は、導体層７ａ及び
７ｂ間でみて、駆動用回路装置３の信号用端子片４ａ及
び接地用端子片４ｂ間でみた第２の駆動信号に対する出
力インピ―ダンスと等しい特性インピ―ダンスを有し、
従って、５０Ωの特性インピ―ダンスを有するのを普通
とする。In this case, the transmission line 7 has an output impedance for the second drive signal as seen between the signal terminal piece 4a and the grounding terminal piece 4b of the drive circuit device 3 as seen between the conductor layers 7a and 7b. Has a characteristic impedance equal to
Therefore, it is common to have a characteristic impedance of 50Ω.
【００１４】さらに、前後端部の周りにそれぞれ設けら
れた対の電極８ａ及び８ｂを有し、そして、一方の電極
８ｂを伝送線路７の導体層７ａの前方遊端部に上方から
連結し、他方の電極８ａを前方に位置させた状態で、基
板２の主面２ａ上の前方端部上に固定して配されている
インピ―ダンス整合用抵抗素子８を有する。Further, it has a pair of electrodes 8a and 8b respectively provided around the front and rear ends, and one electrode 8b is connected to the front free end of the conductor layer 7a of the transmission line 7 from above. The impedance matching resistance element 8 is fixedly arranged on the front end portion on the main surface 2a of the substrate 2 with the other electrode 8a positioned in the front.
【００１５】また、インピ―ダンス整合用抵抗素子８の
電極８ａと、光半導体素子６の電極６ａとを連結してい
るリボン状接続用導体９ａと、伝送線路７の対の導体層
７ｂとヒ―トシンク用板体５の導電性主面５ａとを連結
している対のリボン状接続用導体９ｂとを有する。A ribbon-shaped connecting conductor 9a connecting the electrode 8a of the impedance matching resistance element 8 and the electrode 6a of the optical semiconductor element 6, a pair of conductor layers 7b of the transmission line 7, and a conductor. -A pair of ribbon-shaped connecting conductors 9b connecting the conductive main surface 5a of the tosink plate 5 to each other.
【００１６】この場合、インピ―ダンス整合用抵抗素子
８は、インピ―ダンス整合用抵抗素子８の電極８ｂの伝
送線路７の導体層７ａとの連結点と、リボン状接続用導
体９ｂの伝送線路７の導体層７ｂとの連結点との間か
ら、光半導体素子６側をみたインピ―ダンスが、伝送線
路７の特性インピ―ダンスと等しくなる値を有する。す
なわち、インピ―ダンス整合用抵抗素子８と光半導体素
子６とが近接して配され、従って、リボン状接続用導体
９ａ及び９ｂがその抵抗を無視し得るに十分なだけ短い
ものとして、伝送線路７の５０Ωの特性インピ―ダンス
から光半導体素子６の入力インピ―ダンスを引いた値を
有し、従って、４３〜４６Ω（（５０Ω−７Ω）〜（５
０Ω−４Ω））の値を有するのを普通とする。In this case, the impedance matching resistance element 8 has a connection point between the electrode 8b of the impedance matching resistance element 8 and the conductor layer 7a of the transmission line 7 and the transmission line of the ribbon-shaped connecting conductor 9b. The impedance seen from the optical semiconductor element 6 side from the point of connection with the conductor layer 7b of 7 has a value equal to the characteristic impedance of the transmission line 7. That is, the impedance matching resistance element 8 and the optical semiconductor element 6 are arranged close to each other, so that the ribbon-shaped connecting conductors 9a and 9b are sufficiently short so that their resistance can be neglected. It has a value obtained by subtracting the input impedance of the optical semiconductor element 6 from the characteristic impedance of 50Ω of 7 and therefore 43 to 46Ω ((50Ω-7Ω) to (5
It is common to have values of 0Ω-4Ω)).
【００１７】以上が、従来提案されている光半導体素子
集積回路装置の構成である。The above is the configuration of the conventionally proposed optical semiconductor element integrated circuit device.
【００１８】このような構成を有する従来の光半導体素
子集積回路装置によれば、駆動用回路装置３に、その後
端面３ｄ側の、信号用端子片４ａ及び接地用端子片４ｂ
とそれぞれ同様の信号用端子片及び接地用端子片を用い
て、第１の駆動用信号を、外部から供給させれば、それ
に応じて、駆動用回路装置３の前端面３ｃ側の信号用端
子片４ａ及び接地用端子片４ｂ間から、第２の駆動用信
号が出力し、そして、その第２の駆動用信号が、伝送線
路７を介し、次でインピ―ダンス整合用抵抗素子８、リ
ボン状接続導体９ａ及び９ｂを通じて、光半導体素子６
に供給され、よって、光半導体素子６の光出射面６ｃか
ら、第２の駆動用信号に応じた光が外部に出射する、と
いう光半導体素子集積回路装置としての機能を呈する。According to the conventional optical semiconductor element integrated circuit device having such a configuration, the driving circuit device 3 has the signal terminal piece 4a and the grounding terminal piece 4b on the rear end face 3d side.
If the first driving signal is supplied from the outside by using the same signal terminal piece and grounding terminal piece, respectively, the signal terminal on the front end face 3c side of the driving circuit device 3 is correspondingly supplied. A second driving signal is output from between the piece 4a and the grounding terminal piece 4b, and the second driving signal is transmitted through the transmission line 7 and then to the impedance matching resistance element 8 and the ribbon. The optical semiconductor element 6 through the linear connection conductors 9a and 9b.
The optical semiconductor element 6 has a function as an optical semiconductor element integrated circuit device in which light corresponding to the second driving signal is emitted to the outside from the light emitting surface 6c of the optical semiconductor element 6.
【００１９】[0019]
【発明が解決しようとする課題】図４に示す従来の光半
導体素子集積回路装置の場合、駆動用回路装置３が、そ
れに外部から供給される第１の駆動用信号に対する入力
インピ―ダンスと等しい、端子片４ａ及び４ｂ間に出力
される第２の駆動用信号に対する出力インピ―ダンスを
有し、そして、入力インピ―ダンが５０Ωであるのを普
通とすることから、出力インピ―ダンスが５０Ωである
のを普通とし、従って出力インピ―ダンスが比較的高い
値を有する。In the case of the conventional optical semiconductor element integrated circuit device shown in FIG. 4, the driving circuit device 3 has an input impedance equal to the first driving signal supplied from the outside. , Has an output impedance for the second drive signal output between the terminal pieces 4a and 4b, and since the input impedance is normally 50Ω, the output impedance is 50Ω. , And thus the output impedance has a relatively high value.
【００２０】このため、伝送線路７が、駆動用回路装置
３の出力インピ―ダンスと等しい特性インピ―ダンスを
有するが、その特性インピ―ダンスが高い値を有し、一
方、光半導体素子６が、４〜７Ωというような駆動用回
路装置３の第２の駆動用信号に対する出力インピ―ダン
スに比し十分低い入力インピ―ダンスしか有しないこと
から、インピ―ダンス整合用抵抗素子８が４６〜４３Ω
というような十分高い値を有する。Therefore, the transmission line 7 has a characteristic impedance equal to the output impedance of the driving circuit device 3, but the characteristic impedance has a high value, while the optical semiconductor element 6 has The impedance matching resistance element 8 has a value of 46 to 7Ω because it has an input impedance that is sufficiently lower than the output impedance for the second driving signal of the driving circuit device 3 such as 4 to 7Ω. 43Ω
It has a sufficiently high value such as.
【００２１】従って、光半導体素子集積回路装置として
の機能を得るとき、インピ―ダンス整合用抵抗素子８に
無視し得ない発熱を伴う。Therefore, when the function as the optical semiconductor element integrated circuit device is obtained, the resistance element 8 for impedance matching is accompanied by heat generation which cannot be ignored.
【００２２】一方、インピ―ダンス整合用抵抗素子８が
光半導体素子６に近い位置に配されている。On the other hand, the impedance matching resistance element 8 is arranged at a position close to the optical semiconductor element 6.
【００２３】以上のことから、図４に示す従来の光半導
体素子集積回路装置の場合、光半導体素子６が、インピ
―ダンス整合用抵抗素子８からの熱によって悪影響を受
け、よって、光半導体素子集積回路装置としての機能を
十分発揮しない、という欠点を有していた。From the above, in the case of the conventional optical semiconductor element integrated circuit device shown in FIG. 4, the optical semiconductor element 6 is adversely affected by the heat from the impedance matching resistance element 8, and therefore, the optical semiconductor element. It has a drawback that the function as an integrated circuit device is not fully exhibited.
【００２４】また、図４に示す従来の光半導体素子集積
回路装置の場合、インピ―ダンス整合用抵抗素子８を必
要とする、という欠点を有していた。Further, the conventional optical semiconductor element integrated circuit device shown in FIG. 4 has a drawback that the impedance matching resistance element 8 is required.
【００２５】さらに、図４に示す従来の光半導体素子集
積回路装置の場合、光半導体素子６が、基板２上にでは
なく、ヒ―トシンク用板体５を用いて、支持体１上に配
されているので、光半導体素子集積回路装置を構成する
のに多くの工程を必要とする、という欠点を有してい
た。Further, in the case of the conventional optical semiconductor element integrated circuit device shown in FIG. 4, the optical semiconductor element 6 is arranged not on the substrate 2 but on the support 1 using the heat sink plate 5. Therefore, there is a drawback that many steps are required to construct an optical semiconductor element integrated circuit device.
【００２６】よって、本発明は、上述した欠点のない、
新規な光半導体素子集積回路装置を提案せんとするもの
である。Therefore, the present invention does not have the above-mentioned drawbacks.
A new optical semiconductor element integrated circuit device is proposed.
【００２７】[0027]
【課題を解決するための手段】本発明による光半導体素
子集積回路装置は、図４で上述した従来の光半導体素子
集積回路装置の場合と同様に、（ｉ）基板と、（ｉｉ）
光半導体素子と、（ｉｉｉ）上記基板上に配され、且つ
光半導体素子を駆動するための第１の駆動用信号の入力
に応じて第２の駆動用信号を出力する駆動用回路装置
と、（ｉｖ）上記基板上に形成され、且つ上記駆動用回
路装置から出力される上記第２の駆動用信号を上記光半
導体素子に伝達させる伝送線路とを有する。An optical semiconductor element integrated circuit device according to the present invention has an (i) substrate and (ii) as in the case of the conventional optical semiconductor element integrated circuit device described above with reference to FIG.
An optical semiconductor element; and (iii) a driving circuit device which is arranged on the substrate and which outputs a second driving signal in response to input of a first driving signal for driving the optical semiconductor element, (Iv) a transmission line formed on the substrate and transmitting the second driving signal output from the driving circuit device to the optical semiconductor element.
【００２８】しかしながら、本発明による光半導体素子
集積回路装置は、このような構成を有する光半導体素子
集積回路装置において、（ｖ）上記駆動用回路装置が、
上記第１の駆動用信号に対する入力インピ―ダンスに比
し十分低い上記第２の駆動用信号に対する出力インピ―
ダンスを有し、また、（ｖｉ）上記半導体素子が、上記
基板上に配されている構成を有する。However, an optical semiconductor element integrated circuit device according to the present invention is an optical semiconductor element integrated circuit device having such a configuration, in which (v) the driving circuit device is:
An output impedance for the second driving signal, which is sufficiently lower than an input impedance for the first driving signal.
And (vi) the semiconductor element is arranged on the substrate.
【００２９】[0029]
【作用・効果】本発明による光半導体素子集積回路装置
によれば、図４で前述した従来の光半導体素子集積回路
装置の場合と同様に、駆動用回路装置に、外部から第１
の駆動用信号を供給させれば、それに応じて、駆動用回
路装置３から、第２の駆動用信号が出力し、そして、そ
の第２の駆動用信号が、伝送線路を介して光半導体素子
に供給され、よって、光半導体素子から第２の駆動用信
号に応じた光が外部に出射する、という光半導体素子集
積回路装置としての機能を呈する。According to the optical semiconductor element integrated circuit device of the present invention, as in the case of the conventional optical semiconductor element integrated circuit device described above with reference to FIG.
Drive signal is supplied from the drive circuit device 3, a second drive signal is output from the drive circuit device 3, and the second drive signal is transmitted via the transmission line to the optical semiconductor element. Is supplied to the optical semiconductor element, and thus the light corresponding to the second drive signal is emitted from the optical semiconductor element to the outside, thus exhibiting a function as an optical semiconductor element integrated circuit device.
【００３０】しかしながら、本発明による光半導体素子
集積回路装置の場合、駆動用回路装置が、第１の駆動用
信号に対する入力インピ―ダンスに比し十分低い第２の
駆動用信号に対する出力インピ―ダンスを有することか
ら、伝送線路を、駆動用回路装置の出力インピ―ダンス
と等しい、図４で前述した従来の光半導体素子集積回路
装置の場合に比し十分低い特性インピ―ダンスを有する
ものとすることができる。However, in the case of the optical semiconductor element integrated circuit device according to the present invention, the driving circuit device has an output impedance for the second driving signal which is sufficiently lower than the input impedance for the first driving signal. Therefore, the transmission line has a characteristic impedance equal to the output impedance of the driving circuit device, which is sufficiently lower than that of the conventional optical semiconductor element integrated circuit device described above with reference to FIG. be able to.
【００３１】このため、駆動用回路装置からの第２の駆
動用信号を、光半導体素子に、インピ―ダンス整合用抵
抗素子を介して供給するようにしても、そのインピ―ダ
ンス整合用抵抗素子の値を、光半導体素子の同じ入力イ
ンピ―ダンスで、図４で前述した従来の光半導体素子集
積回路装置の場合に比し格段的に小さくすることがで
き、従って、光半導体素子集積回路装置としての機能を
得るとき、インピ―ダンス整合用抵抗素子に発熱がほと
んど伴わないか、伴ってもわずかであり、または、イン
ピ―ダンス整合用抵抗素子を省略することができる。Therefore, even if the second driving signal from the driving circuit device is supplied to the optical semiconductor element through the impedance matching resistance element, the impedance matching resistance element is provided. Can be significantly reduced with the same input impedance of the optical semiconductor device as compared with the conventional optical semiconductor device integrated circuit device described in FIG. When obtaining the function as, the impedance matching resistance element generates little or no heat, or the impedance matching resistance element can be omitted.
【００３２】よって、光半導体素子が、外部からの熱に
よって悪影響を受ける、ということを有効に回避させる
ことができ、従って、光半導体素子集積回路装置として
の機能を十分良好に発揮する。Therefore, it is possible to effectively avoid that the optical semiconductor element is adversely affected by the heat from the outside, and therefore, the function as the optical semiconductor element integrated circuit device is sufficiently exhibited.
【００３３】また、本発明による光半導体素子集積回路
装置の場合、上述したように、インピ―ダンス整合用抵
抗素子を省略することができる。In the case of the optical semiconductor element integrated circuit device according to the present invention, the impedance matching resistance element can be omitted as described above.
【００３４】さらに、本発明による光半導体素子集積回
路装置の場合、光半導体素子が、基板上に、駆動用回路
装置とともに並置して配列されているので、光半導体素
子集積回路装置を構成するのに、図４で前述した従来の
光半導体素子集積回路装置の場合に比し少ない工程しか
必要としない。Further, in the case of the optical semiconductor element integrated circuit device according to the present invention, since the optical semiconductor elements are arranged side by side on the substrate together with the driving circuit device, the optical semiconductor element integrated circuit device is constructed. In addition, fewer steps are required than in the case of the conventional optical semiconductor element integrated circuit device described above with reference to FIG.
【００３５】[0035]
【実施例１】次に、図１を伴って、本発明による光半導
体素子集積回路装置の第１の実施例を述べよう。First Embodiment Next, a first embodiment of an optical semiconductor element integrated circuit device according to the present invention will be described with reference to FIG.
【００３６】図１において、図４との対応部分には同一
符号を付し、詳細説明を省略する。In FIG. 1, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.
【００３７】図１に示す本発明による光半導体素子集積
回路装置は、図４で前述した光半導体素子集積回路装置
において、（ａ）駆動用回路装置３が、後端面３ｄ側の
信号用端子片４ａ及び接地用端子片４ｂとそれぞれ同様
の信号用端子片及び接地用端子片を用いて入力される第
１の駆動用信号に対する入力インピ―ダンスに比し十分
低い、従って、図４で前述した従来の光半導体素子集積
回路装置の場合に比し十分低い、信号用端子片４ａ及び
接地用端子片４ｂ間でみたそれら間に出力される第２の
駆動用信号に対する出力インピ―ダンスを有し、また、
（ｂ）これに応じて、インピ―ダンス整合用抵抗素子８
が、図４で前述した従来の光半導体素子集積回路装置の
場合に比し十分低い値を有し、さらに、（ｃ）ヒ―トシ
ンク用板体５が省略され、また、（ｄ）これに応じて、
伝送線路７を構成している接地用の対の導体層７ｂの前
方遊端が、基板２の前端部上において連結するように延
長され、そして、それら導体層７ｂの延長部上に、光半
導体素子６が、その電極６ｂを導体層７ｂの遊端部に連
結して配され、さらに、（ｅ）これに応じて、リボン状
接続用導体９ｂが省略されていることを除いて、図４で
前述した従来の光半導体素子集積回路装置と同様の構成
を有する。The optical semiconductor element integrated circuit device according to the present invention shown in FIG. 1 is the same as the optical semiconductor element integrated circuit device described above with reference to FIG. 4, in which (a) the driving circuit device 3 is a signal terminal piece on the rear end face 3d side. 4a and the grounding terminal piece 4b, which are sufficiently lower than the input impedance for the first driving signal input by using the same signal terminal piece and grounding terminal piece, respectively. It has an output impedance for the second driving signal output between the signal terminal piece 4a and the grounding terminal piece 4b which is sufficiently lower than that of the conventional optical semiconductor element integrated circuit device. ,Also,
(B) Accordingly, the impedance matching resistance element 8 is provided.
Has a value sufficiently lower than that of the conventional optical semiconductor element integrated circuit device described above with reference to FIG. 4, and further, (c) the heat sink plate 5 is omitted, and (d) Depending on,
The forward free ends of the pair of grounding conductor layers 7b forming the transmission line 7 are extended so as to be connected on the front end of the substrate 2, and the optical semiconductor is provided on the extension of the conductor layers 7b. The element 6 is arranged by connecting its electrode 6b to the free end of the conductor layer 7b, and (e) accordingly, except that the ribbon-shaped connecting conductor 9b is omitted. The configuration is similar to that of the conventional optical semiconductor element integrated circuit device described above.
【００３８】以上が、本発明による光半導体素子集積回
路装置の第１の実施例の構成である。The above is the configuration of the first embodiment of the optical semiconductor element integrated circuit device according to the present invention.
【００３９】このような構成を有する本発明による光半
導体素子集積回路装置によれば、上述した事項を除い
て、図４で前述した従来の光半導体素子集積回路装置と
同様の構成を有するので、詳細説明は省略するが、図４
で前述した従来の光半導体素子集積回路装置の場合と同
様の、光半導体素子集積回路装置としての機能を呈す
る。The optical semiconductor element integrated circuit device according to the present invention having such a configuration has the same configuration as that of the conventional optical semiconductor element integrated circuit device described above with reference to FIG. 4, except for the above matters. Although detailed description is omitted, FIG.
The same function as the optical semiconductor element integrated circuit device as in the case of the conventional optical semiconductor element integrated circuit device described above is exhibited.
【００４０】しかしながら、図１に示す本発明による光
半導体素子集積回路装置の場合、駆動用回路装置３が、
第１の駆動用信号に対する入力インピ―ダンスに比し十
分低い第２の駆動用信号に対する出力インピ―ダンスを
有することから、伝送線路７を、駆動用回路装置３の出
力インピ―ダンスと等しい、図４で前述した従来の光半
導体素子集積回路装置の場合に比し十分低い特性インピ
―ダンスを有するものとすることができる。However, in the case of the optical semiconductor element integrated circuit device according to the present invention shown in FIG. 1, the driving circuit device 3 is
Since the output impedance for the second driving signal is sufficiently lower than the input impedance for the first driving signal, the transmission line 7 is equal to the output impedance of the driving circuit device 3. It can have a characteristic impedance sufficiently lower than that of the conventional optical semiconductor element integrated circuit device described with reference to FIG.
【００４１】このため、駆動用回路装置３からの第２の
駆動用信号を、光半導体素子６に、インピ―ダンス整合
用抵抗素子８を介して供給するようにしているが、その
インピ―ダンス整合用抵抗素子８の値を、光半導体素子
６の同じ入力インピ―ダンスで、図４で前述した従来の
光半導体素子集積回路装置の場合に比し格段的に小さく
することができ、従って、光半導体素子集積回路装置と
しての機能を得るとき、インピ―ダンス整合用抵抗素子
８に発熱がほとんど伴わないか、伴ってもわずかであ
る。For this reason, the second driving signal from the driving circuit device 3 is supplied to the optical semiconductor element 6 via the impedance matching resistance element 8. The value of the matching resistance element 8 can be significantly reduced with the same input impedance of the optical semiconductor element 6 as compared with the case of the conventional optical semiconductor element integrated circuit device described above with reference to FIG. When the function as the optical semiconductor element integrated circuit device is obtained, the impedance matching resistance element 8 hardly generates heat, or even slightly.
【００４２】よって、光半導体素子６が、インピ―ダン
ス整合用抵抗素子８からの熱によって悪影響を受ける、
ということを有効に回避することができ、従って、光半
導体素子集積回路装置としての機能を十分良好に発揮す
る。Therefore, the optical semiconductor element 6 is adversely affected by the heat from the impedance matching resistance element 8,
This can be effectively avoided, and thus the function as the optical semiconductor element integrated circuit device can be sufficiently exhibited.
【００４３】さらに、図１に示す本発明による光半導体
素子集積回路装置の場合、光半導体素子６が、基板２上
に、駆動用回路装置３とともに並置して配列されている
ので、光半導体素子集積回路装置を構成するのに、図４
で前述した従来の光半導体素子集積回路装置の場合に比
し少ない工程しか必要としない。Further, in the case of the optical semiconductor element integrated circuit device according to the present invention shown in FIG. 1, since the optical semiconductor element 6 is arranged side by side on the substrate 2 together with the driving circuit device 3, the optical semiconductor element is arranged. To construct an integrated circuit device, FIG.
In comparison with the above-mentioned conventional optical semiconductor element integrated circuit device, fewer steps are required.
【００４４】なお、本実施例においては、基板２の前端
部上に光半導体素子６が配されていると述べたが、その
基板２として、光半導体素子６を配している前端部から
さらに前方に延長し、その延長部上にガラス、リチウム
ナイオベートなどの誘電体でなる光導波路で構成された
光回路を配している、例えばＳｉでなる基板を用い、そ
して、その光回路に、光半導体素子６の光出射面６ｃか
ら出射される光を入射させるようにすることができるこ
とは明らかであろう。Although the optical semiconductor element 6 is arranged on the front end portion of the substrate 2 in the present embodiment, the substrate 2 further has a front end portion on which the optical semiconductor element 6 is arranged. An optical circuit that extends forward and has an optical waveguide made of a dielectric such as glass or lithium niobate on the extension is used, for example, a substrate made of Si is used, and in the optical circuit, It will be apparent that the light emitted from the light emitting surface 6c of the optical semiconductor element 6 can be made incident.
【００４５】[0045]
【実施例２】次に、図２を伴って、本発明による光半導
体素子集積回路装置の第２の実施例を述べよう。Second Embodiment Next, a second embodiment of an optical semiconductor element integrated circuit device according to the present invention will be described with reference to FIG.
【００４６】図２において、図１との対応部分には同一
符号を付し、詳細説明を省略する。2, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.
【００４７】図２に示す本発明による光半導体素子集積
回路装置は、図１に示す本発明による光半導体素子集積
回路装置において、（ａ）インピ―ダンス整合用抵抗素
子８が省略され、また、（ｂ）これに応じて、リボン状
接続用導体９ａの、光半導体素子６側とは反対側の一端
が、伝送線路７を構成している導体層７ａの前方遊端に
連結されていることを除いて、図１に示す本発明による
光半導体素子集積回路装置と同様の構成を有する。The optical semiconductor element integrated circuit device according to the present invention shown in FIG. 2 is the same as the optical semiconductor element integrated circuit device according to the present invention shown in FIG. 1, except that (a) the impedance matching resistance element 8 is omitted. (B) Accordingly, one end of the ribbon-shaped connecting conductor 9a on the side opposite to the optical semiconductor element 6 side is connected to the front free end of the conductor layer 7a forming the transmission line 7. The optical semiconductor device integrated circuit device according to the present invention shown in FIG.
【００４８】以上が、本発明による光半導体素子集積回
路装置の第２の実施例の構成である。The above is the configuration of the second embodiment of the optical semiconductor element integrated circuit device according to the present invention.
【００４９】このような構成を有する本発明による光半
導体素子集積回路装置によれば、上述した事項を除い
て、図１に示す本発明による光半導体素子集積回路装置
と同様の構成を有するので、詳細説明は省略するが、図
１に示す本発明による光半導体素子集積回路装置の場合
と同様の作用効果を得ることができる。The optical semiconductor element integrated circuit device according to the present invention having such a configuration has the same configuration as the optical semiconductor element integrated circuit device according to the present invention shown in FIG. 1 except for the above matters. Although detailed description is omitted, it is possible to obtain the same effects as those of the optical semiconductor element integrated circuit device according to the present invention shown in FIG.
【００５０】ただし、図２に示す本発明による光半導体
素子集積回路装置の場合、図１に示す本発明による光半
導体素子集積回路装置で用いているインピ―ダンス整合
用抵抗素子８を必要としないとともに、インピ―ダンス
整合用抵抗素子８を有しない分、図１に示す本発明によ
る光半導体素子集積回路装置の場合に比し、熱的にも、
優れている。However, the optical semiconductor element integrated circuit device according to the present invention shown in FIG. 2 does not require the impedance matching resistance element 8 used in the optical semiconductor element integrated circuit device according to the present invention shown in FIG. At the same time, since the impedance matching resistance element 8 is not provided, compared with the case of the optical semiconductor element integrated circuit device according to the present invention shown in FIG.
Are better.
【００５１】なお、本実施例においても、実施例１の場
合と同様に、基板２として、光半導体素子６を配してい
る前端部からさらに前方に延長しその延長部上に光導波
路で構成された光回路を配している、という基板を用
い、そして、その光回路に、光半導体素子６の光出射面
６ｃから出射される光を入射させるようにすることがで
きることは明らかであろう。Also in this embodiment, as in the case of the first embodiment, the substrate 2 is further extended forward from the front end portion where the optical semiconductor element 6 is arranged, and an optical waveguide is formed on the extended portion. It will be clear that it is possible to use a substrate which has an optical circuit arranged therein and to make the light emitted from the light emitting surface 6c of the optical semiconductor element 6 incident on the substrate. .
【００５２】[0052]
【実施例３】次に、図３を伴って、本発明による光半導
体素子集積回路装置の第３の実施例を述べよう。Third Embodiment Next, a third embodiment of an optical semiconductor element integrated circuit device according to the present invention will be described with reference to FIG.
【００５３】図３において、図２との対応部分には同一
符号を付し、詳細説明を省略する。3, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.
【００５４】図３に示す本発明による光半導体素子集積
回路装置は、図２に示す本発明による光半導体素子集積
回路装置において、（ａ）伝送線路７を構成している接
地用の対の導体層７ｂが、基板２の絶縁性主面２ａ上の
面状の１つの導体層７ｂとなされ、そして、（ｂ）その
面状の導体層７ｂ上に、誘電体層１０が配され、その誘
電体層１０上に信号用の導体層７ａが配されていること
によって、伝送線路７がコプレナ型の構成であるのに代
え、マイクロストリップ型に構成されていることを除い
て、図２に示す本発明による光半導体素子集積回路装置
の場合と同様の構成を有する。The optical semiconductor element integrated circuit device according to the present invention shown in FIG. 3 is the same as the optical semiconductor element integrated circuit device according to the present invention shown in FIG. The layer 7b is formed as one planar conductor layer 7b on the insulating main surface 2a of the substrate 2, and (b) the dielectric layer 10 is arranged on the planar conductor layer 7b, 2 except that the transmission line 7 has a microstrip type configuration instead of the coplanar type configuration because the signal conductor layer 7a is disposed on the body layer 10. It has the same configuration as that of the optical semiconductor element integrated circuit device according to the present invention.
【００５５】以上が、本発明による光半導体素子集積回
路装置の第３の実施例の構成である。The above is the configuration of the third embodiment of the optical semiconductor element integrated circuit device according to the present invention.
【００５６】このような構成を有する図３に示す本発明
による光半導体素子集積回路装置によれば、上述した事
項を除いて、図２の場合と同様の構成を有するので、詳
細説明は省略するが、図２の場合と同様の作用効果が得
られることは明らかである。The optical semiconductor element integrated circuit device according to the present invention shown in FIG. 3 having such a configuration has the same configuration as that of FIG. 2 except for the matters described above, and therefore detailed description thereof will be omitted. However, it is clear that the same operational effect as in the case of FIG. 2 can be obtained.
【００５７】なお、本実施例においては、基板２の絶縁
性主面２ａ上に、誘電体層１０を、それを含んでマイク
ロストップ型の伝送線路７を構成すべく、導体層７ｂを
介して、形成した場合を示しているが、その誘電体層１
０を、光導波路として用い、その光導波路で構成された
光回路を構成するようにすることができることは明らか
であろう。In this embodiment, the dielectric layer 10 is formed on the insulating main surface 2a of the substrate 2 and the conductor layer 7b is interposed so as to form the microstop type transmission line 7 including the dielectric layer 10. , The case of forming the dielectric layer 1 is shown.
It will be apparent that 0 can be used as an optical waveguide to form an optical circuit formed by the optical waveguide.
【００５８】なお、上述においては本発明のわずかな例
を示したに留まり、本発明の精神を脱することなしに、
種々の変型、変更をなし得るであろう。In the above description, only a few examples of the present invention are shown, and without departing from the spirit of the present invention,
Various modifications and changes could be made.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明による光半導体素子集積回路装置の第１
の実施例を示す略線的斜視図である。FIG. 1 is a first optical semiconductor element integrated circuit device according to the present invention.
FIG. 3 is a schematic perspective view showing the embodiment of FIG.
【図２】本発明による光半導体素子集積回路装置の第２
の実施例を示す略線的斜視図である。FIG. 2 is a second optical semiconductor element integrated circuit device according to the present invention.
FIG. 3 is a schematic perspective view showing the embodiment of FIG.
【図３】本発明による光半導体素子集積回路装置の第３
の実施例を示す略線的斜視図である。FIG. 3 is a third view of an optical semiconductor element integrated circuit device according to the present invention.
FIG. 3 is a schematic perspective view showing the embodiment of FIG.
【図４】従来の光半導体素子集積回路装置を示す略線的
斜視図である。FIG. 4 is a schematic perspective view showing a conventional optical semiconductor element integrated circuit device.
【符号の説明】 １ 支持体 １ａ 支持体１の絶縁性主面 ２ 基板 ２ａ、２ｂ 基板２の絶縁性主面 ３ 駆動用回路装置 ３ａ、３ｂ 駆動用回路装置３の主面 ３ｃ 駆動用回路装置３の絶縁性前端面 ３ｄ 駆動用回路装置３の絶縁性後端面 ４ａ 信号用端子片 ４ｂ 接地用端子片 ５ ヒ―トシンク用板体 ５ａ、５ｂ ヒートシンク用板体５の導電性主面 ６ 光半導体素子 ６ａ、６ｂ 光半導体素子６の電極 ６ｃ 光半導体素子６の光出射面 ７ 伝送線路 ７ａ、７ｂ 伝送線路７の導体層 ８ インピ―ダンス整合用抵抗素子 ８ａ、８ｂ インピ―ダンス整合用抵抗素子８の電
極 ９ａ、９ｂ リボン状接続用導体 １０ 誘電体層DESCRIPTION OF SYMBOLS 1 Support 1a Insulating main surface of support 1 2 Substrate 2a, 2b Insulating main surface of substrate 2 Drive circuit device 3a, 3b Main surface of drive circuit device 3 3c Drive circuit device Insulating front end face 3d Insulating rear end face of driving circuit device 4a Signal terminal piece 4b Grounding terminal piece 5 Heat sink plate 5a, 5b Conductive main surface of heat sink plate 5 Optical semiconductor 6 Elements 6a, 6b Electrodes of optical semiconductor element 6 6c Light emission surface of optical semiconductor element 7 Transmission line 7a, 7b Conductor layer of transmission line 7 Impedance matching resistance element 8a, 8b Impedance matching resistance element 8 Electrodes 9a, 9b Ribbon-shaped connection conductor 10 Dielectric layer
───────────────────────────────────────────────────── フロントページの続き (72)発明者 加藤 邦治 東京都千代田区内幸町１丁目１番６号 日 本電信電話株式会社内 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Kuniharu Kato 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation
Claims (1)
ための第１の駆動用信号の入力に応じて、第２の駆動用
信号を出力する駆動用回路装置と、 上記基板上に配され、且つ上記駆動用回路装置から出力
される上記駆動用信号を上記光半導体素子に伝達させる
伝送線路とを有する光半導体素子集積回路装置におい
て、 上記駆動用回路装置が、上記第１の駆動用信号に対する
入力インピ―ダンスに比し十分低い上記第２の駆動用信
号に対する出力インピ―ダンスを有し、 上記半導体素子が、上記基板上に配されていることを特
徴とする光半導体素子集積回路装置。1. A substrate, an optical semiconductor element, and a second drive signal that is arranged on the substrate and that outputs a second drive signal in response to input of a first drive signal for driving the optical semiconductor element. An optical semiconductor element integrated circuit device, comprising: a driving circuit device that operates on the substrate; The driving circuit device has an output impedance for the second driving signal that is sufficiently lower than an input impedance for the first driving signal, and the semiconductor element is arranged on the substrate. An optical semiconductor element integrated circuit device characterized by the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5147012A JPH06334167A (en) | 1993-05-26 | 1993-05-26 | Photo-semiconductor element integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5147012A JPH06334167A (en) | 1993-05-26 | 1993-05-26 | Photo-semiconductor element integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06334167A true JPH06334167A (en) | 1994-12-02 |
Family
ID=15420558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5147012A Pending JPH06334167A (en) | 1993-05-26 | 1993-05-26 | Photo-semiconductor element integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06334167A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008518461A (en) * | 2004-10-25 | 2008-05-29 | クリー インコーポレイテッド | Solid metal block semiconductor light emitting device mounting substrate and package including cavity and heat sink and method for packaging them |
-
1993
- 1993-05-26 JP JP5147012A patent/JPH06334167A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008518461A (en) * | 2004-10-25 | 2008-05-29 | クリー インコーポレイテッド | Solid metal block semiconductor light emitting device mounting substrate and package including cavity and heat sink and method for packaging them |
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