JPH06333805A - Chip for dimensional reference of semiconductor process and dimensional correction method - Google Patents

Abstract

PURPOSE:To provide a reference dimensional sample (reference chip) for semiconductor process wherein pattern dimensional error between processing processes in IC/LSI is reduced. CONSTITUTION:An Si reference dimensional pattern 8 and reference dimensional patterns 9 to 14 of various films formed in each processing process are formed on the same chip. Therefore, a reference chip which is free from dimensional error caused by absorption, scattering, etc., of electron beam based on difference of thickness, waviness, kink, etc., of a wafer can be acquired. Since a reference chip is used, pattern dimensional correction operation of a processing wafer wherein a measurement SEM, etc., is used can be made effective.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample for measuring a process standard dimension of a semiconductor device using charged particles and a processing apparatus, and particularly, it accurately measures a fine dimension of each of a plurality of thin films formed by different processes. The present invention relates to a semiconductor process dimension standard sample suitable for.

[0002]

2. Description of the Related Art In the manufacture of semiconductor devices such as ICs and LSIs, the dimensions of a reference dimension measurement sample (reference chip) prepared for each processing process are measured and used as reference dimensions, and the wafer pattern processed in the process is measured. I was trying to measure the dimensions of the battery. When the pattern dimension is 1 μm or less, the device yield greatly depends on the precision of this dimension measurement. For the above dimension measurement, a measuring SEM
(Scanning Electron Microscope), an optical interference coordinate measuring device, an electron beam drawing device incorporating the same, or the like is used. Further, the above-mentioned conventional reference chip is provided with only one type of reference pattern corresponding to the processing process.

FIG. 8A is a manufacturing process diagram of a conventional photoresist reference chip. After the photoresist 2 is formed on the Si wafer 1, the pattern of the reference pattern mask is exposed and developed by the reduction projection exposure apparatus, and the resist is patterned as shown in FIG. Also, as shown in FIG.
The Si wafer 1 was patterned by dry-etching the openings of the above, and the resist was removed and washed to obtain the Si reference chip as shown in FIG.

In 1988, Nov / Dec J,
Vac. Sci. Technol. B, vol. 6 describes that a Si pattern is directly processed on the Si wafer 1 by laser interference exposure to produce a Si reference chip as shown in FIG. Further, as shown in FIG. 10, patterning is also performed on the SiN film 7 formed on the Si wafer 1.

[0005]

In the conventional IC / LSI manufacturing, a reference chip is prepared for each manufacturing process, the reference chip is measured before patterning, and the measured value is used as a control device (computer) for the process. It was stored in the (-)), and the subsequent processing dimensional accuracy was managed. However, since the reference chip used was one cut out from a different wafer,
The following problems were involved.

That is, as is well known, different wafers have different dimensional errors due to absorption, scattering, etc. of electron beams due to differences in thickness, waviness, twist, etc. As a result, dimensional errors in the reference chip in each process are different. There is confusion in quality control between each process. In particular, submicron dimensional accuracy is required as in a large capacity DRAM, and when the number of processes approaches 30, the yield is rapidly reduced due to the accumulation of the above errors, which has been a serious problem. Further, even in the same process, if the reference chip is replaced with a different wafer, an error occurs.

At present, the IC / LSI processing equipment is calibrated by a reference chip prepared by the manufacturer of the IC / LSI processing equipment.
It is delivered to the user, and the user side creates a reference chip for himself and performs accuracy control, so the dimensional error calculated by the user and the user is inevitably caused by the difference in the reference wafer. There was a case where a discrepancy occurred and a serious trouble occurred. For example, when the exposure time for obtaining a line width of 1.1 μm is calculated from the measurement value of the measurement SEM using the above-mentioned reference chip, the average is 0.80 s at the process site, and the calculated value on the device maker side is 0.91 s. Due to this difference, the error per 1 μm line pitch is -4 at the process site.
%, And 0.5% on the device maker side, which is a big difference. This is because the wafer of the reference chip used at the process site and the device maker side are different. Such problems have become apparent due to the miniaturization of IC / LSI, and ISO (International Standard Or
ganization) has begun to study the standardization of standard size devices for IC / LSI. An object of the present invention is to provide a semiconductor process standard size sample (standard chip) capable of reducing the above-mentioned size measurement error.

[0008]

In order to solve the above-mentioned problems, the above-mentioned reference chip is formed by being cut out from the dimensional reference pattern parts for different semiconductor processes formed on a common wafer. Further, the dimensional reference pattern portion is formed on the process layer formed by the semiconductor process. Further, the reference chip includes a plurality of dimensional reference pattern parts for different semiconductor processes formed on a common wafer.

Further, different dimensional reference pattern portions for different semiconductor processes of the reference chip are sequentially formed on process layers laminated in the order of operation of the semiconductor process. In addition, a dimension reference chip including a plurality of different dimension reference pattern portions for different semiconductor processes formed on the same wafer is mounted in the dimension measurement apparatus, and pattern patterns on the wafer are sequentially formed in the operation order of the semiconductor process. The size of the pattern is calibrated by comparing it with the pattern part of the standard chip for the semiconductor process.

[0010]

By forming pattern reference patterns for different semiconductor processes on a common wafer or forming process layers formed by the semiconductor process, variations in thickness, twist, etc. of the wafer occur. The dimensional deviation between the reference chips disappears. Further, by including a plurality of dimensional reference pattern portions for different semiconductor processes formed on a common wafer in the reference chip, a plurality of semiconductor process devices can be calibrated by the reference chip having a common wafer. It

Further, by sequentially forming the respective pattern patterns for dimensional reference on the process layers laminated in the working order of the semiconductor process, the reference chip dedicated to the semiconductor device manufactured by the semiconductor process is formed. . Further, by mounting the dimension reference chip including the plurality of reference pattern portions in the dimension measuring apparatus, the pattern on the wafer formed for each semiconductor process operation is calibrated without replacing the reference chip. It

[0012]

[Embodiment 1] FIG. 1 is a plan view and a sectional view of an embodiment of a reference chip according to the present invention. In FIG. 1A, one surface of a Si wafer is divided into a plurality of reference chip sections, and reference patterns of various inorganic films required for a series of semiconductor processes are provided in each reference chip 15. Figure 1
As shown in (b), a pattern of Si is formed on the reference chip surface.
Pattern 8, thermal oxidation film pattern 9 of Si, pattern 10 of Poly-Si film, pattern 11 of SiN film, pattern 12 of PSG film (Phosphor Silicate Grass), BPSG
Pattern 13 of the membrane (Born Phosphor Silicate Grass),
An Al film pattern 14 and the like are formed.

The Si thermal oxide film, Poly-Si film, S
The iN film, the PSG film, the BPSG film, the Al film, etc. are formed by using respective processes, and the line width is set to 0.
It should be in the range of 1 to 1 μm. 2 shows the above Si
Poly-Si film or SiN film 31 on the surface of the pattern 8 of
It is sectional drawing of the Example of this invention which formed. In Figure 2,
The Si pattern 8 is processed by the interference exposure method, and the Poly-Si film or the SiN film 31 is formed thereon.
Since the pattern 8 is processed by the laser interference exposure method, the pattern accuracy can be increased to 0.02 μm (3σ) or less.

FIG. 3 is a sectional view of the case where a laminated film 36 of SiO ₂ / PSG / SiN or the like is formed on the Si pattern 8 similarly formed by the laser interference exposure method. Si above
Since a large number of reference chips 15 are obtained from the wafer 1,
By distributing these to each processing device of a series of inorganic film patterns necessary for manufacturing the IC / LSI, each processing device manages its own processing dimension by using a reference chip having a common wafer. You can As a result, it is possible to eliminate the reference dimensional error due to the difference in the thickness and twist of the wafer in the conventional technique.

At present, a wafer called Super Flat Wafer is used, which has good thickness uniformity and flatness. Therefore, as long as the wafer is common, the thickness and flatness are uniform regardless of the cutting position. It is possible to obtain a large number of reference chips.

[Embodiment 2] FIG. 4 is a sectional view of another embodiment of the reference chip according to the present invention. In FIG. 4, FIG.
A reference pattern of the photoresist (organic film) 2 necessary for the next step is formed on the reference chip 15 of the inorganic film shown in FIG. First, a photoresist film 2 is applied onto a wafer 1 of FIG. 1A, dried, and then subjected to a reduction projection exposure method, an electron beam drawing method,
A predetermined reference pattern is formed on the resist 2 by the laser interference exposure method or the like. This standard dimension width is, for example, 0.1 to
It is in the range of 1 μm. Since the reference chip 16 manufactured in this way has the same wafer as the reference chip in the other steps, it is possible to eliminate the reference dimensional error due to the difference in the thickness and twist of the reference chip.

[Third Embodiment] FIG. 5 is a cross-sectional view of another reference chip embodiment according to the present invention. In IC / LSI, since process layers are stacked on a wafer in the order of semiconductor processing steps, it is desirable to form a reference pattern on the reference chip for each process layer formed in the above step order. FIG. 5 is an example of such a reference chip cross section.
First, on the reference chip surface, a pattern 9 of a thermal oxide film of Si and P
Poly-Si film pattern 10, SiN film pattern 1
1, Al film pattern 14 and resist pattern 2,
And Si patterns 8, 81 and the like are sequentially generated. The thermal oxide film covering the Si pattern 81 is formed simultaneously with or separately from the other thermal oxide film 9 depending on the process.

Then, the pattern 9 of the Si thermal oxide film, the pattern 11 of the SiN film and the like in the central portion are covered with the pattern 10 of the Poly-Si film, and further the pattern 1 of the BPSG film.
3. The pattern 12 of the PSG film, the pattern 14 of the Al film, etc. are sequentially formed. As described above, when the reference pattern is formed for each process layer stacked in the order of processing steps of IC / LSI, the height of each process layer is higher than that of each actually manufactured IC / LSI. Is equal to
The focus positions of the exposure device and the electron beam drawing device can be kept the same, and errors due to defocus can be reduced.

[Embodiment 4] In each of the embodiments of the present invention, the IC / L is formed on a chip cut from the same wafer.
A plurality of series of reference patterns required for manufacturing SI were installed. However, as shown in FIG. 6, chips having a single reference pattern are combined according to the number of manufacturing processes and mounted on one table, and the chips are attached to the reference chip 15.
It can also be used instead of.

In FIG. 6, as an example, a Si pattern reference sample 21, a thermal oxide film forming sample 22, and a Poly-Si film pattern reference sample 23 are mounted on the metal susceptor 24, and the metal susceptor 24 is made of metal. It is attached to the jig 25 and the whole is used as one reference sample. Note that, in general, one sheet of Si
A reference pattern for each manufacturing process of the LSI is formed on the wafer, the reference pattern for each manufacturing process is individually cut out, and these are combined to form a jig as shown in FIG.

For example, when the standard pattern number of each manufacturing process is 10 and the standard pattern chip size is 3 mm square and cut out from a 6-inch Si wafer, about 100 standard pattern chips of about 100 each are obtained. Therefore, it is possible to supply the jig 25 having ten types of reference pattern chips taken from the same Si wafer to 100 dimension measuring devices. As a result, an error caused by a difference in wafers does not occur between the 100 dimension measuring devices, so that the pattern size of each processing process of the LSI can be evaluated with extremely high accuracy.

[Embodiment 5] FIG. 7 shows a wafer 10 to be processed using the reference chips 15, 16, 17 and the like according to the present invention.
It is a block diagram of the measuring SEM which performs 0 dimension measurement. In order to simplify the description, the reference chips 15, 16, and 1 will be referred to hereinafter.
7 will be represented by 150 as a representative. In FIG. 7, the wafer 100 to be processed and the reference chip 150 are S for measurement.
It is installed on a table in the chamber 102 of the EM 101.

First, the reference chip 150 is placed within the scanning range of the electron beam, the reference pattern of a predetermined process is scanned by the electron beam 103, and the reference pattern is detected by the secondary electron detection from the reference chip 150. -Detect the pitch dimension of the pitch. Next, the table is moved to move the wafer 100 to be processed.
The processing pattern of the above predetermined process of the electronic beam 103
Scanning by the secondary electron detection, and the processing pattern is detected by the secondary electron detection.
The pitch dimension of the pattern is detected and compared with the pitch dimension of the reference pattern to evaluate the processing error.

In the conventional or processing error evaluation, since the number of reference patterns on the reference chip is one, both the wafer to be processed and the reference chip are replaced and aligned each time the processing process is changed. Had to set. However, in FIG. 7, since the reference chip has the reference pattern corresponding to a large number of processing processes, only the wafer 100 to be processed needs to be taken in and out for each process, and the efficiency of the processing error evaluation work is greatly improved. can do.

[0025]

According to the present invention, it is possible to provide a reference size sample (reference chip) for a semiconductor process in which a pattern size error between different processing processes is reduced. That is, in the present invention, since the reference size pattern for each processing process is formed on the same wafer, the reference size does not have a size error due to absorption or scattering of electron beams due to differences in wafer thickness, waviness, twist, etc. Chips can be provided.

According to the experiment, Si of three processed wafers
The line pattern of the N film with a width of 0.8 μm was measured by using the conventional reference chips of different wafers, and the result was about −5 to 10
% (-0.04 to +0.08 .mu.m), the line width error was about 0 to 2.5% (0 to +0.02 .mu.m) using the reference chip according to the present invention. . From this, it is understood that the present invention can reduce the line width error to about 1/4.

Further, the standard size pattern for each machining process.
Since it is also possible to collectively provide the reference chips on one of the reference chips, it is possible to improve the efficiency of the pattern size calibration work of the wafer to be processed by the reference chips using, for example, a measuring SEM. The present invention has a number of steps close to 30 as in a large capacity DRAM, and when sub-micron dimensional accuracy is required for the same steps, the accumulation of dimensional errors can be reduced and the yield can be improved. it can. Also,
Since a large number of reference chips of the present invention can be taken out from the same wafer, it is possible to maintain a high dimensional accuracy level at the manufacturing site by matching error levels among a plurality of dimension measuring devices.

[Brief description of drawings]

FIG. 1 is a plan view of a wafer according to the present invention and a cross-sectional view of a reference chip embodiment.

FIG. 2 is a cross-sectional view of another pattern of the reference chip according to the present invention.

FIG. 3 is a cross-sectional view of another pattern of the reference chip according to the present invention.

FIG. 4 is a cross-sectional view of another reference chip embodiment according to the present invention.

FIG. 5 is a cross-sectional view of another reference chip embodiment according to the present invention.

FIG. 6 is a cross-sectional view of a reference chip jig according to the present invention.

FIG. 7 is a conceptual diagram of a measuring SEM showing a pattern size calibration method according to the present invention.

FIG. 8 is a manufacturing process diagram of a standard reference chip.

FIG. 9 is a cross-sectional view of a standard reference chip.

FIG. 10 is a cross-sectional view of another reference chip of the traditional model.

[Explanation of symbols] 1 ... Si wafer, 2 ... Photoresist, 3 ... Pattern portion, 4 ... Si pattern, 7 ... SiN film, 8 ... Si pattern, 9 ... Thermal oxide film pattern Pattern of 10, ..., 1
2 ... PSG film pattern, 13 ... BPSG film pattern
14 ... Al film pattern, 15, 16 ... Reference chip, 24 ... Metal susceptor, 25 ... Jig, 100 ... Wafer, 101 ... SEM for measurement, 105 ... Reference chip,
31 ... Poly-Si film / SiN film, 36 ... Laminated film.

Claims (5)

[Claims] 1. A reference chip for pattern size calibration in a semiconductor process, which is formed by cutting out at least one of a plurality of size reference pattern parts for various semiconductor processes formed on a common wafer. A chip for a dimensional reference of a semiconductor process, which is characterized in that 2. The chip for dimensional reference in a semiconductor process according to claim 1, wherein the dimensional reference pattern part is formed in a process layer formed by the semiconductor process. 3. The pattern according to claim 1 or 2.
The reference chip for dimensional calibration is a dimensional reference pattern for different semiconductor processes formed on the common wafer.
A chip for a dimensional reference in a semiconductor process, characterized by including a plurality of internal parts. 4. The dimensional reference pattern part for different semiconductor processes according to claim 4, wherein the different dimensional reference pattern parts are sequentially formed on process layers stacked in the order of operation of the semiconductor device manufacturing process. Chip for dimensional reference of semiconductor process. 5. A pattern size calibration method for a semiconductor process, wherein a pattern size on a wafer is calibrated by measuring both a pattern on a wafer and a pattern of a size reference chip by a size measuring device. On a wafer which is formed in the above-mentioned dimension measuring apparatus, a dimension reference chip including a plurality of dimension reference pattern portions for different semiconductor processes formed on a common wafer is sequentially mounted, and which are sequentially formed in a semiconductor process operation order. A method for calibrating a dimension of a semiconductor process, wherein the dimension of the pattern is calibrated by comparing it with a dimension reference pattern portion of the dimension reference chip for the semiconductor process.