JPH06333398A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent the generation of malfunction and the useless prolongation of a waiting time by outputting a status polling signal and informing the outside that the inside is under reset operation or the reset operation is completed. CONSTITUTION:This memory device is provided with a control circuit 1 and the control circuit 1 controls an I/O buffer 2 and a command register 3 based on the control signals: the inverse of CE, the inverse of OE and the inverse of WE. When external resetting action is imparted to the memory during the mode operation, a user knows whether the inside of the memory is in a 'Ready' state or a 'Busy' state by means of a status polling signal. Consequently, the generation of malfunction and the useless prolongation of the waiting time are prevented as much as possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device which can be electrically erased, written, and read by a command method.

[0002]

2. Description of the Related Art Generally, a flash E ² P capable of rewriting electrical data is used.
In a ROM (hereinafter, also simply referred to as a storage device), a command system in which each mode such as data writing and erasing is switched by a command (a combination of data) is predominant. For example, a bar C is used as a control signal.
In the storage device in which the mode is switched by the logic of three signals of E, bar OE, and bar WE, bar CE,
When the bar OE and the bar WE are "L", "H", and "L", respectively, the command writing mode, "L", "L", and "H"
In this case, it is distinguished from the read mode. That is, bar C
When E is "L", the storage device is activated, and the bar O
The command writing mode and the reading mode are switched depending on the values of E and WE. FIG. 15 shows an automatic erase command mode for erasing all bits of data in such a storage device.
It will be described with reference to FIGS. The automatic erasing command consists of pre-programming in which all bits are written in advance and erasing operation after pre-programming. The automatic erasing command automatically determines whether the program is OK during pre-programming and whether erasing is OK during erasing. This is what you do.

The internal operation of the storage device at the time of automatic erasing is shown in the flowchart of FIG. First, initialization is performed (see step F171), and "0" is set in the first memory cell.
Data is written (see step F172). Then, a recovery state in which a high voltage is discharged and a verify state in which data is correctly written are verified (see step F173). Then, the written data is read and compared with the reference data (see step F174),
If not correctly written, steps F172, F173, and F174 are repeated until correctly written (see steps F176 and 177). At this time, if the number of repetitions exceeds 25 times, for example, this storage device is determined to be defective.

On the other hand, if the data has been correctly written, 1 is added to the address of the memory cell in which the current data is written (see step F175), and the process returns to step F172 and the next memory corresponding to the address to which 1 is added. Data “0” is written in the cell, and then steps F173 and F1 are performed.
By repeating 74, data "0" is written in all the memory cells. When data is written in all the memory cells, batch erase is performed (see step F180). Then, the recovery state and the baifai state are set (step F1
81), read the data from each memory cell, compare it with the reference data, and verify whether or not complete erasure has been performed (see step F182), and if not erased properly, perform steps F180, F1 until completely erased.
81 and F182 are repeated (steps F183 and F18
4). However, this repeating operation is stopped, for example, when the number of repetitions exceeds 3000 times, and this storage device is determined to be defective.

FIG. 15 shows a timing chart of a normal operation in such an automatic erase command mode, and FIG. 16 shows a timing chart when a reset command for forcibly stopping the operating mode is input. Figure 15
In the above, the command data "30" is input twice at the rising edge of the bars CE and WE, whereby the automatic erase mode is set. The command data is expressed in hexadecimal because the input data is 8 bits. When the automatic erasing mode is set, the automatic erasing is performed within the time set by the built-in timer. The state at this time is notified to the outside by using the least significant data bit D7 as a status polling signal. During erase operation (Bu
The status polling signal is "0" in the sy state, and becomes "1" when the erase operation is completed (Ready state). Then, in FIG. 15, bar CE and bar WE
At the rising edge of, the command data "10" represented by a hexadecimal number is input, and the automatic program mode is entered.

On the other hand, in FIG. 16, the same procedure as in FIG. 15 is performed until the automatic erase mode is entered, but the reset command "FF" is issued twice when the bars CE and WE rise during the automatic erase mode. When input, the automatic erase mode is forcibly stopped and the reset state is entered. Conventionally, the input of the reset command is performed in one step or two steps, but in FIG. 16, it is performed in two steps.

As described above, in the automatic erasing mode using the command system, it is possible to know by the status polling signal whether the operation is being performed or the operation is completed in the normal operation. However, if a reset is forcibly applied from the outside during operation, the automatic erase operation is immediately stopped and the next command is accepted. On the user side, there is no particular restriction on the timing of resetting, and in some cases, it may be desirable to immediately proceed to the next operation.

When the reset is applied during the program operation or the erase operation, that is, when the memory cell and the peripheral circuits are reset with a high potential applied, the correct voltage is immediately obtained when the next operation mode is entered. It cannot be set, which causes malfunction. For example, if the read mode is set before the word line is set from the high potential to V _cc (power supply potential) by resetting during programming, correct cell data cannot be read. In order to perform the correct operation after the reset, it must be performed after the internal is normally reset.
10 μs) had to wait.

Further, in the conventional memory device, it is necessary to specify an address when writing data or erasing in block units, and as shown in FIG. 19, the fall of the signal bar WE for controlling command input (or Set at the rising edge timing. The address latch at the time of command input can be realized by a device that takes in an address at the timing of the falling edge of the signal bar WE in the command input mode and maintains the address latch state during the write operation and the erase operation. This device is configured by including a CE buffer 61, a WE buffer 62, a V _pp detection circuit 63, an address latch pulse generation circuit 66, and an address buffer 67 as shown in FIG. The CE buffer 61 outputs the signal CES1B which activates the WE buffer 62 and the address buffer 67 in synchronization with the signal bar CE based on the signal bar CE. WE buffer 62
Outputs a signal WES1B for controlling the generation of the address latch pulse based on the signal bars WE and CES1B. As shown in FIG. 21, the signal WES1B is a signal which falls when the WE buffer 62 is activated, falls after a predetermined time delay from the fall of the signal bar WE, and rises in synchronization with the rise of the signal bar WE. The V _pp detection circuit 63 detects whether or not the voltage V _pp of the erasing power supply has reached a voltage value sufficient for performing the erasing operation. For example, when the voltage V _pp reaches a sufficient voltage value (V _pp = 12V). Is “0”, and when it has not reached (V _pp = V _cc )
The signal SVPPB that becomes "1" is output. The address latch pulse generation circuit 66 is a circuit which outputs the address latch pulse AL synchronized with the fall of the signal WES1B and its inversion pulse ALB when the signal SVPPB is "0", and is, for example, as shown in FIG. Composed. The address buffer 67 passes the address A _i only when the signal ALB is “1”, and when the signal ALB is “0”, always holds the address latched at the falling edge of the signal WES1B and sends it as a signal AiS to a decoder (not shown). 20B, for example, and is configured as shown in FIG. The timing of each signal described above is shown in FIG.
Shown in 1.

[0010] Thus 2 supply V _pp, in the conventional memory device using the V _cc, the write, erase, is performed by setting the V _pp to a high voltage (= 12V) is a command input mode, the V _pp V High voltage (= 12) from _cc (= 5V) or 0V
ALB becomes "L" when raised to V), the address latch state (address at the time of the V _pp = 12V from being latched) (see FIG. 22).

Therefore, there has been a problem that, after setting V _pp = 12V, normal random reading can be performed only after the address state is released.

Also, three control signal bars CE, OE,
FIG. 23 shows a timing chart of a series of control signals from a command write mode in a program operation to a status read for reading a status signal indicating the status of the storage device in a conventional storage device that switches modes using the bar WE. Shown in. The program operation in FIG. 23 is performed in two steps, the program command is input in the first step, and the address and data to be programmed are input in the second step. In the command writing mode, the address is fetched and latched at the falling edge of the bar CE or the bar WE, and the data is fetched and latched at the rising edge of the bar CE or the bar WE. When reading the status signal, the address and data latched in the previous command write mode are held as they are.
Thus, in the command writing mode, the bar WE is "L" and the bar OE is "H", and in the read mode, the bar WE is "H" and the bar OE is "L".

However, a storage device which is controlled only by the control signal bars CE and OE has been proposed for compatibility with EPROMs. In such a memory device, the active state and the standby state are switched by the signal bar CE, and the command write mode and the read mode are distinguished from each other while the signal bar OE is in the “H” state while the signal bar CE has a negative pulse. Or the signal bar CE and the bar OE become "L" and "L" respectively. FIG. 24 shows the timing of a series of control signals from the command write mode of the program operation to the status read in such a storage device. In FIG. 24, the movements of the signal bars CE and OE are the same as those shown in FIG. However, since there is no signal bar WE, the signal bar OE is “H” at the fall of the signal bar CE in both the command write mode and the status mode, and the current operation is the command write mode only at the fall of the signal bar CE. Or read mode (status read)
I can't make a decision. That is, in the command write mode, the address must be fetched at the falling edge of the signal bar CE, whereas in the read mode, the address must not be fetched and the address non-latch state must be continued. There is a problem that the judgment cannot be made only at the falling edge of.

The present invention has been made in consideration of the above circumstances. A first object of the present invention is that a malfunction may occur even if a reset is applied by a command input during programming or erasing. Another object of the present invention is to provide a non-volatile semiconductor memory device that prevents the above-mentioned problem and does not wastefully lengthen the standby time.

A second object of the present invention is to provide a nonvolatile semiconductor memory device in which normal random reading is possible before a command is input even after the voltage V _pp of the erasing power supply is set to a high voltage (= 12V). To provide.

The third purpose is to provide two control signal bars C
An object of the present invention is to provide a non-volatile semiconductor memory device that does not malfunction even if mode switching is performed using E and bar OE.

[0017]

A nonvolatile semiconductor memory device according to a first aspect of the present invention comprises a reset means for confirming a reset command and performing an internal reset operation during a program operation or an erase operation by a command method. And a polling means for outputting a status polling signal based on the output of the reset means and notifying the outside whether the internal reset operation is completed or the reset operation is completed.

In the nonvolatile semiconductor memory device according to the second aspect of the present invention, the voltage of the power supply is detected based on the voltage detection means for detecting whether or not the data rewriting power supply exceeds a predetermined value, and the detection output of the voltage detection means. Based on the pulse signal generating means that outputs a pulse signal only at the rising edge of, and the detection output of the voltage detecting means and the output of the pulse generating means, the latch command signal that normally latches the address is output and the pulse signal is received. Only when the next command is received, the address latch signal generation means that outputs the latch release command signal that releases the latch of the address and the address is latched based on the latch command signal and the address is released based on the latch release command signal. And an address buffer for releasing the latch of (1) are provided.

In the nonvolatile semiconductor memory device according to the third aspect of the invention, the mode recognition means for recognizing the command write mode or the read mode based on the timing of the two control signals, and the address recognition based on the output of the mode recognition means. A latch command signal generating means for generating a command signal for instructing whether or not to latch, and an address buffer for latching an address based on the output of the latch command signal generating means and for holding or transferring the latched address. It is characterized by being

[0020]

According to the nonvolatile semiconductor memory device of the first invention (hereinafter, also referred to as a memory device) configured as described above,
Whether the internal reset operation is completed or the reset operation is completed can be known by the output of the polling means, and it is possible to prevent malfunctions as much as possible and prevent wasteful extension of the standby time.

According to the memory device of the second aspect of the invention configured as described above, the pulse signal is output from the pulse signal generating means only when the voltage of the data rewriting power source rises. As a result, the address latch release command signal is generated from the address latch signal generating means, the address latch is released in the address buffer, and normal random read is possible even after setting the voltage to a high voltage.

According to the memory device of the third aspect of the invention configured as described above, the mode recognition means recognizes whether the current mode is the command write mode or the read mode. In response to this mode recognition, a command signal is output from the latch command signal generating means, the address is held in the read mode, and the address is transferred to the decoder in the command write mode. This gives 2
Even if the mode is switched by one control signal, it is possible to prevent malfunction as much as possible.

[0023]

FIG. 1 shows the configuration of an embodiment of a nonvolatile semiconductor memory device (hereinafter, also referred to as a memory device) according to the first invention. The memory device of this embodiment includes a control circuit 1, an I / O buffer 2, a command register circuit 3, an auto mode control circuit 4, a write / erase control circuit 5, an erase circuit 6, a row decoder 7, It includes a sense amplifier 8, a column gate 9, and a memory cell array 10. The control circuit 1 controls the I / O buffer 2 and the command register circuit 3 based on the control signals CE, OE and WE.

The command register circuit 3 is a circuit for recognizing a command input via the I / O buffer and switching modes such as writing and erasing. As shown in FIG. 2, the program command register 3a and the erasing command are used. It has a command register 3b and a reset command register 3c. The auto mode control circuit 4 is a circuit for controlling the operation of each auto mode switched by the command register circuit 3, and includes an auto program start circuit 4a and a logic circuit 4b including a NAND gate and an inverter as shown in FIG. , A program timer 4c,
A program verify timer 4d, an auto comparator 4e, an auto erase start circuit 4f, a logic circuit 4g including a NAND gate and an inverter, an erase timer 4h, an erase verify timer 4i, and a polling circuit 4j are provided. The write / erase control circuit 5 uses the voltage V applied to the memory cell array 10 during writing and erasing.
A circuit for setting _pp, which includes a program control circuit 5a, a verify control circuit 5b, a booster circuit 5c, an erase control circuit 5d, and a data latch circuit 5e as shown in FIG.
And have.

The erasing circuit 6 is a circuit for generating a high voltage V _pp during erasing. The row decoder 7 selects the memory cell corresponding to the row address, and the column gate 9 selects the memory cell corresponding to the column address. The sense amplifier 8 reads out the data stored in the memory cell selected by the row decoder 7 and the column gate 9.

The program command register 3a stores the auto program command data "1" when writing a command.
When "0" is set, the output signal APRO is set to "1" by recognizing the automatic program mode, and the output signal APRO is set to "0" at the end of the program or when the reset command is input.
Is sent to the automatic program start circuit 4a and the polling circuit 4j.

The erase command register 3b recognizes the automatic erase commands "30" and "30" and outputs the output signal AER.
S is set to "1", and the output signal AERS is set to "0" at the end of erasing or when the reset command is input and sent to the auto program start circuit 4a and the polling circuit 4j.

The reset command register 3c recognizes the reset commands "FF" and "FF", generates the pulse signal FF1P when the command "FF" in the first step is input, and inputs the command "FF" in the second step. Then, the signal FFRT which generates the pulse signal FF2P and sends it to the polling circuit 4j is set to "1" between the first step and the second step, and is set to "0" in the other periods.

The automatic program start circuit 4a is a circuit for outputting a pulse signal PPUS at the start of the program, and specifically, the output signal AP of the command register 3a.
When RO is "1" (during auto program), when the output signal AERS of the command register 3b is "1" (during auto erase), or when the program operation during auto operation restarts (output pulse of the auto comparator 4e) The pulse signal PPUS is generated when the signal APV is received.

The logic circuit 4b delays the signal PROG (the signal which is the output signal of the program control circuit 5a and which is "1" at the time of writing and "0" otherwise).
ROGD and the output signal FF1P of the command register 3c
The logical product of the
Send to.

The program timer 4c outputs a pulse signal TPRG after a predetermined time (for example, 10 μs) has elapsed after receiving the signal PPUS. Program verify timer 4
After programming, d operates by the signal TPRG and outputs the pulse signal TPR after the verify setting time (for example, 6 μs).

The auto-comparator 4e determines whether or not writing to the memory cell can be correctly performed at the time of program verify of the automatic operation, and determines whether or not the memory cell can be properly erased at the time of erase verify. The determination is made when the signal TPR is "1" during the program verify, and the determination is made when the output signal TER of the erase verify timer 4i is "1" during the erase verify. When performing programming as the next operation, the pulse signal APV sent to the program start circuit 4a is set to "1" to drive the program start circuit 4a, and when erasing is performed, the pulse signal AEV sent to the erase start circuit 4f is set. "1"
Then, the erase start circuit 4f is driven. When the program operation in the program mode ends, the pulse signal EN
The command register 3a is reset using DP, and in the erase mode, a pulse signal EN is generated at the end of preprogramming.
The DP is used to drive the erase start circuit 4f, and the pulse register ENDE is used to reset the command register 3b at the end of the erase operation.

The automatic erasing start circuit 4f is a circuit which outputs a pulse signal EPUS at the start of erasing, and receives the output signal AEV of the automatic comparator 4e during the automatic operation to generate the pulse signal EPUS.

The logic circuit 4g delays the signal ERAS (the output signal of the erase control circuit 5d, which is "1" during the erase operation, and "0" otherwise).
The logical product of SD and the output signal FF1P of the command register 3c is calculated, and the logical product is sent to the erase timer 4h.

The erasing timer 4h outputs the pulse signal TERS a predetermined time (for example, 10 ms) after receiving the pulse signal EPUS.

After erasing, the erase verify timer 4i outputs a pulse signal TER a predetermined time (6 μs) after receiving the signal TERS.

The polling circuit 4j is a signal for setting the status polling signal to the "Busy" state during the automatic operation or the recovery operation at the time of resetting, that is, for setting the output of the input / output pin D7 of the I / O buffer 2 to "0". POL is set to "0" and the status polling signal is set to "Rea" after completion of the auto operation or after completion of the recovery operation at the time of reset.
The dy "state, that is, the output of the input / output pin D7 is set to" 1 "and output to the I / O buffer 2.

When the program control circuit 5a is programmed,
A boosted potential (for example, word voltage V _WL = 12 V, bit line voltage V _BL = 6) is applied to the word line and bit line of the write cell.
The booster circuit 5c is controlled so as to give V).

The verify control circuit 5b uses the word line voltage V _WL during program verify in order to improve the write and erase margins of the word line voltage during verify.
Is set to 7 V, and V _WL is set to 3.5 V during erase verify. The booster circuit 5c is used to boost the potential of the word line and the bit line during programming.

The erase control circuit 5d controls the erase circuit 6 so as to apply a boosted potential (for example, source voltage V _s = 12V) to the source of the memory cell during erase.

The data latch circuit 5e is a circuit for latching write data during auto programming. At the time of verifying the auto program, the output of the sense amplifier 8 and the data latched by the latch circuit 5e are compared by the auto comparator 4e to determine whether or not the data is correctly written. During auto-erasing, all bits “0” (write state) are used as expected values during pre-program operation, and program verification is performed by the auto-comparator 4e. During erase operation, all bits “1” (erase state) are used as expected values. Erase verification is performed by the auto comparator 4e. Then, these expected values are also set by the data latch circuit 5e.

Next, the operation of this embodiment will be described with reference to FIGS. FIG. 3 is a timing chart of the operation in the normal automatic erase mode. In FIG. 3, the automatic erase commands “30” and “30” are the I / O buffer 2
When input via the
b recognizes and sets the output signal AERS to "1". Then, the pulse signal PP is output from the automatic program start circuit 4a.
US is output, whereby the output signal PROG of the program control circuit 5a becomes "1", the booster circuit 5c is driven, and writing of data "0" to one memory cell is started. That is, step F172 of FIG. 17 is executed.

At this time, the output signal POL of the polling circuit 4j also becomes "0", and this value is output to the outside through the input / output pin D7 of the I / O buffer 2, and the inside of the storage device becomes "Busy". "Inform the outside of the status.

When a predetermined time elapses after the pulse signal PPUS is generated, the pulse signal T is output from the program timer 4c.
PRG is output, which causes the program control circuit 5a.
Output signal PROG becomes "0" and the output signal PREC of the verify control circuit 5b becomes "1".
Step F173 of No. 7 is executed. Also, the pulse signal E
When a predetermined time has elapsed after the automatic erase start pulse signal TPRG was generated after a predetermined time has elapsed since the NDP was generated, the program verify timer 4d generates the pulse signal TPR, and program verify is performed to determine whether the program is correctly performed. Run. That is, step F174 of FIG. 17 is executed. If it is determined at this verification that the program has been performed correctly and the data 0 has been written, steps F175 and F172 of FIG. 17 for counting up the address and writing the memory cell corresponding to the next address are executed. If it is determined that the data "0" cannot be written correctly, additional writing to the memory cell corresponding to the current address is performed, and steps F176 and F17 in FIG.
7, F172 is executed. By repeating this operation, when the data "0" is written in the memory cells of all addresses, the pulse signal ENDP is generated from the auto comparator 4e, and the program mode is completed. Further, after a predetermined time has elapsed since the pulse signal ENDP was generated, the pulse signal EPUS is generated from the automatic erasing start circuit 4f, which causes the signal E output from the erasing control circuit 5d.
When RAS becomes "1", the erase circuit 6 is driven and the erase mode is set. That is, step F180 shown in FIG. 17 is executed.

When a predetermined time elapses after the pulse signal EPUS is generated, the pulse signal TER is output from the erase timer 4h.
S is issued, which causes the output ER of the erase control circuit 5d.
As AS becomes "0", the output EREC of the verify control circuit 5b becomes "1". That is, step F181 shown in FIG. 17 is executed.

When a predetermined time has elapsed after the pulse signal TER was generated, the erase verify timer 4i generates the pulse signal TER. As a result, the output EREC of the verify control circuit 5b becomes "0" and the erase recovery mode ends. When the pulse signal TER is generated, erase verify is performed to determine whether or not the erase is properly performed. That is, step F18 of FIG.
2 is executed. If erasure is incomplete in this verification, auto erasure start 4 is performed via auto comparator 4e.
The pulse signal EPUS is generated from f and the erasing is performed again. That is, steps F182 and F18 shown in FIG.
3, F184, F180 are executed.

If the erasure is complete, the comparator 4
The pulse signal END is output from e. As a result, the erase command register 3b is stopped and its output signal AER
S becomes "0", the output signal POL of the polling circuit 4j becomes "1", and the erasing is completed.

FIG. 4 shows automatic erasing (during program mode).
6 is a timing chart of the operation when the reset is applied to the. In FIG. 4, one-step command “FF”
It is similar to the case described in FIG. 3 until is input.

First step reset command "FF"
Is input via the I / O buffer 2, the reset command register 3c recognizes this and outputs the pulse signal FF1.
At the same time that P is generated, the signal FFRT sent to the polling circuit 4j is set to "1". When the pulse signal FF1P is issued, the operation of the erase command register 3b is stopped and the automatic erase mode is stopped. That is, the output signal AERS of the erase command register 3b becomes "0". Subsequently, the output PROG of the program control circuit 5a becomes "0" to stop the internal operation (in this case, the write operation), and the recovery start pulse TPRG is generated from the program timer 4c, so that the verify operation of the bay-fi control circuit 5b is stopped. The output signal PREC becomes "1" and the recovery mode is set. After a lapse of a predetermined time from the recovery mode, the program verify timer 4d issues a pulse signal TPR, and the output P of the verify control circuit 5b.
REC becomes “0”. At this time, since the output FFRT of the reset command register 3c is "1", the polling circuit 4j determines that the recovery mode is completed and sets its output POL to "1". That is, I / O buffer 2
The status polling signal output from the I / O pin D7 of "1" becomes "Ready".

When the reset command "FF" of the second step is input, the reset command register 3
c detects this, and internally generates a pulse signal FF2P. As a result, the signal FFRT sent from the reset command register 3c to the polling circuit 4j becomes "0".

When the reset is applied during the automatic erase mode as described above, the memory is stored from the input of the reset command "FF" in the first step to the input of the reset command "FF" in the second step. The user can know whether the internal state of the device is during recovery or completion of recovery as a status polling signal (output of the input / output pin D7 of the I / O buffer 2) as shown in FIG.

As described above, according to this practical example, whether the inside of the storage device is in the "Ready" state or "Busy" when the reset is applied from the outside during the mode operation.
The status polling signal allows the user to know the status. As a result, malfunction can be prevented as much as possible, and unnecessary increase in standby time can be prevented as much as possible.

In the above embodiment, the case of the automatic erase mode has been described as an example. However, when the reset is applied in the middle of modes such as the automatic block erase mode and the automatic program mode (write mode in byte unit). Similarly, the reset command of the first step and 2
During the reset command of the step, it is possible to output a status polling signal indicating whether recovery is in progress or completed.

Next, FIG. 6 shows the configuration of an embodiment of a nonvolatile semiconductor memory device (hereinafter, also referred to as a memory device) according to the second invention. The memory device of the embodiment is the same as the conventional device shown in FIG. 18, _except that a V _pp pulse generation circuit 64 is newly provided and an address latch pulse generation circuit 65 is provided instead of the address latch pulse generation circuit 66.

The V _pp pulse generation circuit 64 is, for example, as shown in FIG.
As shown in (b), the voltage V _{pp of the} erase power supply is set to the drive voltage V based on the output SVPPB of the V _pp detection circuit 63.
_{From cc} (eg 5V) or 0V to a predetermined high voltage (eg 1
When it rises to 0 V or more), it outputs a single pulse signal RSTAL.

The address latch pulse generation circuit 65 is constructed, for example, as shown in FIG. 7A, operates based on the output SVPPB of the V _pp detection circuit 63 and the output RSTAL of the V _pp pulse generation circuit 64, and outputs the voltage. When V _pp is V _cc or less, that is, when SVPPB is “1”, the address latch is released (AL is “0” and ALB is “1”), and when the voltage V _pp is high voltage, that is, SVPPB is “1”. In the case of 0 ”, the single pulse signal RSTAL is output from the V _pp pulse generation circuit 64, so that two NOR gates N
Output 72 of flip-flop composed of OR1 and NOR2
Becomes "1" and the address latch release state (AL is "0", ALB is "1") is maintained. After that, when the pulse of the signal bar WE is input in the command input mode, the level of the node 71, which is the reset input of the flip-flop, becomes "1", the flip-flop is released, and the level of the node 72 becomes "0". That is, the address latch state is set.

A timing chart of the above signals is shown in FIG. When the voltage V _pp to the high voltage level of the node 72 signal SVPPB becomes "0""0" to "1"
And the level of the signal AL is maintained at "0".

The address latch state is carried out at the rising edge of the first pulse of the signal bar WE, and at the falling edge of the signal bar WE from the second stage. Currently, in a flash E ² PROM that performs writing and erasing using the command method, latching is performed at the falling edge of the second pulse of the signal bar WE, and correct address latching can be performed when rewriting data.

The V _pp pulse generating circuit may have a structure as shown in FIG. In this case, a single pulse RSTAL is output when V _pp rises from 0 V to a predetermined high potential.

As described above, according to the present embodiment, even after the voltage V _pp is set to a high voltage, normal random reading can be performed before command input.

Next, FIG. 9 shows the configuration of an embodiment of the nonvolatile semiconductor memory device according to the third invention. The memory device of this embodiment has a CE buffer 91, an OE buffer 92, a read mode recognition circuit 93, an address latch pulse generation circuit 94, and an address buffer 95, and keeps the timing of signal CE and bar OE. Read mode recognition circuit 9
In 3, the command write mode or the read mode is determined, and feedback is given to the address latch pulse generation circuit to determine whether or not address latch is performed.

A specific example of the read mode recognition circuit 93 of this practical example is shown in FIG. 10, a specific example of the address latch pulse generation circuit 94 is shown in FIG. 11, a specific example of the address buffer 95 is shown in FIG. The operation of is shown in the timing chart of FIG. 2 pulses to latch the address
Signal ALS1B and ALS2B
1B becomes a pulse at the falling edge of the bar CE, and the signal ALS2B becomes a pulse at the rising edge of the bar CE. Further, the read mode recognition circuit 93 determines whether the command write mode is the read mode. In the command write mode, the output signal CR of the recognition circuit remains "L" and in the read mode it becomes "H". The address buffer 95 has a two-stage latch circuit, and the first-stage latch circuit receives the signal ALS1B.
The second-stage latch circuit operates by the signal ALS2B and latches the address.

As shown in FIG. 13, when the command write mode or the read mode cannot be determined only by the fall of the signal CE, the signal ALS at the fall of the signal CE.
1B becomes a pulse, and the latch operation of the first stage of the address buffer is performed. After that, if the bar OE is “H” until the signal bar CE rises, it is judged as the command writing mode, the signal ALS2B becomes a pulse at the rising edge of the bar CE, and the address at the falling edge of the signal bar CE is transferred to the decoder (not shown). To do. If the bar OE becomes "0" before the signal bar CE rises, the read mode is determined, the signal ALS2B does not become a pulse, and the address is maintained as it is.

A concrete example of the address latch pulse generating circuit in the case of limiting the output signal RSTAL of the V _pp pulse generating circuit so that the address latch is released even when the voltage V _pp is set to a high voltage is shown in FIG. Show.

As described above, no malfunction occurs even if mode switching is performed using only the two control signal bars CE and OE.

[0066]

According to the first aspect of the present invention, it is possible to prevent malfunctions as much as possible even if a reset is applied by a command input during programming or erasing, and to reduce the waiting time. It is possible to prevent unnecessary lengthening.

According to the second aspect of the invention, even after setting the voltage V _pp to a high voltage, normal random reading can be performed before command input.

Further, according to the third invention, it is possible to prevent malfunction even if the mode is switched by using the two control signal bars CE and OE.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the first invention.

FIG. 2 is a block diagram showing details of main components of the embodiment shown in FIG.

FIG. 3 is a timing chart explaining the operation of the embodiment shown in FIG.

FIG. 4 is a timing chart explaining the operation of the embodiment shown in FIG.

5 is a timing chart for explaining the effect of the embodiment shown in FIG.

FIG. 6 is a block diagram showing the configuration of an embodiment of the second invention.

7 is a circuit diagram showing a specific example of a V _pp pulse generation circuit and an address latch pulse generation circuit according to the embodiment shown in FIG.

FIG. 8 is a timing chart explaining the operation of the embodiment shown in FIG.

FIG. 9 is a block diagram showing the configuration of an embodiment of the third invention.

10 is a circuit diagram showing a specific example of a read mode recognition circuit according to the embodiment shown in FIG.

FIG. 11 is a circuit diagram showing a specific example of an address latch pulse generation circuit according to the embodiment shown in FIG.

FIG. 12 is a circuit diagram showing a specific example of an address buffer according to the embodiment shown in FIG.

FIG. 13 is a timing chart explaining the operation of the embodiment shown in FIG.

FIG. 14 is a circuit diagram showing another specific example of the address latch pulse generation circuit.

FIG. 15 is a timing chart illustrating the operation of a conventional storage device.

FIG. 16 is a timing chart illustrating the operation of a conventional storage device.

FIG. 17 is a flowchart illustrating an all-bit erasing operation of the flash type E ² PROM.

FIG. 18 is a block diagram showing the configuration of another conventional storage device.

19 is a timing chart illustrating the operation of the memory device illustrated in FIG.

20 is a circuit diagram showing details of main components of the memory device shown in FIG.

21 is a timing chart illustrating a problem of the memory device illustrated in FIG.

22 is a timing chart illustrating a problem of the memory device illustrated in FIG.

FIG. 23 is a timing chart illustrating the operation of another conventional storage device.

FIG. 24 is a timing chart explaining the operation of still another conventional storage device.

FIG. 25 is a circuit diagram showing another specific example of the Vpp pulse generating circuit according to the second invention.

[Explanation of symbols]

 1 Control Circuit 2 I / O Buffer 3 Command Register Circuit 4 Auto Mode Control Circuit 5 Write / Erase Control Circuit 6 Erase Circuit 7 Row Decoder 8 Sense Amplifier 9 Column Gate 10 Memory Cell Array

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tadayuki Taura 580-1, Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Toshiba Semiconductor Systems Technology Center, Ltd. (72) Inventor Yukiko Ominino, Kawasaki, Kanagawa 580-1, Horikawa-cho, Tokyo Stock Company Toshiba Semiconductor System Technology Center

Claims (3)

[Claims] 1. A reset means for confirming a reset command and performing an internal reset operation when a program operation or an erase operation is performed by a command system, and a status polling signal is output based on an output of the reset means, A non-volatile semiconductor memory device, comprising: a polling unit that notifies the outside whether the reset operation is completed or the reset operation is completed. 2. A voltage detection means for detecting whether or not the data rewriting power supply exceeds a predetermined value, and a pulse signal for outputting a pulse signal only when the voltage of the power supply rises based on the detection output of the voltage detection means. Based on the generation means and the detection output of the voltage detection means and the output of the pulse generation means, a latch command signal for latching an address is output under normal conditions, and the next command is received only when the pulse signal is received. Up to an address latch signal generating means for outputting a latch release command signal for releasing the address latch, and an address buffer for latching the address based on the latch command signal and releasing the address latch based on the latch release command signal A non-volatile semiconductor memory device comprising: 3. A mode recognition means for recognizing a command write mode or a read mode based on the timing of two control signals, and a command signal for instructing whether or not to latch an address based on the output of the mode recognition means. A non-volatile semiconductor, comprising: a latch command signal generating means for latching an address based on the output of the latch command signal generating means, and an address buffer for holding or transferring the latched address. Storage device.