JPH06332789A - Parallel processor and locking method for shared data - Google Patents

Abstract

PURPOSE:To make it possible to improve whole performance by averaging lock standby time by assigning he authority of a lock in order of large number of times of trial of the lock and preventing the authority of the lock from centralizing in a specified processor. CONSTITUTION:This device is the one accessing to the data of a shared memory from plural processors provided with lock instructions and unlock instructions. A shared memory is provided with an access holding part 20b holding the pair of an address information storage part 20b-1 for storing address information showing the address of data, an access counter 20b-2 for counting the number of time of trial of the lock for the data shown by address information corresponding to address information every processor and a lock flag part 20b-3 storing lock flags showing whether the data corresponding to address information is locked or not. By using these, the authority of the lock is assigned in order of large number of times of trial of the lock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared data locking system for a shared memory shared by a plurality of processors.

[0002]

2. Description of the Related Art In recent years, in order to realize a computer having a higher processing capacity, a parallel processing apparatus for processing in parallel by a plurality of processors has been developed.
In such a parallel processing device, it is necessary to exchange data between processors, and there is a shared memory as one method for realizing this.

The shared memory is capable of reading and writing data by designating an address from a processor like a normal memory, but in order to maintain consistency when data is updated by a plurality of processors, At the same time, it becomes necessary to lock the update operation.

One of the conventional locking methods is a special instruction that enables a processor to read or write an address in a shared memory without interference from other processors. There is a method to prepare in the processor.

This special instruction method gives the lock right to the processor that has accessed first.
Therefore, when updating is frequently performed, if the timing is wrong, the right to lock a specific processor may not be granted. Hereinafter, a specific example will be described with reference to FIG.

FIG. 4 (a) is a flow chart showing the flow of processing of the program shown in FIG. 4 (b). Figure 4
Each instruction (instructions I1 to I8) of the program shown in (b)
Can be processed in one cycle each.

In this case, as shown in FIG. 4, whether the lock succeeds or fails in the instruction I1, the label L
It takes 5 cycles to return to OOP. In such a situation, it is assumed that the processor Q executes this program one cycle later than the processor P. The timing of the execution instruction of each processor (P, Q) at this time is shown in FIG.

In this example, processor P has instructions I1 ...
I5 will be repeated, and the address M will be locked between T1 and T4. Therefore, when the processor Q tries to lock (instruction I1), the processor P always locks, and the processor Q cannot lock.

[0009]

As described above, the conventional method has a problem that, in the worst case, a particular processor cannot lock. The present invention has been made in consideration of the above-mentioned circumstances. The lock waiting time is averaged by allocating the locks in descending order of the number of trials so that lock authority is not concentrated on a specific processor. An object of the present invention is to provide a parallel processing device and a shared data locking method capable of improving the overall performance.

[0010]

According to the present invention, data in a shared memory is accessed from a plurality of processors having a lock instruction and an unlock instruction for data, and the shared memory is an address of stored data. Address information storage means for storing the address information indicating the address, and a counter for counting the number of lock attempts for the data indicated by the address information corresponding to the address information stored in the address information storage means for each processor. , And access holding means for holding a set of lock flag means for storing a lock flag indicating whether or not the data corresponding to the address information stored in the address information storage means is locked. hand,
When the specified address in the shared memory is not held in the access holding means, the same address is held in the address information storage means, the count value of each processor of the counter is initialized, and the lock flag means is held. When the lock flag is set, the processor is notified that the lock is successful, and when the specified address in the shared memory is held in the access holding means, the lock flag means is notified to the lock instruction. If the lock flag is not set and the count value corresponding to the processor of the counter is the maximum, the lock flag is set to the lock flag means and the processor is notified that the lock is successful. In the case of, the count value of the processor is increased and Reports that the lock has failed to,
In response to the unlock instruction, the count value of the processor of the counter corresponding to the designated address is initialized.

[0011]

According to this structure, the processor executes the lock instruction to try to lock the data to be updated. At this time, the address is not locked by another processor, and the lock is tried. The lock succeeds if the number of attempts made by the processor is maximum. If the lock is unsuccessful, the trial is repeated and the number of trials of the processor increases. As a result, those who try to lock earlier can preferentially lock. On the other hand, once the lock is successful, the number of trials is initialized, so that the next lock request has a low priority. As a result, the lock requests are frequently allocated in order.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the main configuration of a computer according to an embodiment of the present invention. As shown in FIG. 1, the computer in this embodiment is configured by connecting a plurality of processors 10-1, 10-2, ..., 10-N and a shared memory 20 via a bus 30.

Processors 10-1, 10-2, ..., 10
The lock command and unlock command from -N are sent to the shared memory 20 via the bus 30. As shown in FIG. 2, the shared memory 20 is provided with a data section 20a for storing data and an access holding section 20b.

Further, the access holding unit 20b includes an address information storage unit 20b-1 and an access counter 20b-.
2, a lock flag portion 20b-3 is provided. The address information storage unit 20b-1 is for storing address information indicating the address of the data stored in the data unit 20a. The access counter 20b-2 is for counting the number of lock attempts for the data indicated by the address information for each processor, corresponding to the address information stored in the address information storage unit 20b-1. The lock flag portion 20b-3 indicates whether or not the data corresponding to the address information stored in the address information storage portion 20b-1 is locked. A set of address information, counter value, and lock flag is called an entry.

Next, the operation of this embodiment will be described.
Here, the processors 10-1, 10-2, ..., 10-
A description will be given by taking as an example a process in which an arbitrary processor P and a processor Q in N operate data at the same address M1.
For simplification of explanation, it is assumed that the program shown in FIG. 4 used in the description of the conventional technique is used, and the operation on the address M1 is not performed by a program other than the program explicitly shown in FIG.

The program shown in FIG. 4 is the program used in the description of the prior art. Even when the lock is successful,
Also, in the case of failure, the processing requires 5 cycles each. A situation in which the processor P executes one cycle earlier than the processor Q will be described for each clock (T1 to T10) with reference to the timing chart shown in FIG.

(T1) Processor P is read with loc
The k instruction (lock instruction I1) tries to apply a read lock to the data at the address M1 on the shared memory 20. Here, since there is no entry for the address M1 in the access holding unit 20b, a new entry is secured and the address information M1 is stored in the address information storage unit 2.
Store in 0b-1. Further, the access counter 20b-2 for each processor is initialized in the entry of the address M1, and a lock flag is set in the lock flag unit 20b-3 (“1”). The shared memory 20 notifies the value of the address M1 and the success of the lock.

(T2) The processor P checks whether the lock has failed (instruction I2), and as a result of this, it does not jump because it succeeds. On the other hand, the processor Q uses read with lock
The instruction (lock instruction I1) attempts to lock the read of the data at the address M1 on the shared memory 20. Here, since the lock flag of the entry of the address M1 has already been set, the shared memory 20 increases the counter value of the access counter 20b-2 for the processor Q, and notifies the processor Q that the lock has failed.

(T3) The processor P executes a process of adding 1 to the read value (instruction I3). on the other hand,
Processor Q checks if the lock failed (instruction I
2). As a result, it is determined that the lock has failed, and the process jumps to the label FAIL.

(T4) The processor P calculates the calculation result by wri.
Attempt to release the write lock by the te with unlock instruction (unlock instruction I4). The shared memory 20 is
Access counter 2 of entry corresponding to address M1
The counter value for the processor P of 0b-2 is initialized, and the lock flag is cleared (“0”). On the other hand, the processor Q executes the inst1 instruction (instruction I6).

(T5) The processor P unconditionally jumps to the label LOOP (instruction I5). On the other hand, the processor Q
The inst2 instruction (instruction I7) is executed. (T6) The processor P uses the read with lock instruction (lock instruction I1) to address M on the shared memory 20.
Attempts to lock the data of No. 1 by reading it. In the shared memory 20, the lock flag is not set for the entry of the address M1, but the count value of the entry corresponding to each processor of the access counter 20b-2 is compared, and the counter value of the entry of the processor P is not the maximum.
The counter value of the processor P is incremented, and the processor P is notified of the lock failure. On the other hand, the processor Q unconditionally jumps to the label LOOP (command I
8).

(T7) The processor P determines whether the lock has failed as a result of checking whether the lock has failed, and therefore jumps to the label FAIL (instruction I2). On the other hand, processor Q
Attempts to lock the data at the address M1 on the shared memory 20 by the read with lock instruction (lock instruction I1). Since the lock flag is not set in the entry of the address M1 and the counter of the processor Q is maximum, the shared memory 20 sets the lock flag,
Notify the value of the address M1 and the success of the lock to the processor Q.

(T8) The processor P executes the inst1 instruction (instruction I6). Processor Q checks if the lock failed and does not jump because it succeeded (instruction I
2). (T9) The processor P executes the inst2 instruction (instruction I8). The processor Q performs a process of adding 1 to the read value (instruction I3).

(T10) The processor P unconditionally jumps to the label LOOP (instruction I8). The processor Q writes the calculation result in a write with unlock instruction (unlock instruction I4)
Try to release the write lock by. The shared memory 20 initializes the counter value of the processor Q of the entry of the address M1 and lowers the lock flag.

In this way, when the processor executes the lock instruction to attempt to lock the data to be updated, the address is not locked by another processor, and the number of trials of the processor that has tried to lock the data. If is maximum, the lock succeeds. If the lock is unsuccessful, the trial is repeated and the number of trials of the processor increases. As a result, the person who tried the lock first can preferentially perform the lock.

On the other hand, once the lock is successful, the number of trials is initialized, so that the next lock request has a low priority. As a result, the lock requests are allocated in order from the most frequent one.

Therefore, the lock authority is not concentrated on a specific processor, and there is no possibility that another processor cannot lock. In addition,
For the operation of increasing the counter of each processor of the access holding unit 20b, the number of lock attempts may be held as it is, or a value subjected to priority processing may be held. Accordingly, the maximum judgment of the counter value of each processor is
It should be based on the number of lock attempts.

The entry may be released at any time unless the lock flag is set. Further, as a method of notifying that the lock has failed, the lock code may be reflected in the condition code or may be notified by an interrupt.

[0029]

As described above, according to the present invention, the lock authority is assigned in order from the one having the largest number of lock attempts, so that the lock authority is not concentrated on a specific processor. The time can be averaged, access competition for the shared memory can be relaxed, and the overall performance can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the main configuration of a computer according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a shared memory 20 in this embodiment.

FIG. 3 is a diagram showing the timing of execution instructions of two processors P and Q for explaining the operation of this embodiment.

FIG. 4 is a diagram showing an example of a lock program for explaining the operation.

FIG. 5 is a diagram showing timings of execution instructions of two processors P and Q for explaining a conventional technique.

[Explanation of symbols]

10-1, 10-2, ..., 10-N ... Processor, 20
... shared memory, 20a ... data section, 20b ... access holding section, 20b-1 ... address information storage section, 20b-2 ...
Access counter, 20b-3 ... Lock flag part, 30
…bus.

Claims (2)

[Claims] 1. A parallel processing apparatus for accessing data in a shared memory from a plurality of processors having a lock instruction and an unlock instruction for data, wherein the shared memory stores address information indicating an address of the stored data. Address information storing means, a counter for counting the number of lock attempts for the data indicated by the address information corresponding to the address information stored in the address information storing means for each processor, and the address information storage Access holding means for holding a set of lock flag means for storing a lock flag indicating whether or not the data corresponding to the address information stored in the means is locked; Specified address is not held in the access holding means In the case, holding the same address in the address information storage means,
Initialize the count value of each processor of the counter,
While setting a lock flag in the lock flag means,
Notifying the processor that the lock is successful, and when the specified address in the shared memory is held in the access holding means in response to the lock instruction,
The lock flag is not set in the lock flag means,
If the count value of the counter corresponding to the processor is maximum, the lock flag means is set to the lock flag and the processor is notified that the lock is successful. Otherwise, the count of the processor is counted. In parallel with increasing the value, notifying the processor that locking has failed, and initializing the count value of the processor of the counter corresponding to the specified address to the unlock instruction. Processing equipment. 2. A method of locking shared data in a shared memory, which is accessed by a plurality of processors having a lock instruction and an unlock instruction for data, wherein the shared memory is address information indicating an address of the stored data. Address information storing means for storing the address, a counter for counting, for each processor, the number of lock attempts for the data indicated by the address information corresponding to the address information stored in the address information storing means, and the address An access holding means for holding a set of lock flag means for storing a lock flag indicating whether or not the data corresponding to the address information stored in the information storage means is locked is provided, and the sharing is performed in response to the lock instruction. The specified address in the memory is held in the access holding means. If not, hold the same address in the address information storage means,
Initialize the count value of each processor of the counter,
While setting a lock flag in the lock flag means,
Notifying the processor that the lock is successful, and when the specified address in the shared memory is held in the access holding means in response to the lock instruction,
The lock flag is not set in the lock flag means,
If the count value of the counter corresponding to the processor is maximum, the lock flag means is set to the lock flag and the processor is notified that the lock is successful. Otherwise, the count of the processor is counted. Shared by not only increasing the value but also notifying the processor that locking has failed, and initializing the count value of the processor of the counter corresponding to the specified address for the unlock instruction. How to lock data.