JPH06331679A - Switching circuit fault detecting device - Google Patents

Switching circuit fault detecting device

Info

Publication number
JPH06331679A
JPH06331679A JP5116134A JP11613493A JPH06331679A JP H06331679 A JPH06331679 A JP H06331679A JP 5116134 A JP5116134 A JP 5116134A JP 11613493 A JP11613493 A JP 11613493A JP H06331679 A JPH06331679 A JP H06331679A
Authority
JP
Japan
Prior art keywords
circuit
signal
output
failure detection
switch circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5116134A
Other languages
Japanese (ja)
Inventor
Masayoshi Sakai
坂井  正善
Koichi Yomogihara
弘一 蓬原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Signal Co Ltd
Original Assignee
Nippon Signal Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Signal Co Ltd filed Critical Nippon Signal Co Ltd
Priority to JP5116134A priority Critical patent/JPH06331679A/en
Publication of JPH06331679A publication Critical patent/JPH06331679A/en
Pending legal-status Critical Current

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  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)

Abstract

PURPOSE:To make it easy to detect the fault of a switching circuit which turns a load on and off. CONSTITUTION:A signal-transmitting transformer T1 is inserted in series with a first snubber circuit 6 connected in parallel to a relay contact 4a, so that a fault detection signal generated by a signal generator circuit 8 is transmitted to the first snubber circuit 6. A signal-receiving transformer T2 is inserted in series with a second snubber circuit 7 connected in parallel to an SSR (solid- state relay) 5, so that the fault detection signal transmitted to the first snubber circuit 6 is received by the signal-receiving transformer T2. Therefore, when the relay contact 4a or the SSR 5 is shortcircuited, no fault detection signal is transmitted to the signal-receiving transformer T2 and the output of the signal-receiving transformer T2 becomes a logical value of 0. When a load is off in a normal state, a fault detection signal is transmitted to the signal- receiving transformer T2 and the output becomes a logical value of 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、制御対象である負荷の
駆動電流をON・OFFするスイッチ回路の故障検出を
行うスイッチ回路故障検出装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch circuit failure detection device for detecting a failure of a switch circuit for turning on / off a drive current of a load to be controlled.

【0002】[0002]

【従来の技術】従来、制御対象である負荷の駆動電流を
ON・OFFするスイッチ回路を、電磁リレーの接点と
半導体スイッチ素子、例えばスリッドステートリレー
(SSR)とを直列接続して構成し、電磁リレー接点と
SSRをON・OFF制御して負荷への給電を制御する
ようした負荷駆動回路がある。
2. Description of the Related Art Conventionally, a switch circuit for turning on / off a drive current of a load to be controlled is constructed by connecting contacts of an electromagnetic relay and a semiconductor switch element, for example, a slit state relay (SSR) in series, There is a load drive circuit that controls power supply to a load by controlling ON / OFF of a relay contact and an SSR.

【0003】即ち、前記スイッチ回路は、負荷の駆動入
力信号が入力した時には、まず、電磁リレー接点がON
し、その後にSSRがONして初めて負荷に駆動電流が
流れ、負荷駆動入力信号が停止した時には、逆にSSR
が先にOFFして負荷への給電が停止し、その後電磁リ
レー接点がOFFするように構成されている。かかる構
成によれば、スイッチ回路が正常である時には、実質的
にSSRのON・OFFによって負荷駆動電流のON・
OFFが制御され、電磁リレー接点は駆動電流のON・
OFFには直接関与しないが、SSRが短絡故障を起こ
して負荷駆動電流をOFFできない場合に、電磁リレー
接点をOFFとすることによって負荷駆動電流を強制的
にOFFとすることができる。
That is, in the switch circuit, when the drive input signal of the load is input, first, the electromagnetic relay contact is turned on.
Then, after the SSR is turned on, the drive current flows to the load for the first time, and when the load drive input signal is stopped, the SSR is reversed.
Is turned off first, power supply to the load is stopped, and then the electromagnetic relay contact is turned off. With this configuration, when the switch circuit is normal, the load drive current is turned on / off substantially by turning the SSR on / off.
OFF is controlled, and the electromagnetic relay contacts turn on the drive current.
Although not directly involved in OFF, when the SSR causes a short-circuit fault and the load drive current cannot be turned OFF, the load drive current can be forcibly turned OFF by turning OFF the electromagnetic relay contact.

【0004】ところで、前記SSRの短絡を検出する従
来回路としては、負荷とスイッチ回路とが直列に挿入さ
れた負荷給電回路に、トランスの2次側を直列に介装
し、このトランスの1次側から交流の短絡検出用信号を
前記2次側を介して負荷の給電回路に供給する構成とす
る。この場合、スイッチ回路の電磁リレーとSSRに
は、通常、雑音防止回路(コンデンサと抵抗の直列回路
で構成されるスナバ回路)がそれぞれ並列接続されてお
り、SSR又は電磁リレー接点が短絡故障した場合に
は、トランスの1次側から見た給電回路のインピーダン
スが低下する。従って、このインピーダンスの低下に基
づく出力変化を監視することで、スイッチ回路の短絡を
検出するようにしていた。
By the way, as a conventional circuit for detecting the short circuit of the SSR, a secondary side of a transformer is inserted in series in a load feeding circuit in which a load and a switch circuit are inserted in series, and the primary side of this transformer is inserted. The AC short-circuit detection signal is supplied from the side to the load power supply circuit via the secondary side. In this case, a noise prevention circuit (a snubber circuit composed of a series circuit of a capacitor and a resistor) is usually connected in parallel to the electromagnetic relay and the SSR of the switch circuit, and when the SSR or the electromagnetic relay contact has a short-circuit failure. In addition, the impedance of the power feeding circuit seen from the primary side of the transformer decreases. Therefore, the short circuit of the switch circuit is detected by monitoring the output change based on the decrease in the impedance.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、従来の
短絡故障の検出回路のように、給電回路のインピーダン
ス変化に基づく出力変化を監視して、スイッチ回路の短
絡故障を検出する方式では、出力のレベル変化を検出す
ることになり、閾値設定が面倒である。また、スナバ回
路のコンデンサの短絡故障を考慮しようとすれば、より
一層閾値設定が面倒であり、故障検出の精度の面で十分
ではなかった。
However, as in the conventional short-circuit failure detection circuit, in the method of detecting the short-circuit failure of the switch circuit by monitoring the output change based on the impedance change of the feeding circuit, the output level is reduced. The change is detected, and the threshold setting is troublesome. Further, if a short circuit failure of the capacitor of the snubber circuit is to be taken into consideration, the threshold setting is further troublesome, and the accuracy of failure detection is not sufficient.

【0006】本発明は上記の事情に鑑みなされたもの
で、スイッチ回路の短絡故障の有無を論理値1(出力有
り)と論理値0(出力無し)の2値の出力形態で表すこ
とのできるスイッチ回路の故障検出装置を提供すること
を目的とする。
The present invention has been made in view of the above circumstances, and the presence or absence of a short circuit fault in a switch circuit can be represented by a binary output form of a logical value 1 (with output) and a logical value 0 (without output). An object is to provide a failure detection device for a switch circuit.

【0007】[0007]

【課題を解決するための手段】このため本発明では、電
磁リレー接点と半導体スイッチ素子の直列回路で構成さ
れ、負荷駆動信号が入力した時に前記電磁リレー接点と
半導体スイッチ素子がONして負荷に給電し、負荷駆動
信号の入力が停止した時に前記電磁リレー接点と半導体
スイッチ素子がOFFして負荷への給電を停止する構成
のスイッチ回路の故障を検出するスイッチ回路故障検出
装置において、抵抗とコンデンサの直列回路からなり前
記電磁リレー接点に対して並列に接続される第1の雑音
防止回路と、同じく抵抗とコンデンサの直列回路からな
り前記半導体スイッチング素子に対して並列に接続され
る第2の雑音防止回路と、スイッチ回路故障検出用信号
を発生する信号発生回路と、どちらか一方の雑音防止回
路に直列に挿入されて前記スイッチ回路故障検出用信号
を当該雑音防止回路側に伝達する信号送信トランスと、
他方の雑音防止回路に直列に挿入されて前記スイッチ回
路故障検出用信号を受信して抽出する信号受信トランス
とを備えて構成し、電磁リレー接点及び半導体スイッチ
素子の少なくとも一方が短絡した時に信号受信トランス
の抽出出力が論理値0となるようにした。
Therefore, according to the present invention, a series circuit of an electromagnetic relay contact and a semiconductor switch element is provided, and when the load drive signal is input, the electromagnetic relay contact and the semiconductor switch element are turned on to apply a load. A resistor and a capacitor in a switch circuit failure detection device for detecting a failure in a switch circuit configured to stop power supply to a load by supplying power and stopping input of a load drive signal when the electromagnetic relay contact and a semiconductor switch element are turned off. A first noise prevention circuit formed of a series circuit of the above and connected in parallel to the electromagnetic relay contact, and a second noise circuit formed of a series circuit of a resistor and a capacitor, connected in parallel to the semiconductor switching element. The noise prevention circuit, the signal generation circuit that generates the switch circuit failure detection signal, and either of the noise prevention circuits are inserted in series. A signal transmission transformer for transmitting to the radio interference suppression circuit side the switch circuit failure detection signal Te,
A signal receiving transformer that is inserted in series with the other noise prevention circuit and receives and extracts the switch circuit failure detection signal, and receives a signal when at least one of the electromagnetic relay contact and the semiconductor switch element is short-circuited. The extracted output of the transformer has a logical value of 0.

【0008】また、前記信号受信トランスの抽出出力を
整流する整流回路と、該整流回路の整流出力を入力して
当該整流出力レベルが所定範囲内にある時にスイッチ回
路正常と判断して論理値1の出力を発生するウインドコ
ンパレータとを設けて構成した。また、前記信号受信ト
ランスの抽出出力を発生する2次側に、前記抽出出力に
対して逆相の信号を供給する信号供給手段を設けて構成
した。
Further, a rectifier circuit for rectifying the extracted output of the signal receiving transformer, and the rectified output of the rectifier circuit are inputted, and when the rectified output level is within a predetermined range, it is judged that the switch circuit is normal and the logical value is 1 And a window comparator that generates the output of the. Further, the secondary side for generating the extraction output of the signal receiving transformer is provided with signal supply means for supplying a signal having a reverse phase to the extraction output.

【0009】[0009]

【作用】かかる構成において、スイッチ回路の電磁リレ
ー接点と半導体スイッチ素子とが共に正常で短絡故障し
ていない場合、信号発生回路から信号送信トランスを介
して一方の雑音防止回路に伝達された交流のスイッチ回
路故障検出用信号は、他方の雑音防止回路に挿入された
信号受信トランスで受信される。この場合には、信号受
信トランスからの抽出出力は論理値1(出力有り)とな
る。
In such a structure, when both the electromagnetic relay contact of the switch circuit and the semiconductor switch element are normal and there is no short-circuit failure, the alternating current transmitted from the signal generation circuit to the one noise prevention circuit is transmitted through the signal transmission transformer. The switch circuit failure detection signal is received by the signal reception transformer inserted in the other noise prevention circuit. In this case, the extracted output from the signal receiving transformer has the logical value 1 (output is present).

【0010】一方、電磁リレー接点及び半導体スイッチ
素子のどちらか一方が短絡していると、信号発生回路か
ら信号送信トランスを介して一方の雑音防止回路に伝達
された交流のスイッチ回路故障検出用信号は、スイッチ
回路の短絡によって信号受信トランス側に流れず受信さ
れない。このため、信号受信トランスからの抽出出力は
論理値0(出力無し)となる。
On the other hand, when one of the electromagnetic relay contact and the semiconductor switch element is short-circuited, an AC switch circuit failure detection signal transmitted from the signal generation circuit to one noise prevention circuit via the signal transmission transformer. Is not received because it does not flow to the signal receiving transformer side due to the short circuit of the switch circuit. Therefore, the extraction output from the signal receiving transformer has a logical value of 0 (no output).

【0011】また、雑音防止回路のコンデンサが短絡し
た場合には、雑音防止回路のインピーダンス変化によ
り、信号受信トランスの1次側に流れる電流が変化し、
信号受信トランスの抽出出力レベルが変化する。そし
て、この短絡時の抽出出力レベルがウインドコンパレー
タの窓の範囲(設定レベル範囲)外となるように設定す
ることで、雑音防止回路のコンデンサの短絡故障も検出
できる。
Further, when the capacitor of the noise prevention circuit is short-circuited, the current flowing in the primary side of the signal receiving transformer changes due to the impedance change of the noise prevention circuit,
The extraction output level of the signal receiving transformer changes. Then, by setting the extraction output level at the time of the short circuit to be outside the window range (setting level range) of the window comparator, it is possible to detect the short circuit failure of the capacitor of the noise prevention circuit.

【0012】また、前記信号受信トランスの抽出出力を
発生する2次側に、前記抽出出力に対して逆相の信号を
供給する信号供給手段を設けることで、雑音防止回路の
コンデンサが短絡した時の信号受信トランスの抽出出力
のレベル変化率を拡大することができ、レベル検定にお
ける閾値設定が容易になる。
When the capacitor of the noise prevention circuit is short-circuited by providing a signal supply means for supplying a signal having a reverse phase to the extracted output on the secondary side for generating the extracted output of the signal receiving transformer. The level change rate of the extraction output of the signal receiving transformer can be expanded, and the threshold setting in the level test becomes easy.

【0013】[0013]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。図1は、本発明に係るスイッチ回路の故障検出装
置の第1実施例を適用した負荷駆動回路を示す。尚、図
1に示す故障検出装置は、スイッチ回路の短絡故障のみ
を考慮した場合のものである。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a load drive circuit to which a first embodiment of a failure detection device for a switch circuit according to the present invention is applied. The failure detection device shown in FIG. 1 is for the case where only a short circuit failure of the switch circuit is considered.

【0014】図1において、商用の交流電源である負荷
駆動電源1から交流電流を負荷2に給電する給電回路
に、前記負荷2と直列にスイッチ回路3が接続されてい
る。該スイッチ回路3は、電磁リレー4の励磁時ONす
るリレー接点4aと半導体スイッチ素子としての例えば
SSR5との直列回路からなる。前記リレー接点4aに
は、接点OFF時の雑音を防止するため抵抗R1 とコン
デンサC1 の直列回路からなる第1の雑音防止回路であ
る第1スナバ回路6が並列接続されている。また、SS
R5にも、同じく抵抗R2 とコンデンサC2 からなる第
2の雑音防止回路である第2スナバ回路7が並列接続さ
れている。そして、前記第1スナバ回路6に、信号発生
回路8で発生する交流のスイッチ回路故障検出用信号を
第1スナバ回路6側に伝達する信号送信用トランスT1
の2次巻線が直列に挿入されている。また、第2スナバ
回路7には、第1スナバ回路6に伝達されたスイッチ回
路故障検出用信号を受信して抽出する信号受信トランス
T2の1次巻線が直列に挿入されている。この信号受信
トランスT2の2次巻線には、抽出出力を整流する整流
回路9が接続されている。ここで、前記第1及び第2ス
ナバ回路6,7と、信号送信トランスT1と、信号受信
トランスT2と、信号発生回路8及び整流回路9で本実
施例の故障検出装置10が構成される。また、負荷8に
も、同様に抵抗R3 とコンデンサC3 の直列回路からな
る雑音防止用のスナバ回路が設けられている。
In FIG. 1, a switch circuit 3 is connected in series with the load 2 to a power feeding circuit for feeding an alternating current from a load driving power source 1 which is a commercial AC power source to the load 2. The switch circuit 3 comprises a series circuit of a relay contact 4a which is turned on when the electromagnetic relay 4 is excited and a semiconductor switch element, for example, an SSR 5. A first snubber circuit 6, which is a first noise prevention circuit including a series circuit of a resistor R 1 and a capacitor C 1 , is connected in parallel to the relay contact 4a in order to prevent noise when the contact is turned off. Also, SS
A second snubber circuit 7, which is a second noise prevention circuit and is also composed of a resistor R 2 and a capacitor C 2 , is connected in parallel to R5. Then, a signal transmission transformer T1 for transmitting to the first snubber circuit 6 an AC switch circuit failure detection signal generated in the signal generation circuit 8 to the first snubber circuit 6 side.
Secondary windings are inserted in series. A primary winding of a signal receiving transformer T2 that receives and extracts the switch circuit failure detection signal transmitted to the first snubber circuit 6 is inserted in series in the second snubber circuit 7. A rectifier circuit 9 that rectifies the extracted output is connected to the secondary winding of the signal receiving transformer T2. Here, the first and second snubber circuits 6 and 7, the signal transmitting transformer T1, the signal receiving transformer T2, the signal generating circuit 8 and the rectifying circuit 9 constitute the failure detecting device 10 of the present embodiment. Similarly, the load 8 is also provided with a noise preventing snubber circuit including a series circuit of a resistor R 3 and a capacitor C 3 .

【0015】尚、信号送信トランスT1を第2スナバ回
路7側に、信号受信トランスT2を第1スナバ回路6側
に設けて構成してもよい。一方、スイッチ回路3に負荷
駆動信号を入力する信号入力部は、自己保持回路11
と、フェールセーフなOFFディレー回路12と、フェ
ールセーフなONディレー回路13と、前記電磁リレー
4とを備えて構成されている。
The signal transmitting transformer T1 may be provided on the second snubber circuit 7 side and the signal receiving transformer T2 may be provided on the first snubber circuit 6 side. On the other hand, the signal input unit for inputting the load drive signal to the switch circuit 3 is the self-holding circuit 11
And a fail-safe OFF delay circuit 12, a fail-safe ON delay circuit 13, and the electromagnetic relay 4.

【0016】自己保持回路11は、前記故障検出装置1
0の出力(整流回路9の出力)をトリガ入力とし、負荷
駆動信号INをリセット入力として、前記トリガ入力を
自己保持する構成である。フェールセーフなOFFディ
レー回路12は、自己保持回路11の出力が入力すると
同時に出力が立ち上がり、自己保持回路11の出力が停
止した時に所定時間遅延して出力が立ち下がり、電磁リ
レー4を励磁・消磁してリレー接点4aをON−OFF
制御する。ONディレー回路13は、自己保持回路11
の出力が入力すると所定時間遅延して出力が立ち上が
り、自己保持回路11の出力が停止した時に同時に出力
が立ち下がり、SSR5のON−OFFを制御する。
The self-holding circuit 11 is provided in the failure detecting device 1
The output of 0 (output of the rectifier circuit 9) is used as a trigger input, the load drive signal IN is used as a reset input, and the trigger input is held by itself. The fail-safe OFF-delay circuit 12 rises at the same time when the output of the self-holding circuit 11 is input, and when the output of the self-holding circuit 11 stops, the output falls after a predetermined time delay to excite / demagnetize the electromagnetic relay 4. ON / OFF the relay contact 4a
Control. The ON delay circuit 13 includes the self-holding circuit 11
When the output of (1) is input, the output rises with a delay of a predetermined time, and when the output of the self-holding circuit 11 stops, the output falls at the same time to control ON / OFF of the SSR 5.

【0017】尚、自己保持回路11は、故障時に出力が
論理値0となるフェールセーフな構成であり、また、O
FFディレー回路12及びONディレー回路13も、遅
延時間が遅れ側の故障のみ許されるフェールセーフな構
成である。次に、この負荷駆動回路及び故障検出装置の
動作を説明する。まず、スイッチ回路3が正常の場合に
ついて説明する。
The self-holding circuit 11 has a fail-safe structure in which the output becomes a logical value of 0 when a failure occurs, and O
The FF delay circuit 12 and the ON delay circuit 13 also have a fail-safe configuration in which only the failure on the delay time side is allowed. Next, the operations of the load drive circuit and the failure detection device will be described. First, the case where the switch circuit 3 is normal will be described.

【0018】負荷駆動信号INが発生する以前では、信
号発生回路8からの短絡故障検出用信号が、信号送信ト
ランスT1の1次側から2次側に伝達され第1スナバ回
路6に伝達される。この時、スイッチ回路3のリレー接
点4aとSSR5はOFF状態にあるため、この短絡故
障検出用信号は、信号受信トランスT2の1次側を介し
て2次側で抽出され高エネルギ状態の論理値1(出力有
り)の出力が整流回路9に入力する。整流回路9の整流
出力は、自己保持回路11にトリガ入力信号として入力
する。この状態で、負荷駆動信号INが、自己保持回路
11のリセット入力信号として入力すると、自己保持回
路11から出力が発生し、OFFディレー回路12及び
ONディレー回路13に入力する。OFFディレー回路
12では、自己保持回路11からの信号が入力すると同
時に出力が立ち上がり電磁リレー4が励磁される。これ
により、図2に示すように、自己保持回路11の立ち上
がりからリレー特性で定まる多少の遅延時間t2 後にリ
レー接点4aがONとなる。また、ONディレー回路1
3は、図2に示すように、自己保持回路11からの信号
が入力してから所定の遅延時間t1 (t1 >t2 )遅れ
て出力が立ち上がり、SSR5がONとなる。このよう
に、リレー接点4aがONとなってからSSR5がON
となり、負荷2に駆動電流が流れ、負荷2が駆動され
る。尚、リレー接点4aがONした時点から、信号受信
トランスT2側に信号発生回路8からの信号が伝達され
なくなり、整流回路8の出力レベルが論理値0となって
自己保持回路11のトリガ入力信号がなくなるが、この
トリガ入力は自己保持回路11の出力で自己保持され自
己保持回路11は出力を発生し続ける。
Before the load drive signal IN is generated, the short circuit fault detection signal from the signal generation circuit 8 is transmitted from the primary side to the secondary side of the signal transmission transformer T1 and is transmitted to the first snubber circuit 6. . At this time, since the relay contact 4a of the switch circuit 3 and the SSR 5 are in the OFF state, this short-circuit fault detection signal is extracted on the secondary side via the primary side of the signal receiving transformer T2 and the logical value of the high energy state is obtained. The output of 1 (with output) is input to the rectifier circuit 9. The rectified output of the rectifier circuit 9 is input to the self-holding circuit 11 as a trigger input signal. In this state, when the load drive signal IN is input as the reset input signal of the self-holding circuit 11, an output is generated from the self-holding circuit 11 and is input to the OFF delay circuit 12 and the ON delay circuit 13. In the OFF delay circuit 12, an output rises and the electromagnetic relay 4 is excited at the same time when the signal from the self-holding circuit 11 is input. As a result, as shown in FIG. 2, the relay contact 4a is turned on after a delay time t 2 which is determined by the relay characteristic from the rising of the self-holding circuit 11. Also, the ON delay circuit 1
As shown in FIG. 2, the output of the signal No. 3 rises after a predetermined delay time t 1 (t 1 > t 2 ) from the input of the signal from the self-holding circuit 11, and the SSR 5 is turned on. In this way, the SSR 5 turns on after the relay contact 4a turns on.
Then, a drive current flows through the load 2 and the load 2 is driven. From the time when the relay contact 4a is turned on, the signal from the signal generating circuit 8 is not transmitted to the signal receiving transformer T2 side, the output level of the rectifying circuit 8 becomes a logical value 0, and the trigger input signal of the self-holding circuit 11 is obtained. However, the trigger input is self-held by the output of the self-holding circuit 11, and the self-holding circuit 11 continues to generate an output.

【0019】その後、負荷駆動信号INが停止すると、
自己保持回路11の出力は同時に立ち下がり、ONディ
レー回路13の出力も同時に立ち下がりSSR5が直ち
にOFFとなって負荷2への駆動電流の給電がなくなり
負荷2の駆動が停止する。そして、図2に示すように、
SSR5がOFFしてから所定時間t3 後にOFFディ
レー回路12の出力が立ち下がり電磁リレー4が消磁し
てリレー接点4aがOFFとなる。
After that, when the load drive signal IN is stopped,
The output of the self-holding circuit 11 falls at the same time, the output of the ON delay circuit 13 also falls at the same time, and SSR5 is immediately turned off, so that the drive current is not supplied to the load 2 and the driving of the load 2 is stopped. Then, as shown in FIG.
SSR5 relay contacts 4a to output drops electromagnetic relay 4 Standing degaussing the OFF to OFF delay circuit 12 after a predetermined time t 3 from the turned OFF.

【0020】SSR5に短絡故障が発生した場合、信号
発生回路8から信号送信トランスT1を介して第1スナ
バ回路6に伝達される短絡故障検出用信号は、SSR5
の短絡によって第2スナバ回路7には流れず信号受信ト
ランスT2側に伝達されない。従って、信号受信トラン
スT2の抽出出力レベルは論理値0(出力無し)とな
り、自己保持回路11のトリガ入力信号はない。このた
め、負荷駆動信号INが自己保持回路11に入力しても
自己保持回路11は出力を発生せず、リレー接点4aが
OFF状態となって負荷2には駆動電流が供給されるこ
とはない。
When a short circuit fault occurs in the SSR5, the short circuit fault detection signal transmitted from the signal generation circuit 8 to the first snubber circuit 6 via the signal transmission transformer T1 is SSR5.
Due to the short circuit, the current does not flow into the second snubber circuit 7 and is not transmitted to the signal receiving transformer T2 side. Therefore, the extraction output level of the signal receiving transformer T2 becomes a logical value 0 (no output), and there is no trigger input signal of the self-holding circuit 11. Therefore, even if the load drive signal IN is input to the self-holding circuit 11, the self-holding circuit 11 does not generate an output, and the relay contact 4a is in the OFF state, so that the drive current is not supplied to the load 2. .

【0021】従って、SSR5が短絡故障して以後は、
負荷駆動電流INが発生してもリレー接点4aによって
駆動電流が遮断され負荷2は動作しない。尚、通常は負
荷2の給電は、実質的にSSR5によって制御されてリ
レー接点4aは負荷2の駆動電流をON−OFFしない
ので、溶着故障の心配はなく信頼性は高いものである。
Therefore, after the SSR 5 is short-circuited,
Even if the load drive current IN is generated, the drive current is cut off by the relay contact 4a and the load 2 does not operate. Normally, the power supply to the load 2 is substantially controlled by the SSR 5 and the relay contact 4a does not turn ON / OFF the drive current of the load 2, so there is no fear of welding failure and the reliability is high.

【0022】このように、本実施例の故障検出装置10
は、短絡故障がない時には論理値1の出力を発生し、短
絡故障時には論理値0の出力を発生する構成であり、出
力が発生するかしないかの2値の出力形態であるので、
従来のようなレベル変化を監視するものに比べて短絡故
障の検出が容易となり、検出精度が向上する。次に、図
3に本発明の故障検出装置の第2実施例を示す。この実
施例は、スイッチ回路3の短絡故障だけでなく第1及び
第2スナバ回路6,7のコンデンサC 1 ,C2 の短絡故
障も考慮したものである。尚、図1の第1実施例と同一
部分には同一符号を付して説明を省略する。
In this way, the failure detection device 10 of this embodiment
Generates a logical 1 output when there is no short-circuit fault and
In the case of a fault, the output of logical value 0 is generated.
Since it is a binary output form whether force is generated or not,
Due to a short circuit compared to the conventional type that monitors level changes
The obstacle can be easily detected, and the detection accuracy is improved. Next, the figure
3 shows a second embodiment of the failure detecting device of the present invention. This fruit
In the example, not only the short circuit failure of the switch circuit 3 but also the first and
Capacitor C of the second snubber circuits 6 and 7 1, C2Because of the short circuit
Obstacles are taken into consideration. The same as the first embodiment of FIG.
The same reference numerals are given to the parts and the description thereof will be omitted.

【0023】図3において、本実施例の故障検出装置2
0では、第1実施例の構成に加えて整流回路9の後段
に、故障時に出力が論理値0となるフェールセーフな従
来公知のウインドコンパレータWCが接続されている。
かかる構成において、スナバ回路6,7のコンデンサC
1 ,C2 が正常の時と短絡故障した時とで、スナバ回路
6,7のインピーダンスが変化し、スナバ回路6,7に
流れる電流が変化する。これにより、信号受信トランス
T2で抽出される信号電圧が変化する。
In FIG. 3, the failure detection device 2 of this embodiment is shown.
At 0, in addition to the configuration of the first embodiment, a fail-safe conventionally known window comparator WC whose output becomes a logical value 0 at the time of failure is connected to the subsequent stage of the rectifier circuit 9.
In such a configuration, the capacitor C of the snubber circuits 6 and 7
The impedances of the snubber circuits 6 and 7 change between when the C 1 and C 2 are normal and when there is a short circuit failure, and the current flowing through the snubber circuits 6 and 7 changes. As a result, the signal voltage extracted by the signal receiving transformer T2 changes.

【0024】従って、ウインドコンパレータWCの窓の
範囲設定を、コンデンサC1 ,C2が正常の時の信号受
信トランスT2の抽出出力レベルが窓の範囲内となり、
コンデンサC1 ,C2 が短絡故障した時の信号受信トラ
ンスT2の抽出出力レベルが窓の範囲外となるように設
定する。これにより、コンデンサC1 ,C2 の正常時
は、ウインドコンパレータWCから論理値1の出力が自
己保持回路11にトリガ入力信号として入力し、コンデ
ンサC1 ,C2 の短絡故障時には、ウインドコンパレー
タWCの出力が論理値0となって自己保持回路11のト
リガ入力がなくなる。このため、コンデンサC1 ,C2
が短絡故障すれば、負荷駆動信号INが入力しても自己
保持回路11から出力が発生せず負荷2は駆動しない。
尚、スイッチ回路3の短絡時には、信号受信トランスT
2の出力レベルが論理値0となり、ウインドコンパレー
タWCの窓の範囲外となるので、スイッチ回路3の短絡
故障も検出できることは言うまでもない。
Therefore, when setting the window range of the window comparator WC, the extraction output level of the signal receiving transformer T2 when the capacitors C 1 and C 2 are normal is within the window range.
Extracting the output level of the signal received transformer T2 when the capacitor C 1, C 2 are short-circuited is set to be out of the range of the window. Accordingly, when the capacitors C 1 and C 2 are normal, the output of the logic value 1 is input from the window comparator WC to the self-holding circuit 11 as a trigger input signal, and when the capacitors C 1 and C 2 are short-circuited, the window comparator WC is output. Output becomes a logical value 0, and the trigger input to the self-holding circuit 11 disappears. Therefore, the capacitors C 1 , C 2
If there is a short-circuit failure, the self-holding circuit 11 does not generate an output even if the load drive signal IN is input, and the load 2 is not driven.
When the switch circuit 3 is short-circuited, the signal receiving transformer T
Since the output level of 2 has a logical value of 0 and is outside the window range of the window comparator WC, it goes without saying that a short circuit failure of the switch circuit 3 can also be detected.

【0025】ところで、上記第2実施例の構成では、コ
ンデンサC1 ,C2 の正常時と短絡故障時の信号受信ト
ランスT2の抽出出力の変化率が小さく、ウインドコン
パレータWCの窓の範囲を狭く設定する必要があり、設
定が厳しい。この正常時と短絡時の変化率を大きくする
ためコンデンサの容量を選択しても精々2倍弱の変化率
である。しかも、スナバ回路の機能を果たすためにコン
デンサC1 ,C2 の容量の選択範囲は狭く選択の自由度
は制限される。
By the way, in the configuration of the second embodiment, the change rate of the extraction output of the signal receiving transformer T2 is small when the capacitors C 1 and C 2 are normal and when the short-circuit failure occurs, and the window range of the window comparator WC is narrowed. It is necessary to set, and the setting is strict. Even if the capacitance of the capacitor is selected in order to increase the change rate between the normal state and the short circuit, the change rate is slightly less than twice. Moreover, in order to perform the function of the snubber circuit, the selection range of the capacitances of the capacitors C 1 and C 2 is narrow and the degree of freedom of selection is limited.

【0026】このようなことから、信号受信トランスT
2の抽出出力の変化率を大きくする故障検出装置の例を
図4に第3実施例として示す。尚、図3の第2実施例と
同一部分には同一符号を付してある。図4において、本
実施例の故障検出装置30は、信号受信トランスT2の
2次側に、当該トランスT2の2次巻線と逆巻の巻線C
A を設け、該巻線CA を、信号送信トランスT1の1次
巻線と直列に信号発生回路8に接続して信号受信トラン
スT2の2次側に抽出出力と逆相の電圧を供給する。こ
こで、巻線CA と信号発生回路8とで信号供給手段が構
成される。
From the above, the signal receiving transformer T
FIG. 4 shows an example of a failure detection device for increasing the rate of change of the extraction output of No. 2 as a third embodiment. The same parts as those in the second embodiment of FIG. 3 are designated by the same reference numerals. In FIG. 4, the failure detection device 30 according to the present exemplary embodiment includes, on the secondary side of the signal receiving transformer T2, a secondary winding C and a reverse winding C of the transformer T2.
A is provided, and the winding C A is connected in series with the primary winding of the signal transmission transformer T1 to the signal generation circuit 8 to supply a voltage of opposite phase to the extraction output to the secondary side of the signal reception transformer T2. . Here, the winding C A and the signal generation circuit 8 constitute a signal supply means.

【0027】かかる構成において、本実施例の信号受信
トランスT2の抽出出力レベルは、図3の第2実施例の
ものに比べて、巻線CA で供給される逆相分だけ小さく
なる。これに対して、コンデンサC1 ,C2 の正常時と
短絡時のトランスT2の抽出出力レベルの変化は第2実
施例と同じである。このため、信号受信トランスT2の
抽出出力に対する正常時と故障時の変化の割合、即ち変
化率は、抽出出力レベルが小さくなった分拡大されるこ
とになる。従って、正常時と故障時とで信号受信トラン
スT2の出力変化を大きくでき、ウインドコンパレータ
WCの窓の範囲設定が楽になり、故障検出の信頼性を高
めることができる。
In such a configuration, the extraction output level of the signal receiving transformer T2 of this embodiment is smaller than that of the second embodiment of FIG. 3 by the amount of the reverse phase supplied by the winding C A. On the other hand, changes in the extraction output level of the transformer T2 when the capacitors C 1 and C 2 are normal and when they are short-circuited are the same as in the second embodiment. Therefore, the rate of change between the extraction output of the signal receiving transformer T2 at the time of normal operation and at the time of failure, that is, the rate of change, is expanded by the amount of decrease in the extraction output level. Therefore, the output change of the signal receiving transformer T2 can be increased between the normal time and the failure time, the window range of the window comparator WC can be set easily, and the reliability of the failure detection can be improved.

【0028】[0028]

【発明の効果】以上説明したように本発明によれば、ス
イッチ回路の短絡の有無の判定を2値、即ち、論理値1
と0で示すことができ、レベル検定の必要がなく、短絡
故障の検出が容易となる。また、故障検出装置の最終段
にウインドコンパレータを設ければ、雑音防止回路のコ
ンデンサ短絡故障も検出することが可能となり、負荷の
スイッチ制御のフェールセーフ性を高めることができ、
産業機械のインタロック制御に極めて有効である。
As described above, according to the present invention, it is possible to determine whether or not a switch circuit is short-circuited by a binary value, that is, a logical value of 1.
Can be represented by 0, and there is no need for level verification, which facilitates detection of short-circuit faults. Further, if a window comparator is provided at the final stage of the failure detection device, it is possible to detect a capacitor short circuit failure of the noise prevention circuit, and it is possible to enhance the fail-safety of load switch control.
It is extremely effective for interlock control of industrial machines.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係るスイッチ回路故障検出装置の第1
実施例を適用した負荷駆動回路の例を示す図
FIG. 1 is a first circuit diagram of a switch circuit failure detection device according to the present invention.
The figure which shows the example of the load drive circuit which applied the Example.

【図2】同上第1実施例のリレー接点とSSRと負荷駆
動電流の状態を示すタイムチャート
FIG. 2 is a time chart showing states of a relay contact, an SSR, and a load drive current according to the first embodiment.

【図3】本発明に係るスイッチ故障検出装置の第2実施
例を示す回路図
FIG. 3 is a circuit diagram showing a second embodiment of the switch failure detection device according to the present invention.

【図4】本発明に係るスイッチ故障検出装置の第3実施
例を示す回路図
FIG. 4 is a circuit diagram showing a third embodiment of the switch failure detection device according to the present invention.

【符号の説明】[Explanation of symbols]

1 負荷駆動電源 2 負荷 3 スイッチ回路 4 電磁リレー 4a リレー接点 5 SSR(半導体スイッチ素子) 6 第1スナバ回路 7 第2スナバ回路 8 信号発生回路 9 整流回路 10,20,30 故障検出装置 T1 信号送信トランス T2 信号受信トランス WC ウインドコンパレータ 1 load drive power supply 2 load 3 switch circuit 4 electromagnetic relay 4a relay contact 5 SSR (semiconductor switch element) 6 first snubber circuit 7 second snubber circuit 8 signal generating circuit 9 rectifier circuit 10, 20, 30 failure detection device T1 signal transmission Transformer T2 signal receiving transformer WC window comparator

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】電磁リレー接点と半導体スイッチ素子の直
列回路で構成され、負荷駆動信号が入力した時に前記電
磁リレー接点と半導体スイッチ素子がONして負荷に給
電し、負荷駆動信号の入力が停止した時に前記電磁リレ
ー接点と半導体スイッチ素子がOFFして負荷への給電
を停止する構成のスイッチ回路の故障を検出するスイッ
チ回路故障検出装置において、抵抗とコンデンサの直列
回路からなり前記電磁リレー接点に対して並列に接続さ
れる第1の雑音防止回路と、同じく抵抗とコンデンサの
直列回路からなり前記半導体スイッチング素子に対して
並列に接続される第2の雑音防止回路と、スイッチ回路
故障検出用信号を発生する信号発生回路と、どちらか一
方の雑音防止回路に直列に挿入されて前記スイッチ回路
故障検出用信号を当該雑音防止回路側に伝達する信号送
信トランスと、他方の雑音防止回路に直列に挿入されて
前記スイッチ回路故障検出用信号を受信して抽出する信
号受信トランスとを備えて構成し、電磁リレー接点及び
半導体スイッチ素子の少なくとも一方が短絡した時に信
号受信トランスの抽出出力が論理値0となることを特徴
とするスイッチ回路故障検出装置。
1. A series circuit comprising an electromagnetic relay contact and a semiconductor switch element, wherein when the load drive signal is input, the electromagnetic relay contact and the semiconductor switch element are turned on to supply power to the load, and the input of the load drive signal is stopped. In the switch circuit failure detection device for detecting a failure of the switch circuit configured to stop the power supply to the load by turning off the electromagnetic relay contact and the semiconductor switch element, the electromagnetic relay contact is composed of a series circuit of a resistor and a capacitor. A first noise prevention circuit connected in parallel to the switching circuit, a second noise prevention circuit which is also composed of a series circuit of a resistor and a capacitor and is connected in parallel to the semiconductor switching element, and a switch circuit failure detection signal. Which is inserted in series with either the noise generating circuit or the signal generating circuit for generating the switch circuit failure detection signal. A signal transmitting transformer for transmitting to the noise prevention circuit side, and a signal receiving transformer that is inserted in the other noise prevention circuit in series and receives and extracts the switch circuit failure detection signal, and an electromagnetic relay contact And a switch circuit failure detection device, wherein the extracted output of the signal receiving transformer becomes a logical value 0 when at least one of the semiconductor switching elements is short-circuited.
【請求項2】前記信号受信トランスの抽出出力を整流す
る整流回路と、該整流回路の整流出力を入力して当該整
流出力レベルが所定範囲内にある時にスイッチ回路正常
と判断して論理値1の出力を発生するウインドコンパレ
ータとを設けて構成した請求項1記載のスイッチ回路故
障検出装置。
2. A rectifier circuit for rectifying the extracted output of the signal receiving transformer, and the rectified output of the rectifier circuit is input to determine that the switch circuit is normal when the rectified output level is within a predetermined range and a logical value of 1 is obtained. 2. The switch circuit failure detection device according to claim 1, further comprising a window comparator that generates the output of the switch circuit.
【請求項3】前記信号受信トランスの抽出出力を発生す
る2次側に、前記抽出出力に対して逆相の信号を供給す
る信号供給手段を設けて構成した請求項2記載のスイッ
チ回路故障検出装置。
3. The switch circuit failure detection according to claim 2, wherein the secondary side for generating the extraction output of the signal receiving transformer is provided with signal supply means for supplying a signal of a reverse phase to the extraction output. apparatus.
JP5116134A 1993-05-18 1993-05-18 Switching circuit fault detecting device Pending JPH06331679A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5116134A JPH06331679A (en) 1993-05-18 1993-05-18 Switching circuit fault detecting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5116134A JPH06331679A (en) 1993-05-18 1993-05-18 Switching circuit fault detecting device

Publications (1)

Publication Number Publication Date
JPH06331679A true JPH06331679A (en) 1994-12-02

Family

ID=14679572

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5116134A Pending JPH06331679A (en) 1993-05-18 1993-05-18 Switching circuit fault detecting device

Country Status (1)

Country Link
JP (1) JPH06331679A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0681310A1 (en) * 1993-11-19 1995-11-08 The Nippon Signal Co. Ltd. Load driving circuit
WO1996030923A1 (en) * 1995-03-31 1996-10-03 The Nippon Signal Co., Ltd. Solenoid relay driving circuit
EP1202313A1 (en) * 2000-10-23 2002-05-02 Safecom Ag Device for safety engineering to supervise the switching position of mechanical contacts
WO2003030198A1 (en) * 2001-09-22 2003-04-10 Pilz Gmbh & Co. Safety switch device for safe disconnection of an electric consumer
JP2014050912A (en) * 2012-09-06 2014-03-20 Fanuc Ltd Brake drive control circuit for detecting short-circuit failure of switching element
WO2014057724A1 (en) * 2012-10-10 2014-04-17 住友建機株式会社 Shovel and method for controlling shovel
CN106468752A (en) * 2016-09-27 2017-03-01 武汉大学 A kind of solid circuit breaker RCD buffer circuit being integrated with fault location function and trouble point checking method

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0681310A1 (en) * 1993-11-19 1995-11-08 The Nippon Signal Co. Ltd. Load driving circuit
US5574320A (en) * 1993-11-19 1996-11-12 The Nippon Signal Co., Ltd. Load drive circuit
EP0681310A4 (en) * 1993-11-19 1997-12-10 Nippon Signal Co Ltd Load driving circuit.
WO1996030923A1 (en) * 1995-03-31 1996-10-03 The Nippon Signal Co., Ltd. Solenoid relay driving circuit
US5818681A (en) * 1995-03-31 1998-10-06 The Nippon Signal Co., Ltd. Electromagnetic relay drive circuit
EP1202313A1 (en) * 2000-10-23 2002-05-02 Safecom Ag Device for safety engineering to supervise the switching position of mechanical contacts
WO2003030198A1 (en) * 2001-09-22 2003-04-10 Pilz Gmbh & Co. Safety switch device for safe disconnection of an electric consumer
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