JPH06327074A - Duplex atm cell disassembling device - Google Patents

Abstract

PURPOSE:To switch systems without the omission of frames by matching the states of two systems so as to let the frames outputted from both systems be equal at all times at the time of switching the systems at the time of duplex constitution. CONSTITUTION:This system is constituted of the cell disassembling circuit 10a of a '0' system and the cell disassembling circuit 10b of a '1' system. 'Then, a frame monitoring part 7 compares a message byte number inside a memory 4 for work read by the frame output control part 5 of the present system ('0' system) and the frame read from a shared buffer memory 2 with the respective frames informed from the memory 4 for the work of the other system ('1' system) and the shared buffer memory 2 and performs transition from an asynchronized state to a synchronized state when everything coincides. Further, when the '0' system is a standby system and the synchronized state is smarted, the same frame reproduced inside the '0' system matched with the message byte number and the frame from the '1' system is abandoned and the states of the systems are matched so as to let the frames outputted from both systems be equal at all times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duplex ATM cell disassembling apparatus, and in particular, an original message of an arbitrary length is disassembled into fixed-length cells at a plurality of transmission sources, and address information and control information indicating the transmission source of the cell. Is added to each of the cells, the cells are time-division multiplexed and transmitted, the transmitted cells are received, and the cells are disassembled to reproduce the original message corresponding to each source. The present invention relates to an ATM cell disassembly device.

[0002]

2. Description of the Related Art In such an ATM communication system, when an original message of an arbitrary length is decomposed into fixed length cells and transmitted by a communication device side, each cell is formed as shown in FIG. .

2A and 2B are diagrams showing a cell format capable of performing strict error detection / error control defined in the CCITT recommendation and a cell in which the processing shown in the CCITT recommendation is simplified. FIGS. 3A, 3B, 3C, and 3D are diagrams for explaining the format, and FIGS.

The format shown in FIG. 2A will be described. This format has a 5-byte header (H
header) and a 48-byte payload part (Paylo)
ad) and.

The header portion contains address information (A
DR), payload attribute information (PT), priority control bits (CLP) and error detection information (HEC)
Is included.

The payload part includes segmentation information (ST) and sequence number information (SN), and S
T is position information BOM, COM, SSM described later,
SN indicates the order of cells.

Referring to FIG. 3A, the frame is 45
The original message a1 having a length of at least bytes is decomposed into the original message a2 of a fixed length cell in units of 44 bytes.

At this time, if a surplus portion (indicated by diagonal lines) occurs in the final cell, blank space information of all "0" is inserted in that portion, and the byte length (LI) of the significant data in the payload portion is included. The number of valid bytes is set, and the number of valid bytes is set in the LI of the first cell and the intermediate cell.

The original message a2 of each fixed length cell
Is added with the position information in the original message a1 of each cell as control information. There are two types of position information that differ depending on the cell format.

One is that the portion included in the cell is the head portion of the original message a1 (that is, the start position (BOM: Beg:
(Inning Of Message)) or an intermediate portion (that is, a middle position (COM: Continuation)
n Of Message)) or the last part (that is, the last position (EOM: End Of Message))
It is a method of adding or. In this system, serial number information (SN), effective length display (LI), and error control information (P-CRC) are further added as control data (first system).

The other is a method of adding only the final part, and the header information (HD) includes an identifier for displaying the final data (second method).

AT assembled by the first method
The M cell a3 has header information (H
D) is added. This HD is an address indicating the source of the ATM cell a3. Management data (M
1) and the management data (M2) are added to form a transmission cell having a fixed length. M1 is the above ST (2 bits),
SN (4 bits) of each cell and MID / Re described later
saved (consisting of 10 bits, M2 is L
It is composed of I (6 bits) and error detection information (P-CRC: 10 bits). Also, the payload part has 44
The original message a2 decomposed into bytes is placed.

In FIG. 3A, the original message a1 is longer than 45 bytes, but it may be shorter than 44 bytes. In this case, as shown in FIG. 3 (B), the original message b1 of a frame having a length of 44 bytes or less is an original message b2 of one 44-byte fixed length cell, and the blank space (indicated by diagonal lines) is all. It becomes "0". The position information of this cell is SSM (Single Se).
gment Message). The assembled ATM cell b3 has the same structure as the above-mentioned ATM cell a3.

Returning to FIG. 2A, MID / Reser
ved (10 bits) is reserved and has a length of 44 bytes including a message in the next PLD. As described above, LI indicates the byte length of significant data in the payload part, and P-CRC is error detection information other than the header part.

Next, the format shown in FIG. 2B will be described. This format is composed of a 5-byte header portion (Header) and a 48-byte payload portion (Payload), as in FIG.

The header portion contains address information (A
DR), payload attribute information (PT), priority control bits (CLP) and error detection information (HEC)
Is included.

In this format, the PT is shown in FIG.
As shown in (C), an identifier indicating whether the cell contains the final data of the original message is included, and if the final data is displayed in the header information (HD), the cell is reproduced in the original message only by this. And assemble into ATM cell c3.

AT assembled by the second method
M cell c3 has header information (H
D) is added. This is an address indicating the source of the ATM cell c3. FIG. 3 shows the ATM cell c3.
There is no management data (M1, M2) shown in (A) and (B).

The payload part has 48 bytes, and the data of the original message c2, which is obtained by dividing the original message c1 into 48 bytes, is carried.

FIG. 3D is composed of only the original message d1 of the frame having a length of 48 bytes, and the header information (HD) of the assembled ATM cell d2 has the identifier of the final data display.

The above-described cells are randomly time-division multiplexed and transmitted from a plurality of transmission sources. Therefore,
On the receiving side, multiple buffer memories that physically or logically correspond to the sender are prepared and multiple messages are played back at the same time. Therefore, both the working memory and the buffer memory used are large. I have no choice.

In the prior art, as shown in FIG. 6, the dualization of the ATM cell disassembling apparatus was realized by taking over the information by copying the working memory and the buffer memory in two systems.

FIG. 6 is a system block diagram showing an example of a conventional ATM cell disassembling apparatus, and FIG. 7 is a diagram for explaining the state transition of system switching control in the conventional example.

Referring to FIGS. 6 and 7, this system is composed of a 0-system cell disassembling circuit 20a and a 1-system cell disassembling circuit 20b.
Is provided with a system switching control unit 21, a cell disassembly control unit 22, a work memory 23 and a buffer memory 24.

When the system switching instruction signal is input to the system switching control unit 21, the contents of the current act working memory 23 and buffer memory 24 are copied to the standby working memory 23 and buffer memory 24. The system is started and the system is in the process of switching.

At the same time, the operation of the cell disassembly control unit 22 is stopped so that the contents of the working memory 23 and the buffer memory 24 are not updated by the received cell. This is to prevent the contents of the already copied memories from becoming inconsistent.

When the memory copy of all the contents of the working memory 23 and the buffer memory 24 is completed, the system switching control unit 21 outputs a system switching end signal, and the act system cell disassembly circuit becomes the new standby system and the old standby system system. The cell disassembling circuit of is completely switched to the new act system, and the cell disassembling circuit of the new act system starts the cell disassembling operation.

The switching operation from the standby state to the act state is similarly performed by inputting the system switching instruction.

[0029]

DISCLOSURE OF THE INVENTION This conventional dual AT
In the system switching method in the M cell disassembling apparatus, the cell reception is stopped and the system is switched at the time of system switching, so that cell loss and frame discard associated therewith occur.

Further, the discarding of a plurality of frames causes a rapid increase in traffic due to retransmission in the upper layer and an apparent deterioration in transmission quality. Furthermore, when the multiplicity is increased, the amount of memory is inevitably increased, which causes a problem that the system switching time becomes long.

The object of the present invention is to switch the system without stopping the reception of cells at the time of system switching, so that cell loss and frame discard associated therewith do not occur, and instantaneously in the synchronous mode. By providing a duplex ATM cell disassembling apparatus that does not require the time required for memory copy by allowing the system to be switched and allowing the time to transit to the synchronous mode even in the asynchronous mode. is there.

[0032]

According to the present invention, an existing original message having an arbitrary length is decomposed into cells of a fixed length, and address information indicating a cell source for each cell and Control information including position information for reproducing the original message of the cell is added, all the cells are multiplexed and transmitted, and the original message corresponding to each source is reproduced while disassembling the transmission cell. In the ATM cell disassembling apparatus, the system switching control means for duplexing, the frame output control means, and the output frame monitoring means are provided.
In the standby system, the reproduced frame is compared with the frame output from the act system and the reproduced frame is discarded as the frame is output from the act system. The device is obtained.

Further, a shared buffer memory for storing a corresponding message in a corresponding storage area in which a storage area corresponding to the sender is stored, and each message in a corresponding cell in the corresponding storage area in which a storage area is defined for the sender. A working memory for storing the number of bytes; a first storage means for sequentially storing the number of message bytes of the corresponding cell in a corresponding area of the working memory according to the address information of the transmitted cell; Second storage means for sequentially extracting the message of the corresponding cell according to the address information of the cell and storing the message in the corresponding storage area of the shared buffer memory; and the position information of the transmitted cell indicates the final position. Of the corresponding storage area of the working memory according to the number of message bytes of the corresponding storage area of the working memory. Output means for sequentially reading and outputting the message; first notifying means for notifying the opposite system of the contents of the corresponding storage area of the working memory when reading and outputting the messages sequentially; and output from the opposite system Comparison means for monitoring the content of the message and comparing the content of the notified work memory and the content of the output message with the content of the work memory and the content of the message inside the own system, respectively, and the result of this comparison. And a second notification means for notifying that the work memory has a storage area defined corresponding to the transmission source, and stores the number of each message byte in the corresponding cell and its serial number information in the corresponding storage area. , The first storing means stores the number of message bytes of the corresponding cell and the previous message according to the address information of the transmitted cell. Duplication ATM cell disassembly device according to claim 2, characterized in that sequentially stores the serial number information in a corresponding area of the working memory is obtained.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a system block diagram showing an embodiment of the duplicated ATM cell disassembling apparatus of the present invention, FIG. 4 is a flow chart for explaining the operation of transitioning from an asynchronous state to a synchronous state according to this embodiment, and FIG. It is a figure explaining the state transition of the system switching control in one Example of this invention.

Referring to FIG. 1, this system comprises a 0-system cell disassembling circuit 10a and a 1-system cell disassembling circuit 10b. Each cell disassembling circuit 10a, 10b comprises a system switching control unit 6 and a cell disassembling controller. Part 1, a shared buffer memory 2 for storing a corresponding message in a corresponding storage area in which a storage area is defined for each sender, and a number of message bytes in a corresponding cell in the corresponding storage area for which a storage area is defined for each sender And a working memory 4 for storing the serial number information as necessary, and the message byte number of the corresponding cell according to the address information of the transmitted cell and the serial number information as necessary, the corresponding area of the working memory 4. Are sequentially stored in the shared buffer memory 2, and the message of the corresponding cell is extracted according to the address information of the transmitted cell and the corresponding storage area of the shared buffer memory 2 Sequentially stored in the cell disassembly control unit 3
And a frame output for sequentially reading and outputting messages in the corresponding storage area of the common buffer memory 2 according to the number of message bytes in the corresponding storage area of the working memory 4 when the position information of the transmitted cell indicates the final position. When the control unit 5 and the message are sequentially read and output, the content of the corresponding storage area of the work memory 4 is notified to the opposite system, and the content of the message output from the opposite system is monitored to notify the work memory. 4 and the content of the output message are compared with the content of the internal work memory 4 of the own system and the content of the message, respectively, and a frame monitoring unit 7 for notifying the result of the comparison is provided.

Next, the operation of the present invention will be described with reference to FIGS. 1, 2, 4 and 5.

For example, when the 0-system cell disassembling circuit 10a inputs a cell from a host device (not shown), the cell disassembling unit 1 extracts the header information (HD) and the above-mentioned control information from the received cell, and the cell disassembling control unit. 3, the cell disassembly control unit 3 sends the significant data byte length (LI) of the payload portion of the received cell to the shared buffer memory 2.

In the shared buffer memory 2, the storage area is divided into a plurality of areas. When necessary, the corresponding message is stored in the area in association with the transmitting device, and the corresponding message is output to cope with it when it is no longer needed. The attachment is released.

The working memory 4 has a storage area corresponding to the transmitting device, and the control data for reproducing the frame is read from the corresponding area and the control data is stored in the corresponding area (step S41). Further, the contents of the work memory 4 are updated and controlled by the cell disassembly control unit 3 every time each cell is received.

The frame output controller 5 is a cell disassembly controller 3
Work memory 4 based on the frame reproduction completion instruction from
The information in is read out and the presence or absence of a reproduction frame is checked (S42). When the reproduction is completed (S42 is present), as shown in FIG. 5, the frames accumulated in the shared buffer memory 2 are read and output in the order in which the reproduction is completed.

The frame output control unit 3 outputs the accumulated frames according to an instruction from the frame monitoring unit 7.

The system switching control unit 6 gives an instruction to the frame monitoring unit 7 to notify the synchronous / asynchronous state to the outside and display it, and according to the instruction from the outside, as shown in FIG. The system switching control is performed according to the internal state, and the forced system switching control that ignores the internal state is also performed.

The frame monitoring unit 7 uses the number of message bytes in the work memory 4 read by the frame output control unit 5 of its own system (0 system) and the frame read from the shared buffer memory 2 as the work of another system (1 system). The respective frames notified from the memory 4 and the shared buffer memory 2 (S43) are compared with each other (S44), and when all match, the asynchronous state is changed to the synchronous state.

When the 0 system is the standby system and enters the synchronous state,
As shown in FIG. 5, the same frames reproduced in the 0 system are discarded according to the number of message bytes and frames from the 1 system, and the frames output from both systems are always equal. Match the conditions.

When the 0-system is trying to output the frame asynchronously and the number of message bytes is different from the frame and message bytes from the 1-system (mismatch in S44), the comparison operation is stopped and the next frame is the act-system. The output of the first system is waited for, and when the transmission of the next frame is started, the operation of comparing the same frame from the beginning again is repeated.

When the comparison operation of one frame is repeated the number of times equal to the number of the plurality of buffers divided and formed on the shared buffer memory 2 (S45), the act system has already output. Since the frames are being compared with each other, all the reproduction-completed frames accumulated in the shared buffer memory 2 are discarded (S
46) Then, the reproduction and comparison operations of the frame are newly performed again to establish the synchronization state.

It should be noted that, in FIG. 4, the number of comparisons is 0 when there is none in S42 and when all the frames are discarded in S46.
When it becomes (S47), the process returns to S41. Also, S
43 when no frame is received from the 1st system, and S4
When the number of comparisons in 5 is not equal to the number of buffers, the number of comparisons is updated (S48), and the process returns to S43.

[0049]

As described above, according to the present invention, in an ATM cell disassembling device for reproducing a large number of ATM cells from a large number of transmitting devices, both systems output at the time of system switching when the duplex configuration is adopted. Since the states of the two systems are matched so that the frames are always the same, it is possible to switch the systems without frame loss, which causes a sudden increase in traffic and apparent deterioration in transmission quality due to retransmission in the upper layer. It has an effect that it can be prevented.

Further, as compared with the simple memory copy method, there is an effect that the system switching can be completed in an extremely short time.

[Brief description of drawings]

FIG. 1 is a system block diagram showing an embodiment of a duplicated ATM cell disassembling apparatus of the present invention.

2A and 2B are diagrams showing a cell format capable of performing strict error detection / error control defined in the CCITT recommendation and a cell format obtained by simplifying the processing shown in the CCITT recommendation. FIG.

3 (A), (B), (C) and (D) are diagrams for explaining an example of converting an original message into ATM cells.

FIG. 4 is a flowchart for explaining an operation of transitioning from an asynchronous state to a synchronous state according to this embodiment.

FIG. 5 is a diagram illustrating state transition of system switching control according to an embodiment of the present invention.

FIG. 6 is a system block diagram showing an example of a conventional ATM cell disassembling apparatus.

FIG. 7 is a diagram illustrating a state transition of system switching control in a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Cell disassembly section 2 Shared buffer memory 3,22 Cell disassembly control section 4,23 Working memory 5 Frame output control section 6,21 System switching control section 7 Frame monitoring section 10a, 10b, 20a, 20b Cell disassembly circuit 24 Buffer memory a1 Original message of a frame having a length of 45 bytes or more a2 Original message BO decomposed into 44 bytes
M, COM, EOM a3, b3, c3, d2 assembled ATM cell b1 original message of frame having a length of 44 bytes or less b2 original message SS decomposed into 44 bytes
M c1 Original message of frame having a length of 48 bytes × n (n ≦ 2) c2 Original message decomposed into 48 bytes d1 Original message of frame having a length of 48 bytes

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location H04L 12/48 8732-5K H04L 11/20 C 9076-5K H04Q 11/04 M

Claims (3)

[Claims] 1. An existing original message having an arbitrary length is decomposed into fixed-length cells, and for each cell, address information indicating a source of the cell and the original message of the cell are reproduced. Control information including position information is added,
In an ATM cell disassembly device that multiplexes and transmits all the cells and reproduces the original message corresponding to each transmission source while disassembling the transmission cells, a system switching control means for duplication and a frame output control means In the standby system, the reproduced frame is compared with the frame output from the act system, and the reproduced frame is discarded when the frame is output from the act system. A dual ATM cell disassembling device characterized by going. 2. A shared buffer memory for storing a corresponding message in a corresponding storage area in which a storage area corresponding to the transmission source is defined, and each message in a corresponding cell in the corresponding storage area in which a storage area is defined corresponding to the transmission source. A working memory for storing the number of bytes; a first storage means for sequentially storing the number of message bytes of the corresponding cell in a corresponding area of the working memory according to the address information of the transmitted cell; Second storage means for sequentially extracting the message of the corresponding cell according to the address information of the cell and storing the message in the corresponding storage area of the shared buffer memory; and the position information of the transmitted cell indicates the final position. When there is a message in the corresponding storage area of the working memory, the message in the corresponding storage area of the shared buffer memory is Output means for sequentially reading and outputting the messages, first notifying means for notifying the opposite system of the contents of the corresponding storage area of the working memory when the messages are sequentially read and outputted, and the output means for outputting from the opposite system. Comparing the contents of the notified work memory and the contents of the output message with the contents of the work memory and the contents of the message inside the own system, respectively, and this comparison is performed. Second to notify the result
2. The duplicated ATM cell disassembling apparatus according to claim 1, further comprising: 3. The working memory has a storage area defined corresponding to the transmission source, and stores the number of each message byte in the corresponding cell and its serial number information in the corresponding storage area, and the first storage means transmits the message. 3. The duplex ATM cell disassembling apparatus according to claim 2, wherein the number of message bytes of the corresponding cell and the serial number information are sequentially stored in the corresponding area of the working memory according to the address information of the received cell.