JPH06326522A - Analog signal processing integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption change against the fluctuation of the power voltage and to prolong the service life of a battery by building a switching circuit into a bias voltage generating circuit in order to change the bias voltage level in response to the bias control signal. CONSTITUTION:The power voltage level is monitored by a power voltage monitoring circuit 8. Then the circuit 8 outputs a control signal when the power voltage exceeds a prescribed level. A bias voltage generating circuit 9 contains a switching circuit which receives the control signal from the circuit 8 and changes the bias voltage level. Thus the bias voltage level is changed and the voltage of a level lower than the normal bias voltage is generated if the power voltage exceeds a prescribed level. As a result, no extra power is consumed and the increase of the power consumption can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit for analog signal processing, which consumes less current consumption over a wide power supply voltage range.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing the structure of a conventional analog signal processing integrated circuit, and shows the structure of a filter-contained AD converting integrated circuit. The analog signal input from the analog signal input terminal 3 is input to the AD converter 5 via the filter 4 and converted into a digital signal. The converted digital signal is output to the digital signal output terminal 10 via the control circuit 6. A reference voltage from the reference voltage generating circuit 7 is supplied to the AD converter 5. Further, a predetermined bias voltage from the bias voltage generation circuit 9 is supplied to the filter 4 and the AD converter 5.

FIG. 9 is a circuit diagram of a typical class A CMOS operational amplifier used in the filter 4 and the AD converter 5. 1 is a positive power supply terminal, 2 is a negative power supply terminal, 9
Reference numeral 01 is a negative phase input terminal, 902 is a positive phase input terminal, 903 is an output terminal, and 904 is a bias voltage input terminal. This operational amplifier is used in units of several tens in the filter 4 and the AD converter 5, and occupies most of the current consumption of the integrated circuit.

FIG. 10 is a circuit diagram showing one example of a conventional CMOS bias voltage generating circuit 9. 1a is a positive power supply input terminal (Vp), 2a is a negative power supply input terminal (Vn),
101 is a bias voltage output terminal. In the figure, a transistor N is an N-channel transistor, and a transistor P is a P-channel transistor.
The channel MOS transistor is called NMOS.

The output 101 of the bias voltage generating circuit shown in FIG. 10 is used in the filter 4 and the AD converter 5.
Is connected to the bias input terminal 904 of the operational amplifier shown in FIG. As can be seen from the figure, the output voltage of the bias voltage generating circuit shown in FIG. 10 is connected between the gate and drain of each MOS transistor, so that each MOS transistor has an operating point in the saturation region and the drain of each transistor. The current is expressed by the following equation (1).

Id = 1/2 * β * W / L * (Vgs-Vt) ² (1) where β = μ * Co μ: mobility, Co: gate capacitance per unit area W: gate Width, L: Gate length Vgs: Gate-source voltage Now, assuming that the β and Vt values of each transistor are equal, MOS
The gate-source voltage (= source-drain voltage) of the transistors P3, N5, N6 is Vgs1, Vgs2, Vgs
Assuming 3, the following equation (2) is established.

[0007]

[Equation 1]

Here, the value of Vgs3 that satisfies the above equation (2) becomes the bias voltage output. This means that the bias voltage increases as the power supply voltage increases, and the bias voltage decreases as the power supply voltage decreases.

The current consumption of the operational amplifier is determined by the value of the ratio W / L of the gate width W and the channel length L of the NMOS transistors N7 and N8 shown in FIG. 9 and the magnitude of the bias voltage input from the bias circuit. Since the transistors N7 and N8 are also biased so as to be in the saturation region, the drain current thereof is represented by the above-described equation (1) and changes in proportion to the square of the bias voltage fluctuation.

[0010]

As described above, in the conventional integrated circuit for analog signal processing, when the power supply voltage used increases, the bias voltage of the operational amplifier increases, the consumption current of the operational amplifier increases, and the power supply voltage decreases. Then, the bias voltage of the operational amplifier is reduced and the current consumption of the operational amplifier is also reduced. The current consumption of the operational amplifier is set according to the frequency of the signal for which signal processing such as addition is performed by the operational amplifier. If the frequency is high, the current value of the operational amplifier is large, and if the frequency is low, the current value of the operational amplifier is set small.

A battery is used as a power source in a portable device. The generated voltage of this battery varies greatly between the initial stage and the final stage of use. If this voltage from the battery is used as it is as the power supply voltage of the conventional analog signal processing integrated circuit, a power supply current more than necessary flows in the initial stage of use and the life of the battery is shortened. In order to avoid this, it is general to insert a regulator for stabilizing the voltage in the battery output, but the use of the regulator has a problem that it hinders miniaturization in a portable device that is aimed at miniaturization.

The present invention has been made in order to solve the above-mentioned problems, and the analog signal processing suitable for a portable device for extending the battery life by reducing the change in current consumption with respect to the fluctuation of the power supply voltage of the analog signal processing integrated circuit. It is an object of the present invention to provide an integrated circuit for use.

[0013]

SUMMARY OF THE INVENTION The present invention provides a reference voltage generating circuit that outputs a substantially constant reference voltage regardless of fluctuations in the power supply voltage in a certain range, and a bias voltage that depends on the magnitude of the power supply voltage. Bias voltage generating circuit to output,
An analog signal processing integrated circuit having an analog signal processing circuit which operates by receiving the supply of the reference voltage or / and a bias voltage, wherein the power supply voltage is one input and the reference voltage is the other input, and the power supply voltage is Is larger than a predetermined value determined based on the reference voltage, a power supply voltage monitoring circuit that outputs a bias control signal, and the bias voltage generating circuit in the bias voltage generating circuit in response to the bias control signal. And switching circuit means for switching and outputting the size of the.

[0014]

In the present invention, the magnitude of the power supply voltage is monitored by the power supply voltage monitoring circuit, and when the magnitude of the power supply voltage is in a range larger than a predetermined voltage, the power supply voltage monitoring circuit outputs a control signal. To be done. The bias voltage generation circuit has a built-in switching circuit that receives the control signal and changes the magnitude of the bias voltage. Therefore, when the power supply voltage is higher than a predetermined value, the bias voltage is changed and a voltage lower than the normal bias voltage is output. For this reason, extra current consumption is eliminated and an increase in current consumption is suppressed.

[0015]

1 is a block diagram of an analog signal processing integrated circuit according to an embodiment of the present invention. In FIG. 1, a filter built-in type AD converter is shown as an embodiment. It should be noted that the same reference numerals as those in the conventional circuit configuration are given the same reference numerals in the drawings, and detailed description thereof will be omitted.

The present invention is different from the prior art in that the power supply voltage monitoring circuit 8 is provided and the bias voltage generating circuit 9 controlled by the control signal 8c is provided. The output of the reference voltage generation circuit 7 is the second input terminal 8 of the power supply voltage monitoring circuit 8.
It is connected to the reference voltage input terminal 5a of the AD converter 5 as well as connected to a. The positive power supply voltage terminal 1 is connected to the first input terminal 8b of the power supply voltage monitoring circuit 8. The output terminal 8c of the power supply voltage monitoring circuit 8 is connected to the control input terminal 9a of the bias voltage generating circuit 9. Bias voltage generation circuit 9
9b is connected to the bias voltage input terminal of the operational amplifier used for the filter 4 and the AD converter 5.

FIG. 2 is a circuit diagram showing an example of the reference voltage generating circuit shown in FIG. 201 is a reference voltage output terminal, which includes bipolar transistors Q1 and Q2 and a resistor R
1, R2, R3, a reference voltage generating circuit using a bandgap voltage of a so-called NPN transistor composed of a bias circuit built-in operational amplifier A1, and a resistor R
4, R5, and a voltage adjusting circuit composed of a bias circuit built-in operational amplifier A2, the output voltage change is small even if the power supply voltage changes.

FIG. 3 is a circuit diagram showing an example of the power supply voltage monitoring circuit 8 of FIG. 1, in which 301 is an output terminal, a first voltage divider 303 connected to the first input terminal 302, and a second input. It is composed of a second voltage divider 305 and a comparator 306 connected to the terminal 304. A resistor voltage divider is shown as an example of the voltage divider. The output 307 of the first voltage divider 303 is connected to the negative phase input terminal of the comparator 306, and the output terminal 308 of the second voltage divider 305 is connected to the positive phase input terminal of the comparator 306. When the voltage of the negative phase input terminal is lower than the voltage of the positive phase input terminal of the comparator, the output of the comparator 306 outputs a substantially positive power supply voltage, and when the voltage of the negative phase input terminal is higher than the voltage of the positive phase input terminal. Comparator 306
The output of is a substantially negative power supply voltage.

FIG. 4 shows a circuit diagram of the comparator. Reference numeral 401 represents a negative phase input terminal, 402 represents a positive phase input terminal, and 403 represents an output terminal. Here, the positive power supply voltage is applied to the first input terminal 302 of the power supply voltage monitoring circuit shown in FIG. 3, and the output voltage of the reference voltage generating circuit is applied to the second input terminal 304.

FIG. 5 shows the bias voltage generating circuit 9 shown in FIG.
In an example of a specific circuit configuration of 501, 501 is a control input terminal,
Reference numeral 02 denotes a bias voltage output terminal. The source terminal of the PMOS transistor P1 is connected to the positive power supply, the gate and the drain are commonly connected, and the drain and the gate of the NMOS transistor N1 are connected. The source of the transistor N1 is the drain and gate of the NMOS-N2, and the NMOS-
It is connected to the drain of N3 and the source of PMOS-P2, respectively. The gate of the transistor N3 is the transistor P
2 drain and NMOS-N4 drain. The gates of the transistors P2 and N4 are commonly connected and connected to the control input terminal 501. Transistor N2
The sources of N3 and N4 are connected to the negative power supply terminal.

The output from the power supply voltage monitoring circuit 8 is input to the control input terminal 501, and when the voltage of the control input terminal 501 is substantially a negative power supply voltage, the transistor P2 is turned on, the transistor N4 is turned off, and the transistor N3 is turned on.
Is connected in parallel with N2 and outputs the first bias voltage. When the voltage of the control input terminal 501 is substantially positive power supply voltage, the transistor P2 is turned off and the transistor N4 is turned on, so that the transistor N3 is turned off and the second bias voltage is output.

Now, if the power supply voltage is the same, the first bias voltage is smaller than the second bias voltage. In order to explain the operation of the analog signal processing integrated circuit configured as described above, it is assumed that the negative power supply voltage changes to 0V and the range of the positive power supply voltage changes from 3.6V to 2.7V. An example of the voltage division ratio of a circuit is shown. The division ratio of the first voltage divider 303 is set to 1/2, and the division ratio of the second voltage divider 305 is set so that the positive phase input terminal voltage of the comparator of the power supply voltage monitoring circuit becomes 1.5V. For example, if the reference voltage output is 2V, the division ratio of the second voltage divider 305 is 3/4.

In the voltage monitoring circuit set in this way, when the power supply voltage is higher than 3V, the power supply voltage monitoring circuit is "0".
A bias circuit that outputs (substantially negative power supply voltage) and uses this as a control input outputs a first bias voltage. When the power supply voltage is lower than 3V, the power supply voltage monitoring circuit outputs "1" (substantially positive power supply voltage), and the bias circuit having this as a control input outputs the second bias voltage. The first bias voltage value and the second bias voltage value satisfy the W of each transistor of the bias circuit so as to satisfy the minimum value of the current consumption required for the operational amplifier even when the power supply voltage changes.
Determine the value of / L.

FIG. 6 is a characteristic diagram showing a state of change in power consumption with respect to power supply voltage. The portion extended by the dotted line in the figure shows the state of current consumption when the bias is not switched.
Next, another configuration example of the power supply voltage monitoring circuit will be described.

In the above-mentioned embodiment, the comparison voltage of the monitoring circuit is explained as one point of 1.5V, but the fluttering of the output of the power supply voltage monitoring circuit (the fluttering of the bias voltage) due to a minute fluctuation of the power supply voltage in a short time is explained. To prevent this, the comparator of the power supply voltage monitoring circuit can have a hysteresis width. FIG. 7 is a circuit diagram showing a configuration example of a power supply voltage monitoring circuit having such a hysteresis characteristic. 70
1 is a first input terminal, 702 is a second input terminal, 703
Is the output terminal. Two of the first voltage divider 704 connected to the first input terminal 701 and the second voltage divider 705 connected to the second input terminal 702 and having two divided outputs Va and Vb (Va> Vb). Switch 70 composed of MOS transistors for selectively outputting any one of the two outputs
7. A comparator 706 in which the output of the first voltage divider 704 is connected to the negative phase input and the output of the switch 707 is connected to the positive phase input. Here, the switch 707 is configured to select Vb when the comparator output 703 is “0” and select Va when the comparator output 703 is “1”.

In order to explain the operation of the power supply voltage monitoring circuit shown in FIG. 7 configured as described above, the negative power supply voltage is 0V,
Assuming that the positive power supply voltage range changes from 3.6V to 2.7V, the division ratio of the first voltage divider 704 is set to 1/2, and the division ratio of the second voltage divider 705 is 1.6 when Va is 1.6.
V and Vb are set to be 1.5V. By doing so, when the power supply voltage is higher than 3V, the output 703 of the comparator 706 becomes "0" and the switch 707 is turned on.
Selects Vb. When the power supply voltage becomes lower than 3V, the output 707 of the comparator 706 becomes "1" and the switch 707 selects Va. When the comparison voltage of the comparator 706 is changed from Vb to Va, the power supply voltage becomes 3.
Comparator 706 unless the voltage exceeds 2V
Does not change state. That is, even if the power supply voltage monitoring circuit in FIG. 7 detects a decrease in the power supply voltage and the power supply voltage fluctuates to a higher value within a range smaller than 0.2 V, the monitoring output does not change the state and the bias controlled by this monitoring output is used. The voltage cannot be switched.

In the above description, the case where there is one monitor voltage of the power supply voltage has been described, but it corresponds to the transistor N3 as shown in FIG. 5 in which a plurality of monitor circuits are provided and a plurality of them are provided by the control output of the plurality of monitor circuits. The bias voltage can be finely controlled by controlling the NMOS transistor.

[0028]

As described above in detail with reference to the embodiments, the integrated circuit for analog signal processing according to the present invention is provided with the power supply voltage monitor circuit so that the bias voltage can be switched by the output of the power supply voltage monitor circuit. Therefore, it is possible to reduce the change in consumption current over a wide range of the power supply voltage. Further, if the power supply voltage monitoring circuit has a hysteresis width, the bias voltage is not switched even if the power supply voltage fluctuates in a short time, and an integrated circuit for analog signal processing with stable current consumption can be realized. Is possible.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an analog signal processing integrated circuit according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram of a reference voltage generation circuit used in the present invention.

FIG. 3 is a block circuit diagram showing a configuration of a power supply voltage monitoring circuit used in the present invention.

FIG. 4 is a circuit diagram of a comparator used in the present invention.

FIG. 5 is a circuit diagram of a bias voltage generation circuit used in the present invention.

FIG. 6 is a characteristic diagram showing the relationship between the power supply voltage and the consumption current, which explains the operation of the present invention.

FIG. 7 is a block diagram showing the configuration of a power supply voltage monitoring circuit used in another embodiment of the present invention.

FIG. 8 is a block diagram showing an example of a conventional integrated circuit for analog signal processing.

FIG. 9 is a circuit diagram showing a configuration of a conventional operational amplifier.

FIG. 10 is a circuit diagram showing a configuration of a conventional bias voltage generation circuit.

[Explanation of symbols]

 1 Positive Power Supply Terminal 2 Negative Power Supply Terminal 3 Analog Signal Input 4 Filter 5 AD Converter 6 Control Circuit 7 Reference Voltage Generation Circuit 8 Power Supply Voltage Monitoring Circuit 9 Bias Voltage Generation Circuit

Claims (3)

[Claims] 1. A reference voltage generation circuit that outputs a substantially constant reference voltage regardless of fluctuations in the power supply voltage within a certain range, and a bias voltage generation circuit that outputs a bias voltage that depends on the magnitude of the power supply voltage. An analog signal processing integrated circuit having an analog signal processing circuit which operates by receiving the supply of the reference voltage or / and a bias voltage, wherein the power supply voltage is one input and the reference voltage is the other input, and the power supply voltage is A power supply voltage monitoring circuit that outputs a bias control signal when the magnitude of the bias voltage is greater than a predetermined value determined based on the reference voltage; and the bias voltage in the bias voltage generation circuit in response to the bias control signal. An integrated circuit for analog signal processing, comprising switching circuit means for switching and outputting the size of the signal. 2. The power supply voltage monitoring circuit includes a first voltage division circuit, a second voltage division circuit, and a comparison circuit,
The power supply voltage is divided by the first division circuit, the reference voltage is divided by the second voltage division circuit, and the divided voltage is input to each input terminal of the comparison circuit, and the bias control voltage is taken out from the output terminal. An integrated circuit for analog signal processing according to claim 1. 3. The analog signal processing integrated circuit according to claim 1, wherein the switching circuit means performs switching by switching parallel connection of MOS transistors forming the bias voltage generating circuit.