JPH06326289A - Soled-state imaging device - Google Patents

Abstract

PURPOSE:To provide a solid-state imaging device applying a CMD to a light receiving element so as to evade the increase of parasitic resistance of a source part a drain part, when the picture element size of the CMD is reduced. CONSTITUTION:In a solid-state imaging device wherein a diffused source layer 11 and a diffused layer 12 are formed on an N<-> type channel layer 2 formed on a P<-> type semiconductor substrate 1, a gate electrode 4a is formed on the N<-> type channel layer 2 between the source layer 11 and the drain layer 12, via a gate oxide film 3, and a CMD is applied to light receiving element, silicide films 10 are formed only on the source layer 11 and the drain layer 12.

Description

Detailed Description of the Invention

[0001]

This invention relates to a charge modulation device (Char
The present invention relates to a solid-state imaging device using a ge Modulation Device (hereinafter abbreviated as CMD) as a light receiving element.

[0002]

2. Description of the Related Art Conventionally, various solid-state image pickup devices having a light receiving element having a MIS type light receiving / accumulating portion have been proposed. For example, Japanese Patent Application Laid-Open No. 61-84059 discloses a solid-state image pickup device using a CMD having a MIS type light receiving / accumulating portion and having an internal amplification function as a light receiving element.

Next, a solid-state image pickup device using a conventional CMD type CMD light receiving element will be described. FIG. 10 is a cross-sectional view showing a configuration of one pixel portion of a solid-state imaging device using a known CMD previously proposed by the applicant of the present application as a light receiving element. In FIG. 10, 101 is a P ⁻ type semiconductor substrate, and 102
Is an N ⁻ type channel layer composed of an N ⁻ type epitaxial layer grown on the semiconductor substrate 101 by an epitaxial method or the like. 103 is a gate oxide film formed on the surface of the N ⁻ type channel layer 102, and the thickness of the gate oxide film 103 is 200 to 50.
It is 0 Å. Reference numeral 104 denotes a gate electrode formed on the gate oxide film 103, which is made of, for example, polysilicon or the like and has a film thickness of about 1000 Å or less. Reference numeral 105 is a silicon oxide film formed on the gate electrode 104. 106 and 107 are N ⁺
The type source diffusion layer and the N ⁺ type drain diffusion layer are formed in self-alignment with the gate electrode 104 having the silicon oxide film 105 formed on the entire surface. Reference numeral 108 denotes a source electrode formed on the N ⁺ type source diffusion layer 106.

Next, the operation of the CMD light receiving element thus constructed will be briefly described. In FIG. 10, the gate electrode
The incident light 109 is incident from above the 104, N ^- -type channel layer 102 generates a signal charge in, N just below the signal charges (holes) of the gate electrode 104 ^- -type channel layer 10
Accumulates on the surface of 2. The accumulation of this signal charge modulates the electron current flowing between the N ⁺ type source diffusion layer 106 and the N ⁺ type drain diffusion layer 107 flowing in the N ⁻ type channel layer 102.

[0005]

By the way, in the solid-state imaging device using the CMD light receiving element having the above-mentioned conventional structure, the light receiving region in the CMD light receiving element is a gate electrode region provided between the source and drain diffusion layers. Therefore, the aperture ratio is improved by increasing the ratio of the gate area to the pixel area. Therefore, if miniaturization is performed in the direction of reducing the source and drain diffusion layers and the respective contact diameters, the pixel size can be reduced, that is, the resolution can be improved while the reduction in the amount of signal charges is minimized. It is possible to take advantage of the features of.

However, if the junction depth of the source and drain diffusion layers is made shallow and the width of the diffusion layers is made narrower, there arises a problem that the resistance of the drain diffusion layer increases. Furthermore, when the source electrode 108 in the solid-state imaging device shown in FIG. 10 is made of aluminum commonly used in semiconductor processes, reducing the source contact diameter causes an increase in source contact resistance. The problem arises.

As described above, if the pixel size is reduced with the conventional CMD structure, the parasitic resistance such as the drain diffusion layer resistance or the source contact resistance increases. Then, the increase in the parasitic resistance causes an increase in the dispersion of the parasitic resistance, and as a characteristic of the CMD solid-state imaging device, eventually, an increase in the fixed pattern noise (FPN) due to the dispersion of the parasitic resistance is caused.

The present invention has been made to solve the above-mentioned problems in the conventional solid-state image pickup device using a CMD as a light receiving element. Even if the pixel size of the CMD is reduced, the parasitic resistance of the source and drain portions is reduced. It is an object of the present invention to provide a solid-state imaging device using a CMD as a light receiving element capable of preventing an increase in the number of pixels.

[0009]

In order to solve the above problems, the present invention provides a source diffusion layer and a drain diffusion layer provided on the same surface of a semiconductor layer formed on a high resistance semiconductor substrate, and the source diffusion layer. And a drain diffusion layer and a MOS gate region for accumulating carriers by photoexcitation provided between the drain diffusion layer and the drain diffusion layer. In the device, a silicide film is provided only on the source and drain diffusion layers of the CMD.

[0010]

[Function] Recently, DRAM (Dynamic Random Accessable)
In the memory process, a salicide (self-aligned silicide) structure has been proposed for reducing the resistance of the source, drain or gate electrode of a MOS transistor. The silicide is composed of a component of M _x Si, where M is a refractory metal such as Ti, W, Mo, Ni, Co or Cr,
x is a component ratio. The characteristic of this silicide is that its resistivity is lower than that of polycrystalline silicon by one digit or more.
It is stable even at high temperatures around 00 ° C and has excellent chemical resistance.

FIG. 11 shows a device sectional view of an N-channel MOSFET formed by a salicide process.
In FIG. 11, 201 is a p-type substrate, 202 is an n ⁺ -type source,
The drain diffusion layer 203 is a gate electrode made of polycrystalline silicon. The n ⁺ type source / drain diffusion layer 20
After exposing the surface of 2 and the surface of the gate electrode 203, T
A refractory metal such as i or Mo is grown on the entire surface of the wafer by a sputtering method or the like, and heat treated at about 600 ° C.
After the silicidation reaction is performed, the unreacted metal is etched to form the silicide layer 204. Further, this silicide layer is formed by CVD (Chemical Vapor Deposition).
) Method, it is also possible to form by selective growth of tungsten or the like only on the surfaces of the n ⁺ type source / drain diffusion layer 202 and the gate electrode 203. In addition,
This tungsten-CVD method is regarded as a promising plug process for selectively filling contact holes or via holes.

Further, as the silicide structure, W / Ti
A multilayer film structure of N / TiSi ₂ or the like has been proposed, but by adopting this salicide structure shown in FIG. 11, the sheet resistance of the source / drain diffusion layer 202 and the polycrystalline silicon gate electrode 203 is about several tens Ω. / Can be reduced by one digit or more. Due to this reduction in resistance, the time constant determined by the product of capacitance and resistance value is reduced by one digit or more, and high-speed device operation can be achieved.

In the present invention, the salicide technique applied to the MOSFET described above is adopted in the CMD device structure, and the silicide film is provided only on the source / drain diffusion layers as described above. As a result, CM
Even if the pixel size of D is reduced, it is possible to avoid an increase in the parasitic resistance of the drain diffusion layer and the source contact.
It is possible to realize an ultra-high-definition CMD solid-state imaging device with improved characteristics such as PN.

[0014]

EXAMPLES Next, examples will be described. 1 to 8
FIG. 4A is a cross-sectional view showing a CMD device process step for explaining the first embodiment of the solid-state imaging device according to the present invention. In FIG. 1, 1 is a P ⁻ type silicon substrate, 2 is a P ⁻ type silicon substrate.
Type channel layer 3 is N ^{- -} N formed by an epitaxial method or the like on the -type silicon substrate 1 type channel layer gate oxide film of SiO ₂ or the like formed on the second surface, 4 was formed on the gate oxide film 3 The polysilicon gate electrode film 5 is formed on the gate electrode film 4 by LPCVD (Low Pressure Chemical
It is an oxide film formed by the Vapor Deposition) method or the like. Next, as shown in FIG. 2, a resist film 6 is formed on the gate electrode formation region of the CMD by using a photolithography method, and an unnecessary oxide film 5 and a polysilicon gate electrode film 4 are formed.
Is anisotropically removed by a reactive ion etching method (RIE method) or the like to form the gate electrode 4a.

Then, as shown in FIG. 3, a resist film 6 is formed.
Is removed by ashing, and an insulating film 7 made of SiO ₂ or the like is formed on the entire surface by LPCVD again. Then, an etching back process of the insulating film 7 is performed by using the RIE method, so that a device cross-sectional structure including a sidewall 8 made of the insulating film 7 formed as a result of the etching back process is formed as shown in FIG. can get. Then, as shown in FIG. 5, Ti, W are formed by a CVD method, a sputtering method, or the like.
A thin film 9 of a refractory metal such as is formed on the wafer surface, and then heat treatment is performed to form a silicide film 10 on the peripheral portion of the sidewall 8. At this time, unlike MOSFET,
Since the polysilicon gate electrode 4a of CMD serves as a window for incident light, the silicide film 10 opaque to visible light is not formed on the polysilicon gate electrode 4a.

Next, as shown in FIG. 6, the unreacted metal thin film 9 is removed, and an n-type impurity 13 such as As is formed by ion implantation.
By doping the silicide film 10 or the surface of the N ⁻ type channel 2 with an annealing treatment,
A CMD source diffusion layer 11 and a drain diffusion layer 12 are formed. Next, as shown in FIG. 7, a flowing film 14 made of SiO ₂ or the like is formed on the entire surface, and then, as shown in FIG. 8, the source and drain diffusion layers 1 are formed on the flowing film 14.
Form the contact opening for wiring to 1 and 12,
The source and drain electrodes 15 are formed of aluminum or the like,
As a result, a solid-state imaging device including a CMD having a salicide structure can be obtained.

In the above process steps, as a method of forming the salicide structure, a CVD method of tungsten or the like is used.
If the refractory metal thin film can be selectively grown on the silicon surface, the step shown in FIG. 5 can be omitted after the step shown in FIG. 4 and the step shown in FIG. 6 can be performed. In addition, when an n-type impurity such as As can be added (doping) at the same time when the refractory metal thin film or the silicide film is formed, FIG.
Ion implantation in the step shown in FIG. Alternatively, the source and drain diffusion layers may be formed in advance by an ion implantation method, an annealing method, or the like before forming the silicide film.

In the solid-state image pickup device obtained by the above process steps, since the silicide film is formed only on the source and drain diffusion layers, the parasitic resistance of the source and drain portions and its variation can be reduced by the conventional CMD.
Compared to the solid-state imaging device, it is possible to reduce significantly,
Therefore, even if the pixel size of the CMD is reduced, it is possible to realize a CMD solid-state imaging device having good imaging characteristics without causing an increase in FPN.

Next, a second embodiment will be described with reference to FIG. In this embodiment, the silicide film 10 of the first embodiment shown in FIG. 8 has a multilayer film structure, and the other structure is the same as that of the first embodiment. In FIG. 9, 16 is the uppermost film 16
It is a silicide film having a multilayer film structure including a, the intermediate film 16b, and the lowermost film 16c. Examples of the structure of the multi-layer silicide film 16 include those having a W / TiN / TiSi ₂ structure from the surface. In the silicide film 16 having this multilayer film structure, by setting the film thickness t of the uppermost film 16a and the lowermost film 16c as shown in the following formula (1) or (2),
It is possible to minimize the reflection of stray light that enters the multilayer silicide film 16 from the front and bottom surfaces of the solid-state imaging device.

T = (2 · k · λ) / (4 · n) (1) t = [(2k + 1) · λ] / (4 · n) (2) where Where n is the refractive index of the uppermost film 16a or the lowermost film 16c, λ is the wavelength of visible light, and k is a natural number. The two expressions of the above expressions (1) and (2) exist because the conditions change depending on the magnitude of the refractive index above and below the film.

As the effect of the second embodiment, in addition to the effect of the first embodiment, the crosstalk of signals between pixels caused by stray light or the generation of a false signal such as flare is significantly larger than that of the conventional example. And the like.

Needless to say, the salicide structure shown in each of the above-described embodiments can be applied to a MOSFET that constitutes a peripheral circuit formed on the solid-state image pickup device at the same time as the light receiving portion. And the MOSFE that constitutes the peripheral circuit
For T, forming a silicide film on the gate electrode is effective for speeding up the peripheral circuit.

[0023]

As described above on the basis of the embodiments,
According to the present invention, even if the pixel size of the CMD is reduced, it is possible to avoid an increase in the drain diffusion layer and the source contact resistance and their variations, and it has good imaging characteristics without causing an increase in FPN. Super high definition C
An MD solid-state imaging device can be realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a pixel portion showing a manufacturing process for explaining a first embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process that follows the manufacturing process shown in FIG.

FIG. 3 is a cross-sectional view showing a manufacturing process that follows the manufacturing process shown in FIG.

FIG. 4 is a cross-sectional view showing a manufacturing process that follows the manufacturing process shown in FIG.

FIG. 5 is a cross-sectional view showing a manufacturing process that follows the manufacturing process shown in FIG.

FIG. 6 is a cross-sectional view showing a manufacturing process that follows the manufacturing process shown in FIG.

FIG. 7 is a cross-sectional view showing a manufacturing process that follows the manufacturing process shown in FIG.

FIG. 8 is a cross-sectional view showing a manufacturing process that follows the manufacturing process shown in FIG. 7.

FIG. 9 is a sectional view showing a second embodiment.

FIG. 10 is a cross-sectional view of one pixel portion showing a configuration example of a conventional CMD solid-state imaging device.

FIG. 11 is a cross-sectional view showing a configuration example of a MOSFET having a salicide structure.

[Explanation of symbols]

1 P ⁻ type silicon substrate 2 N ⁻ type channel layer 3 gate oxide film 4 polysilicon gate electrode film 4a gate electrode 5 oxide film 6 resist film 7 insulating film 8 sidewall 9 refractory metal thin film 10 silicide film 11 source diffusion layer 12 Drain diffusion layer 13 N-type impurity 14 Flowing film 15 Source / drain electrode 16 Multi-layered silicide film

Claims (2)

[Claims] 1. A source diffusion layer and a drain diffusion layer provided on the same surface of a semiconductor layer formed on a high resistance semiconductor substrate, and carriers accumulated by photoexcitation provided between the source diffusion layer and the drain diffusion layer. In a solid-state imaging device using as a light receiving element a charge modulation element having a MOS gate region and configured so that a source / drain current flows in parallel with the surface of the semiconductor layer, in the source and drain diffusion layers of the charge modulation element. A solid-state imaging device characterized in that a silicide film is provided only on the solid-state imaging device. 2. The solid-state imaging device according to claim 1, wherein the silicide film is composed of two or more kinds of multilayer films.