JPH06326257A - Semiconductor element and integrated circuit device employing same - Google Patents

Abstract

PURPOSE:To enhance reliability in the operation by employing a semiconductor element in which the operational reliability is enhanced by suppressing the generation of gate leak current and preventing the propagation of noise due to faint emission or high frequency signal from the inner compositional element to the semiconductor element. CONSTITUTION:A J.FET 32 comprises an N<+> region formed in a P substrate, an N<-> region on the N<+> region, a pair of P<+> regions 38, 39 comprising a source and a drain formed on the N<-> region on the opposite sides of the P<-> region 37, an N<+> region 40 for forming a gate embedded in the P<-> region 37 and an interlayer film 41. A source electrode 49, a rain electrode 50 and a gate electrode 51 are formed in the regions covering the through holes 45-47, respectively. A first metal shade layer 42 is formed in stripe within the range covering a stripe groove 48. In the interlayer film, a stripe groove 52 is formed within a range corresponding to the stripe groove 48 and a second metal shade layer 44 is formed covering the range surrounded by the stripe grooves 52, 52.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used as an example in an integrated circuit, has a high input impedance, and is required to realize an extremely minute gate leakage current and to perform stable operation against various noises. Junction FET
The present invention relates to a semiconductor element such as (junction field effect transistor) and an integrated circuit device using the same.

[0002]

2. Description of the Related Art A junction FET is a new type of mask, impurity implantation, and
It is an element that can be formed without the need for a step such as diffusion and can coexist with other bipolar semiconductor elements. Further, it has an advantage that it can be manufactured at low cost as compared with MOSFET (metal-oxide film-semiconductor FET). For this reason, it is often used in circuits that require high input impedance.

FIG. 3 shows a junction FET (hereinafter, J.
A circuit example of the photometric circuit 1 using a FET is shown. The circuit example of FIG. 3 is commonly used in the following description of the prior art and the description of the embodiments. The photometric circuit 1 includes a negative feedback type operational amplifier 2 and a photodiode 3 whose anode and cathode are connected to an inverting input terminal and a non-inverting input terminal of the operational amplifier 2. The operational amplifier 2 has J-FETs 6 and 7 whose inverting input terminal and non-inverting input terminal are respectively connected to their gates. The diode 4 is connected to the negative feedback circuit of the operational amplifier 2, and the anode of the diode 4 is connected to the inverting input terminal of the operational amplifier 2.
The cathode of the photodiode 3 is connected to the positive electrode of the DC power supply 5 having the power supply voltage V0.

The operation of the photometric circuit 1 will be described below. The photometric circuit 1 is a circuit that logarithmically compresses the output current Ip photoelectrically converted and output by the photodiode 3 so as to be easily processed in the integrated circuit. The photometric circuit 1 is used, for example, in a camera having an automatic exposure function, and is used in an integrated circuit that calculates and outputs an exposure value.

In the photometric circuit 1, the photodiode 3
The light incident on is photoelectrically converted, and the output current Ip is output from the photodiode 3. The output current Ip varies from several pA to several 100 μA according to the intensity of light incident on the photodiode 3. This output current Ip
Is logarithmically compressed by the operational amplifier 3,
Outputs the photometric output voltage Vout defined by the following first equation. However, in the first equation, k: Boltzmann constant,
T: absolute temperature, q: electron charge, Is: reverse saturation current of diode 4, Ip ′: forward current of diode 4,
IG: The gate leakage current of J.FET5.

[0006]

## EQU00001 ## Vout = V0-kT / q.times.ln (Ip '/ Is) = V0-kT / q.times.ln ((Ip-IG) / Is) In the first expression, the output in the case of the minimum value Condition Ip >> IG in which the gate leakage current IG is sufficiently smaller than the current Ip
Is satisfied, the photometric output voltage Vout is

[0007]

Equation 2 can be approximated as Vout = V0-kT / q × ln (Ip / Is). That is, the photometric output voltage Vout is output at a value having a correlation substantially defined by the second equation with the output current Ip until the output current Ip of the photodiode 3 is in a very small current region of several pA.

On the other hand, there are two factors that lower the photometric accuracy of the photometric circuit 1; the generation of a gate leak current of the J.FET and the effect of noise from an external circuit. (1) Gate leak current of J.FET The gate leak current IG has a value almost equal to the output current Ip which is the minimum value of about several pA, and the gate leak current IG is near the gate of the J.FET 6. When it occurs depending on the structure of the above, the second expression is satisfied only in the range where the output current Ip is sufficiently larger than the gate leak current IG. This is a case where the light quantity of the light incident on the photodiode 3 is sufficiently large, and when the light quantity of the incident light becomes low, it becomes difficult for the photometric circuit 1 to perform accurate photometry. In addition, the gate leakage current I
When G becomes larger, the J-FETs 6 and 7 cannot realize the designed performance.

There are the following two points as causes of the gate leak current IG in the J.FET 6 as described above.

Reverse leakage current IG1 at the PN junction existing in the structure of J-FET6.

The reverse leakage current IG1 will be described with reference to FIG. FIG. 8 is a perspective view showing a cross section of the J-FET 6 as an example. The J-FET 6 includes an N + region 9 formed in the P substrate 8 and an N- region 10 on the N + region 9.
And a pair of P + regions 12 and 13 serving as a source and a drain, sandwiching the P− region 11 on the N− region 10, and an N + region 14 buried in the P− region 11 and serving as a gate. To be done.

In J-FET6, the gate N +
By applying a predetermined potential to the region 14, a current flows between the P + regions 12 and 13 which are the source and the drain. At this time, as indicated by arrows A1 and A2 in FIG.
From the + region 14 to the P- region 11, and again in the N + region 9
The reverse leakage current IG1 flows from the P substrate 8 toward the P substrate 8.

This reverse gate leakage current IG1 is J
-Varies depending on the size of the FET 6 and the manufacturing process. As an example, the reverse gate leakage current IG1 increases as the PN junction area of the J.FET 6 increases.
The reverse gate leakage current IG1 is 1 pA or less at room temperature (about 25 ° C.).

In the integrated circuit, several 100 nm to several 10 nm generated from the PN junction part of the circuit around the J.FET 6
Gate leakage current IG2 due to the influence of extremely small light emission in the wavelength band of 00 nm.

The gate leakage current IG2 will be described with reference to FIG. FIG. 9 is a cross-sectional view of another conventional J.FET 6a included in the photometric circuit 1 shown in FIG. 3 configured as an integrated circuit. J.FE of this conventional example
Ta is similar to the configuration of the conventional example in FIG. 8, and the same reference numerals are given to corresponding portions. In the J-FET 6a, the interlayer film 15 is formed over substantially the entire surface of the P substrate 8. Through holes are formed in the interlayer film 15 at positions corresponding to the P + regions 12, 13 and the N + region 14, and the source electrode 1 covering the through holes is formed.
6, the drain electrode 18 and the gate electrode 17, and the P +
The regions 12, 13 and the N + region 14 are electrically connected. Further, an interlayer film 19 is formed by covering the source electrode 16, the drain electrode 18, the gate electrode 17 and the interlayer film 15.

At the PN junction of the circuit around the J-FET 6a shown in FIG. 9, weak light emission occurs when a current flows from the P region to the N region. This faint light emission
As an example in the integrated circuit, the light propagates through the interlayer films 15 and 19 and penetrates into other circuits such as the J-FET 6a shown in FIG. 9 as indicated by an arrow A3. Depending on the invading light, J
P between the N + region 14 and the P- region 11 of the FET 6a
PN between N junction or P substrate 8 and N- region 10
Exciting carriers at the junction, etc., arrows A4, A5
A gate leak current IG2 represented by is generated.

The propagation of the faint light emission propagates throughout the same integrated circuit, and its propagation path propagates in the propagation medium in an arbitrary direction according to the arrangement of the constituent elements such as the interlayer film serving as the propagation medium. .

Such a gate leak current IG2 has various occurrences and current levels depending on the scale of the integrated circuit, the arrangement of each component, the manufacturing process, and the like. According to the inventor of the present case, the maximum value may be several pA or more.

In the integrated circuit, the J-FET
If a circuit element having a large light emission amount is arranged in the vicinity of 6, the gate leakage current further increases. Such a circuit element that emits a large amount of light is the transistor 22 in a saturated state in the integrated circuit 20 shown in FIG. 10 as an example. The present inventor connected the base of the transistor 22 to the constant current source 21, and connected the ammeter 23 to the emitter of the transistor 22 to measure the emitter current IE. The collector of the transistor 22 has a common contact c of the switch 26.
The individual contact a of the switch 26 is open, and the individual contact b is connected to the ground potential. When the contact c-b of the switch 26 becomes conductive, the transistor 2
2 becomes non-saturated, and when the contact c-a of the switch 26 becomes conductive, the transistor 22 becomes saturated.

A J-FET 24 is provided near the transistor 22.
Was arranged, an ammeter 25 was connected to the gate of the J.FET 24, and the gate leak current IG2 of the J.FET 24 was measured. The measurement result is shown in the graph of FIG. The change in the gate leakage current IG2 with respect to the emitter current IE when the transistor 22 is in the saturated state is shown by line 27 in FIG.
And the gate leakage current IG2 in the non-saturated state
Is shown on line 28. From the graph of FIG. 5, it can be understood that the gate leakage current IG2 is larger when the transistor 22 is in the saturated state than when it is in the non-saturated state.

In the prior art, in order to solve such a problem, a circuit element such as a transistor which operates in a saturated state with a large amount of light emission as described above and the influence of the weak light emission should be prevented. -The circuit elements such as FETs are arranged at positions separated from each other in the same integrated circuit, so that it takes time and effort to design the integrated circuit elements and the influence of the weak light emission is eliminated. I can't. Therefore, there is a problem that the operational reliability of the integrated circuit device and the semiconductor device inside thereof is low.

(2) Influence of noise from the outside In the integrated circuit, a circuit operating with a high input impedance, such as the gate of the JFET, is affected by various noises generated in other operating parts. There is a case in which the influence is exerted and the required stable operation and output cannot be obtained. FIG. 11 shows an example of a part of an integrated circuit which can cause such a problem.

In the circuit of FIG. 11, an input amplifier 30 having a high input impedance using a J.FET 24 is arranged near the high frequency oscillation circuit 29 as an example. In the case of such an arrangement, high frequency electromagnetic noise or the like is generated in the high frequency oscillation circuit 29, and enters the input terminal of the input amplifier 30 via the capacitance or the conductor. Since the input terminal of the input amplifier 30 has a high input impedance, the input amplifier 30 is particularly susceptible to high frequency electromagnetic noise.

In order to prevent such a circuit malfunction due to the influence of external noise, conventionally, in an integrated circuit device including the circuit shown in FIG. 11 as an example, a wiring on which the integrated circuit device is mounted is mounted. A wiring pattern on the substrate, a metal plate, or the like is used to cover the periphery of the integrated circuit element or its back surface, particularly the high impedance portion as a center. In addition, the wiring pattern or metal plate used for coating is connected to the ground potential or another stable potential to electromagnetically shield the high impedance portion.

In such a conventional technique, there remains a problem that other circuit elements in the same integrated circuit cannot achieve the required stable operation and output due to the electromagnetic noise from the circuit elements in the integrated circuit. It is still done.

[0026]

Therefore, it is difficult to improve the operational reliability of the semiconductor circuit element in the integrated circuit in any of the above-mentioned prior arts. There is a problem that the operational reliability of the integrated circuit device including the same cannot be improved.

The present invention has been made in order to solve the above problems, and a semiconductor element capable of suppressing the generation of a gate leak current and improving the operational reliability,
It is an object of the present invention to provide an integrated circuit device capable of improving the operational reliability by preventing the transmission of noise from the internal components to the semiconductor element due to high frequency signals.

[0028]

The semiconductor device of the present invention comprises:
The semiconductor substrate is formed to have a PN junction, and the periphery is covered with a light-shielding material, whereby the above object can be achieved.

In the present invention, the light-shielding material may be a metal film.

The integrated circuit device of the present invention has a semiconductor substrate having a P
A semiconductor element having an N-junction and a circuit element which emits light during operation are provided, and at least one of the optical semiconductor element and the circuit element is covered with a light-shielding material. Therefore, the above object can be achieved.

In the present invention, the light-shielding material may be a metal film.

In the present invention, the semiconductor element may be a junction field effect transistor.

[0033]

According to the present invention, a semiconductor element is formed on a semiconductor substrate having a PN junction. This semiconductor element
The periphery is covered with a light shielding material. Therefore, it is possible to prevent light from entering the semiconductor element from the outside. When light is incident, the incident light causes the PN of the semiconductor element.
Carriers are excited at the junction and a leak current is generated. In the present invention, since the incidence of light is prevented, the generation of the leak current is prevented. This allows
The semiconductor device can achieve the designed performance,
The operational reliability can be improved.

Further, in the integrated circuit device of the present invention, the light-shielding material prevents the light from propagating to the outside of the circuit element even if the circuit element is accompanied by a light emission phenomenon when the circuit element operates. . When this light propagates from the circuit element to the outside, the propagated light excites carriers in the PN junction portion of the semiconductor element, and a leak current is generated. In the present invention, since the propagation of the light is prevented, the generation of the leak current is prevented. As a result, the semiconductor device can achieve the designed performance.
Therefore, the integrated circuit device including the semiconductor device can realize the designed performance and improve the operational reliability.

[0035]

The present invention will be described below with reference to examples.
1 to 7 show an embodiment of the present invention. FIG. 1 shows a JFET 3 which is a part of an integrated circuit element 31 according to an embodiment of the present invention.
2 is a plan view of FIG. 2, FIG. 2 is a cross-sectional view taken along section line X2-X2 of FIG. 1, and FIG. 3 is a circuit diagram showing a circuit example of the integrated circuit element 31.

The integrated circuit device 31 of this embodiment is realized as the photometric circuit 1 shown in FIG. The photometric circuit 1 includes a negative feedback type operational amplifier 2 and a photodiode 3 whose anode and cathode are connected to an inverting input terminal and a non-inverting input terminal of the operational amplifier 2. The operational amplifier 2 has J-FETs 32 and 33 according to an embodiment of the present invention in which the inverting input terminal and the non-inverting input terminal are respectively connected to the gates. Therefore, the operational amplifier 2 has a high input impedance. The diode 4 is connected to the negative feedback circuit of the operational amplifier 2, and the anode of the diode 4 is the operational amplifier 2
It is connected to the inverting input terminal of. The cathode of the photodiode 3 is connected to the positive electrode of the DC power supply 5 having the power supply voltage V0.

The operation of the photometric circuit 1 will be described below. The photometric circuit 1 is a circuit that logarithmically compresses the output current Ip, which is the light that has entered the photodiode 3 and is photoelectrically converted by the photodiode 3 and output, so that it can be easily processed in the integrated circuit. The photometric circuit 1 is used, for example, in a camera having an automatic exposure function, and is used as an integrated circuit for calculating and outputting an exposure value.

The J-FET 32 in the photometric circuit 1 has a structure as shown in FIGS. JF
The ET 32 is an N + region 35 formed in the P substrate 34.
A pair of P + regions 38 and 39 serving as a source and a drain, and a gate embedded in the P- region 37 and an N- region 36 on the N + region 35 and a P- region 37 on the N- region 36. And an N + region 40 that becomes

Over the substantially entire surface of the P substrate 34,
The interlayer film 41 is formed. In the interlayer film 41, the P
At positions corresponding to the + regions 38 and 39 and the N + region 40,
Through holes 45, 46 and 47 are formed respectively.
Further, a band-shaped groove 48 is formed in a region corresponding to the exposed region of the P substrate 34 which is exposed to the outside in a shape surrounding the N-region 36 of the J.FET 32. A source electrode 49, a drain electrode 50, and a gate electrode 51 are formed in each region that covers the through holes 45 to 47. Further, a band-shaped first light-shielding metal layer 42 is formed in a range covering the band-shaped groove 48. The through holes 45, 4
6, 47 depending on the source electrode 49 and the drain electrode 5
0, the gate electrode 51 and the P + regions 38, 39 and N +
The area 40 is electrically connected.

Due to the first light-shielding metal layer 42, light from the outside is exposed from the exposed region of the P substrate 34 to the P substrate 3 by the external light.
We prevent the situation that we invade in 4. The source electrode 4
An interlayer film 43 is formed by covering the drain electrode 50, the gate electrode 51, the first light-shielding metal layer 42, and the interlayer film 41. In the interlayer film 43, the band-shaped groove 4
The band-shaped grooves 52 are formed in the range corresponding to 8, respectively. The second light shielding metal layer 44 is formed so as to cover the band-shaped groove 52 and the area surrounded by the band-shaped groove 52. The second
The light shielding metal layers 42 and 44 are connected to a stable potential such as a ground potential as an example. The first and second light shielding metal layers 42 and 44
The material used in (1) is a material used for manufacturing a conductor pattern inside the integrated circuit element, such as Al, W, Au and Ti, and is formed in the same process as the manufacturing process of the conductor pattern. . The material is not limited to the above example.
Moreover, the film thickness is appropriately selected so as to realize light shielding for each material.

In the J-FET 32, the gate electrode 51
A current flows between the source electrode 49 and the drain electrode 50 by applying a predetermined potential to the.

An example in which such a J.FET 32 is used in the photometric circuit 1 shown in FIG. 3 will be described. FIG. 4 shows FIG.
3 is a perspective view showing a cross section of a part of the photometric circuit 1 shown in FIG.
In the circuit of FIG. 4, a PNP is provided near the JFET 32.
A type transistor 53 and an NPN type transistor 54 are arranged. The PNP transistor 53 is a P substrate 3
N + region 55 formed in 4 and N on the N + region 55
In the − region 56 and the N − region 56, P + serving as an emitter
A region 57, a P + region 58 serving as a collector formed in a shape surrounding the P + region 57, and an N + region 59 serving as a base are included. The P + regions 57, 58 and N +
An emitter electrode 61 and a collector electrode 62 are formed on the region 59.
And the base electrode 63 is formed.

The NPN transistor 54 is formed on the P substrate 34.
N + region 64 formed therein and N− on the N + region 64
It has a region 65, and a P + region 66 and an N + region 67 formed in the N− region 65 at positions separated from each other. An N + region 68 is formed in the P + region 66.
A base electrode 71, a collector electrode 70 and an emitter electrode 69 are formed on the P + region 66 and N + regions 67 and 68, respectively.

As described with reference to FIG. 10, when the transistors 53 and 54 are transistors operating in a saturated state, weak light emission is performed during operation. At this time,
As indicated by arrows B1 and B2 in FIG. 2, the weak light emission from the circuit that performs the weak light emission propagates through the interlayer films 41 and 43 and J
Reach the location where the FET 32 is formed. In the J-FET 32 of the present embodiment, the light is blocked by the first and second light shielding metal layers 42 and 44, and the P + regions 38 and 39, the N + region and the P exposed to the outside.
Invasion of the substrate 34 is prevented.

Therefore, the generation of the leak current at the PN junction portion described with reference to FIG. 9 is prevented. As a result, the J-FET 32 of the present embodiment can realize the designed performance with respect to the current value flowing between the source and the drain with respect to the gate input. In addition, operational reliability can be improved.

Further, in the photometric circuit 1 of this embodiment described with reference to FIG. 3, generation of the gate leak current IG2 in the J.FETs 32 and 33 is prevented. On the other hand, as described above, J-FETs 32 and 33
The reverse leakage current IG1 based on the structure is 1p
Very low, such as A or less. Therefore, as shown in FIG.
Compared with the case where faint light emission from 4 enters, it is about 50
It can be reduced by about%. Thereby, the gate leak current IG can be made sufficiently small to be negligible in the first expression. Therefore, from the first equation to the second
The equation can be approximately derived, and the second equation holds even in the range where the output current Ip is relatively small. This is the case when the amount of light incident on the photodiode 3 is relatively low. In the photometric circuit 1, even if the amount of the incident light is low, the photometric circuit 1 can realize accurate photometry, the photometric circuit 1 can realize the designed performance, and operational reliability. Can be significantly improved.

A case will be described below in which a high frequency oscillation circuit or the like is arranged near the J.FET 32 as described in the prior art with reference to FIG. First and second
As described above, the light shielding metal layers 42 and 44 are connected to the ground potential as an example. Therefore, even if the high-frequency oscillator circuit generates high-frequency noise, the J-FETs 32, 33
Are electromagnetically shielded by the first and second light-shielding metal layers 42 and 44, and are prevented from malfunctioning due to the high-frequency noise.

The first and second light shielding metal layers 42 and 44
Is formed using the material for manufacturing the conductor pattern inside the integrated circuit element as described above, and is formed in the same process as the manufacturing process of the conductor pattern. In order to manufacture the first and second light-shielding metal layers 42 and 44, it is only necessary to change the mask pattern when manufacturing the conductor pattern in the integrated circuit device. Therefore, the J-FETs 6 and 7 of this embodiment are
When manufacturing the photometric circuit 1 including
It can be manufactured without increasing the number of steps.

FIG. 6 is a plan view of the NPN transistor 54 which is a part of an integrated circuit device 31 according to another embodiment of the present invention, and FIG. 7 is a sectional view taken along the section line X7-X7 of FIG. is there.

The integrated circuit device 31 of this embodiment is realized as the photometric circuit 1 shown in FIG. Detailed re-explanation of the photometric circuit 1 is omitted. As described above, the transistor 54 in the photometric circuit 1 includes the N + region 64 formed in the P substrate 34 and the N− region 6 on the N + region 64.
5 and a P + region 66 and an N + region 67 respectively formed in the N- region 65 at positions separated from each other. An N + region 68 is formed in the P + region 66.

Almost the entire surface of the P substrate 34,
The interlayer film 72 is formed. In the interlayer film 72, the N
In the positions corresponding to the + regions 67 and 68 and the P + region 66,
Through holes 73, 74 and 75 are formed respectively.
Further, a band-shaped groove 76 is formed in a region corresponding to the exposed region of the P substrate 34 which is exposed to the outside in a shape surrounding the N − region 65 of the transistor 54. A collector electrode 77 is provided in each region covering the through holes 73 to 75.
An emitter electrode 78 and a base electrode 79 are formed.
In addition, a band-shaped first light-shielding metal layer 80 is formed in a range that covers the band-shaped groove 76. The through holes 73, 74 and 75 allow the collector electrode 77, the emitter electrode 78, the base electrode 79 and the N + regions 67 and 6 to be formed.
8 and the P + region 66 are electrically connected.

Due to the first light-shielding metal layer 80, light from the outside is exposed from the exposed area of the P substrate 34 to the P substrate 3 by the external light.
We prevent the situation that we invade in 4. The collector electrode 7
An interlayer film 81 is formed so as to cover 7, the emitter electrode 78, the base electrode 79, the first light-shielding metal layer 80, and the interlayer film 72. In the interlayer film 81, the band-shaped groove 7
The band-shaped groove 83 is formed in a range corresponding to 6. A second light shielding metal layer 82 is formed so as to cover the area surrounded by the band-shaped grooves 72, 83. The first and second light-shielding metal layers 8
0 and 82 are formed by the same material and manufacturing process as the first and second light shielding metal layers 42 and 44 in the first embodiment.

Photometric circuit 1 which is an integrated circuit element of this embodiment
In the above, even if light is generated when the transistor 54 that operates in the saturated state operates, the light is still generated by the transistor 5.
4 is blocked by the first and second light shielding metal layers 80 and 82. When the transistor 54 of this embodiment is used in the circuit of FIG. 4, when the light from the transistor 54 propagates from the transistor 54 into the integrated circuit, the propagated light causes the J · FE
At the PN junction portion of T32, 33, the gate leak current IG2 as described above is generated. In the present embodiment, since the propagation of the light is prevented, the generation of the gate leak current is prevented.

Therefore, in the photometric circuit 1 of this embodiment,
It is possible to achieve the same effect as the effect described in the above embodiment. Further, also in the manufacturing process of the photometric circuit 1, it is possible to achieve the same effects as those described in the above embodiment.

The semiconductor element according to the present invention is not limited to the J-FETs 32 and 33 in each of the above-described embodiments, but may be widely applied to semiconductor elements having a PN junction. Also, J
-The FETs 32 and 33 and the circuit elements that emit weak light to generate a gate leakage current in the J-FETs 32 and 33 are
The invention is not limited to the transistor 54 of the above-described embodiment, but can be widely applied to circuit elements that emit weak light.

[0056]

The following effects can be obtained by using the semiconductor element of the present invention. According to the present invention, the periphery of the semiconductor element formed on the semiconductor substrate is
It is covered with a light-shielding material to prevent light from entering the semiconductor element from the outside. Since the incidence of light is prevented, the generation of leak current is prevented in the semiconductor element. As a result, the semiconductor element can achieve the designed performance and the operational reliability can be improved.

The following effects can be obtained by using the integrated circuit device of the present invention. According to the invention, the circuit element is covered with a light-shielding material.
The light-shielding material prevents the light from propagating to the outside of the circuit element even if the circuit element is accompanied by a light emission phenomenon when the circuit element operates. This light prevents the generation of leakage current of semiconductor elements in the same integrated circuit. As a result, the semiconductor element can achieve the designed performance and the operational reliability can be improved.

[Brief description of drawings]

FIG. 1 is a plan view of a J-FET 32 according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the section line X2-X2 in FIG.

FIG. 3 is a block diagram of a photometric circuit 1 according to an embodiment of the present invention.

FIG. 4 is a sectional view of a part of the photometric circuit 1.

FIG. 5 is a graph illustrating the effect of this embodiment.

FIG. 6 is a plan view of a transistor 54 according to another embodiment of the present invention.

7 is a cross-sectional view taken along the section line X7-X7 in FIG.

FIG. 8 is a cross-sectional view of a conventional integrated circuit.

FIG. 9 is a cross-sectional view of another conventional integrated circuit.

FIG. 10 is a circuit diagram illustrating a problem of a conventional example.

FIG. 11 is a block diagram illustrating another problem of the conventional example.

[Explanation of symbols]

 31 integrated circuit element 32, 33 J-FET 34 P substrate 35, 55, 64 N + region 36, 56, 65 N- region 37, 57 P- region 38, 39, 58, 59, 66 P + region 40, 67, 68 N + Region 42, 80 First light-shielding metal layer 44, 82 Second light-shielding metal layer

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI Technical indication location H01L 29/808 27/095 31/10 7376-4M H01L 29/80 E 8422-4M 31/10 A

Claims (5)

[Claims] 1. A semiconductor element formed on a semiconductor substrate having a PN junction, the periphery of which is covered with a light-shielding material. 2. The semiconductor element according to claim 1, wherein the light shielding material is a metal film. 3. A semiconductor substrate having a semiconductor element formed with a PN junction, and a circuit element accompanied by a light emission phenomenon during operation, wherein at least one of the optical semiconductor element and the circuit element is provided. , Integrated circuit device whose periphery is covered with a light-shielding material 4. The integrated circuit device according to claim 3, wherein the light shielding material is a metal film. 5. The integrated circuit device according to claim 3, wherein the semiconductor element is a junction field effect transistor.