JPH06314819A - Light emitting and receiving diode and its manufacture - Google Patents

Abstract

PURPOSE:To improve photosensitivity of a light emitting diode when functioning as a photodetector. CONSTITUTION:A light emitting and receiving region 40 is made a region for one picture element, and a shallow p-n junction 40a having light receiving function and a deep p-n junction 40b having light emitting function are provided to the region 40 in mutual contact. The shallow p-n junction 40a is provided by snaking to a periphery of the light emitting and receiving region 40. Since an area of the shallow p-n junction 40a in the light emitting and receiving region 40 f one picture element is thereby increased, the purpose can be attained. When the p-n junctions 40a, 40b are formed, a layer insulation film 46 which also functions as a diffusion mask is formed on a first semiconductor layer 42 and a window 46a whose periphery snakes is formed in the film 46. A second semiconductor layer 44 is formed in the first semiconductor layer 42 by thermally diffusing impurities through the window 46a. Since impurities are diffused also in a direction along a surface of the first semiconductor layer 42, a snaking shallow p-n junction is formed below the layer insulation film 46 of a window periphery.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for use in constructing a light emitting / receiving diode which has both a light receiving function and a light emitting function, and particularly a diode array used for both an image sensor and an electrophotographic exposure light source. The present invention relates to a light emitting / receiving diode and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, electrophotographic printing apparatuses have been used in copying machines, printers and the like. In this method, the photosensitive surface of the photosensitive drum is uniformly charged by a charger. Then, the photosensitive surface is selectively exposed to form an electrostatic latent image corresponding to the image to be recorded. Hitting the selective exposure of the photosensitive surface, for example, irradiation with exposure light source laser or a light emitting diode (L ight E mitting D iode, hereinafter LED) to the sensitized surface with on-off control for each pixel the light emission.
Alternatively, a fluorescent lamp or a cold cathode tube is used as the exposure light source, and light from the light source is applied to the photosensitive surface through the liquid crystal shutter to open and close the liquid crystal shutter in pixel units. In the exposed portion of the photosensitive surface, the charge is neutralized by a photoelectric phenomenon, and in the unexposed portion, the charge is not neutralized and remains as it is, so that an electrostatic latent image is formed. Next, the charged toner is sprinkled on the photosensitive surface. The toner is selectively adsorbed on the photosensitive surface of the portion charged with the opposite polarity, and as a result, a toner image corresponding to the recording target image is formed. Then, the toner image is transferred onto the recording paper by the transfer device. After that, the toner image is fixed on the recording paper, and the printing of the image to be recorded is completed.

A printing apparatus using an LED as an exposure light source for forming an electrostatic latent image has an advantage that printing can be performed at high speed and high resolution, and such an apparatus is disclosed in, for example, JP-A-56-56.
Some are disclosed in Japanese Patent No. 30154. Further, in order to reduce the cost and the size of the device, a device using the LED as both an exposure light source for forming an electrostatic latent image and an image sensor for reading an image (hereinafter referred to as an integrated printing / reading device) has been proposed. . An example of such an apparatus is disclosed in Japanese Patent Laid-Open No. 58-157252.

FIG. 26 is a perspective view of an essential part showing an example of the structure of the printing / reading integrated apparatus, showing a state of reading a document image to be recorded. In the figure, 10 is a wiring board, and 12 and 14 are LED arrays and control ICs provided on the wiring board 10. Multiple LEDs, for example 64 LEDs
Are linearly arrayed in the array direction A and integrated,
The LED array 12 is composed of D. And each LED
A plurality of LED arrays 12 are arranged in a line so that the LEDs of the array 12 are arranged in a straight line. Each LED array 12 is provided with a control IC 14, and the corresponding LED array 1
2 and the control IC 14 are electrically connected.

Reference numeral 16 is an original document positioned at a predetermined position on a transparent original document plate (not shown), and 18 and 20 are a converging lens array and an illumination light source provided between the original document plate and the LED array 12. Show. Arranging a plurality of converging lenses in the direction A
Are linearly arranged on the holder 22 and are fixed to the holder 22, and the converging lens array 18 is constituted by these converging lenses. Further, the converging lens array 18 and the LED array 12 are opposed to each other so that their optical axes coincide with each other, and the converging lens array 1
Illumination light sources 20 are provided on both sides of 8.

When reading an original image, the illumination light source 20 is used.
The original light 16 is irradiated with the light L1 from the document 16 and the reflected light L2 is incident on the LED array 12 through the converging lens array 18. The reflected light L2 has a light intensity corresponding to the density of the document 16 and forms a document image. On the other hand, since the LED is a diode having a pn junction, the pn junction is applied with a reverse voltage applied.
When the reflected light L2 is incident on the junction, electrons or holes in an amount proportional to the reflected light intensity are excited and move in the depletion layer of the pn junction. As a result, a current flows through the pn junction, and the original image can be converted into an electric signal by detecting this current.

Reference numeral 24 denotes a light shielding plate provided between the illumination light source 20 and the LED array 12. The light shielding plate 24 is arranged so that light other than the light L2 from the converging lens array 18 does not enter the LED array 12.

27 (A) and 27 (B) are a plan view and a sectional view schematically showing the structure of the main part of the LED array, and FIG. 27 (B) is taken along line XXVIIB-XXVIIB in FIG. 27 (A). A cross section taken along is shown. The LED 26 includes an n layer 28 and a p layer 30 that form a pn junction, and an n layer 28 and a p layer 30.
An n-side electrode 32 and a p-side electrode 34 that are electrically connected to each other, and an interlayer insulating film 36 having a window 36a that electrically separates the n-layer 28 and the p-side electrode 34 and exposes the p-layer 30.

The LED 26 is manufactured, for example, as follows. First, an n-GaAs _X P _1-X wafer is prepared as the n layer 28, and the interlayer insulating film 36 is laminated on this layer 28.
The interlayer insulating film 36 is a transparent film made of SiO, SiN or SiON. After that, a window 36a is formed in the interlayer insulating film 36, and the n layer 28 in the p layer formation region is exposed through the window 36a. Next, using the sealed tube method as an impurity introduction technique,
Zn is thermally diffused into the n-layer 28 through the window 36a. Z
A p layer 30 is formed in the n diffusion region. Interlayer insulation film 36
Has a film thickness or a material that does not transmit Zn and acts as a diffusion mask, but Zn diffuses not only in the direction perpendicular to the wafer surface but also in the direction parallel to the wafer surface. Therefore, p layer 3
0 is formed not only in the inner region of the window 36a but also under the interlayer insulating film 36 at the periphery of the window 36a. Here, if the depth from the wafer surface to the pn junction interface is referred to as the pn junction depth, a pn junction 38a having a deep pn junction depth is formed in the region inside the window 36a, and the pn junction depth is shallow at the periphery of the window 36a. pn
The joint 38b is formed. Then, the p-side electrode 34 is formed on the p-layer 30. Further, an n-side electrode 32 is formed on the opposite side of the n-layer 28 from the p-layer 30.

Next, the design of the pn junction depth will be described with reference to FIG. FIG. 28 is a diagram showing the relationship between the pn junction depth of an LED and the light emission intensity. In the figure, the pn junction depth (μm) is plotted on the horizontal axis and the emission intensity (dimensionless) relative to the maximum emission intensity of 1 is plotted on the vertical axis.
An example in which an LED having an emission wavelength of 740 μm is manufactured using _0.8 P _0.2 is shown.

In the example shown in the figure, the pn junction depth is about 7.5 μm.
The light emission output intensity becomes maximum when the depth is around m, and the light emission output intensity decreases as the pn junction depth becomes shallower or deeper. This depends on the following reasons. That is, the surface layer of the p layer 30 has many impurity levels and defect levels, and therefore, as the pn junction depth becomes shallower, the occupation ratio of this level in the depletion layer that contributes to light emission increases. Further, the light generated in the depletion layer is absorbed by the p layer 30 while propagating through the p layer 30, and thus the light absorption amount increases as the pn junction depth increases.

In general, the emission wavelength of the LED 26 is 660 to 780 μm, which gives a large sensitivity to the photosensitive drum.
However, in this case, the pn junction depth is 5 to 10 μm.
By so doing, a sufficiently large emission output intensity can be obtained in practical use.

[0013]

On the other hand, when the photoelectric conversion characteristics when the LED 26 is used as a light receiving element are experimentally examined, the following is found. FIG. 29 is a diagram showing the results of this experiment. In the figure, the experimental results are shown in FIG.
7 shows a cross-sectional structure of a main part of the LED 26 taken along line XXVIIB-XXVIIB in FIG. The position X in the direction along the line XXVIIB-XXVIIB is taken as the horizontal axis of the experimental result, and the scanning light is taken as the p-layer 3 at the position X.
The vertical axis of the experimental results shows the photoelectric conversion current generated when 0 is irradiated. In the experiment, the emission wavelength was 740n
Using the LED 26 designed to be m, scanning light having a spot size sufficiently smaller than that of the p layer 30 was irradiated from a direction perpendicular to the p layer 30. Then, the wavelength of the scanning light is set to 550
And 740 nm, and scanning light is XXVIIB-XX for each wavelength.
The photoelectric conversion current at the position X was measured by scanning along the VIIB line. The solid and dotted curves in the figure show the scanning light wavelength of 5
The experimental results are shown at 50 and 740 nm.

As can be understood from the figure, the wavelength of the scanning light is in the visible range suitable for reading the original image, for example, 550 nm.
In such a case, the photoelectric conversion current is large in the pn junction 38b having a shallow pn junction depth and small in the pn junction 38a having a deep pn junction depth. On the other hand, when the wavelength of the scanning light is set to a wavelength longer than the wavelength in the visible range, for example, 740 nm, the photoelectric conversion current has a shallow pn junction 38b and a deep pn junction.
It becomes large at both joints 38a.

The reason for this is considered as follows. That is, since the visible light has a short wavelength, it can reach only a relatively shallow region of the p layer 30, and therefore the amount of light that reaches the deep pn junction 38a is extremely small. As a result, in the case of visible light, the amount of photoelectric conversion in the deep pn junction 38a decreases. On the other hand, the light having a wavelength longer than that of visible light is p
Can reach deeper regions of the deep pn junction 38
A greater amount of light reaches a. As a result, the amount of photoelectric conversion in the deep pn junction 38a increases when the light has a long wavelength.

This point will be described with reference to FIG.
FIG. 30 shows how the absorption coefficient of GaAs _0.8 P _0.2 changes with the wavelength of incident light. GaA on the horizontal axis of the figure
The wavelength (nm) of light incident on s _0.8 P _0.2 is shown, and the vertical axis shows the absorption coefficient (cm ⁻¹ ) of GaAs _0.8 P _0.2 in logarithmic form. Here, attention is paid to GaAs _0.8 P _0.2 which is usually used in manufacturing the LED 26 having an emission wavelength of 740 nm.

The light intensity I of the incident light that has traveled in GaAs _0.8 P _0.2 by a distance x is 37% of the light intensity I ₀ at the time of incidence.
If it is assumed that the distance is reduced to (I = (1 / e) · I ₀ ), then the distance x at this time can be calculated using the absorption coefficient.

Ga for incident light with a wavelength of about 550 nm
The absorption coefficient of As _0.8 P _0.2 is 1 × 10 ^{4 to} 3 × 10 ⁴ c
It is about m ⁻¹ (see FIG. 30), and when the distance x in this case is calculated, the distance x is about 0.3 to 0.7 μm. In addition, GaAs _0.8 P for incident light with a wavelength of about 740 nm
The absorption coefficient of _0.2 is about 1 × 10 ³ to 2 × 10 ³ cm ⁻¹ (see FIG. 30). When the distance x in this case is calculated, the distance x is about 5 to 10 μm. As can be understood from these, visible light near 550 nm is GaA.
Only the extremely shallow surface layer of s _0.8 P _0.2 can be reached. Therefore, if I _MIN. = (1 / e) · I ₀ is considered as a rough guideline for the lower limit (I _MIN. ) Of the incident light intensity I capable of photoelectric conversion, visible light near 550 nm is GaAs.
Only the depletion layer existing within a depth of _0.3 to 0.7 μm from the _0.8 P _0.2 surface layer is subjected to photoelectric conversion.

As described above, the shallow pn junction 38b plays a role of the light receiving function of the LED 26, but in the conventional LED 26, the shallow pn junction 38b is formed only under the interlayer insulating film 36 around the window 36a. Moreover, a linear shallow pn
The joint 38b is only formed in a rectangular shape. Therefore, since the shallow pn junction 38b is narrow, it is difficult to increase the light receiving sensitivity.

An object of the present invention is to solve the above-mentioned conventional problems, and to provide a light emitting / receiving diode having both a light receiving function and a light emitting function, which has a higher light receiving sensitivity than the conventional one, and a manufacturing method thereof. To do.

[0021]

In order to achieve this object, in the light emitting and receiving diode of the first invention, a shallow pn junction for photoelectric conversion and a deep pn junction for light emission are placed in contact with each other in the light receiving and emitting region. In the light emitting and receiving diode provided, the width of the shallow pn junction is increased with respect to the width of the deep pn junction.

According to the first aspect of the present invention, comparing the width of the deep pn junction to the same level as the conventional one, the light receiving / emitting region becomes wider than the conventional one by the increment of the shallow pn junction, but the light receiving sensitivity of the light receiving / emitting diode is higher than the conventional one. Can be increased. Alternatively, if the area of the light receiving / emitting area is comparable to that of the conventional one, the shallow pn
Although the width of the pn junction, which is deeper by the increment of the junction, is reduced as compared with the conventional case, the light receiving sensitivity of the light receiving and emitting diode can be increased compared with the conventional case. It is preferable to increase the width of the shallow pn junction while reducing the width of the deep pn junction within a range where a practically satisfactory emission output intensity can be obtained.

The light emitting and receiving diode of the second invention is a preferred embodiment of the first invention, and is characterized in that a shallow pn junction is provided along the periphery of the light receiving and emitting region in a meandering manner.

According to the second invention, since the shallow pn junction is meandered, the area of the shallow pn junction can be increased as compared with the conventional case.

The light emitting and receiving diode of the third invention is a preferred embodiment of the first invention, and is characterized in that a shallow pn junction is provided at the peripheral edge of the light receiving and emitting area and the area inside the peripheral edge of the light receiving and emitting area. And

According to the third aspect of the invention, since the shallow pn junction is provided also in the region inside the peripheral edge of the light emitting / receiving region, the shallow pn junction is provided.
The width of the joint can be increased more than before. Further, since the shallow pn junction is provided in the area inside the peripheral edge of the light receiving / emitting area, the light receiving amount of the light receiving / emitting area can be more accurately compared to the conventional case where the shallow pn junction is provided only in the peripheral edge of the light receiving / emitting area. Can be detected.

In the method for manufacturing a light emitting and receiving diode according to the fourth aspect of the present invention, in manufacturing the light receiving and emitting diode according to the second aspect of the present invention, a step of forming an interlayer insulating film also serving as an impurity introduction mask on the first semiconductor layer, and an interlayer insulating A step of forming a window having a meandering window periphery in the film, and a second semiconductor layer for forming a shallow pn junction and a deep pn junction by thermally diffusing impurities in the first semiconductor layer through the window of the interlayer insulating film And a step of forming.

According to the fourth invention, the impurities are thermally diffused through the window of the interlayer insulating film, whereby the deep pn junction and the shallow pn junction can be formed in parallel. Deep pn
The junction is formed in the window inner region of the interlayer insulating film, and the shallow pn junction is formed below the interlayer insulating film at the window periphery. Since the window edge is meandered, a meandering shallow pn junction can be formed, and thus the width of the shallow pn junction can be increased. Moreover, a meandering shallow pn junction can be formed by merely making a simple design change in which the window periphery of the interlayer insulating film also serving as an impurity introduction mask is meandered. Therefore, the area of the shallow pn junction can be increased while avoiding the complication of the manufacturing process.

In carrying out the fourth invention, the interlayer insulating film in the portion covering the shallow pn junction may be selectively removed after the thermal diffusion, but this selective removal is omitted and the manufacturing process is simplified. In order to realize this, it is preferable that the interlayer insulating film is a film transparent to the light to be received.

In the method of manufacturing a light emitting and receiving diode of the fifth invention, in manufacturing the light receiving and emitting diode of the third invention, a step of forming an interlayer insulating film also serving as an impurity introduction mask on the first semiconductor layer, and an interlayer insulating film. A step of forming a window in the film; a step of forming an impurity blocking film on the first semiconductor layer in the window inner region of the interlayer insulating film; and a step of forming impurities in the first semiconductor layer through the window of the interlayer insulating film and the impurity blocking film. Thermal diffusion to form a second semiconductor layer for forming a shallow pn junction and a deep pn junction.

According to the fifth aspect of the present invention, the deep pn junction and the shallow pn junction can be formed in parallel by thermally diffusing the impurities through the window of the interlayer insulating film and the impurity blocking film. The deep pn junction is formed in a region inside the window of the interlayer insulating film, where the impurity blocking film is not formed, and the shallow pn junction is formed below the interlayer insulating film and the impurity blocking film at the periphery of the window. It

In carrying out the fifth invention, the window formation of the interlayer insulating film and the formation of the impurity blocking film may be carried out separately,
In order to simplify the manufacturing process, in parallel with forming the window of the interlayer insulating film, the interlayer insulating film in the window inner region is etched into an arbitrary suitable shape, and the processed interlayer insulating film is used as an impurity blocking film. It is preferably used.

In carrying out the fifth aspect of the invention, the interlayer insulating film and the impurity blocking film in the portion covering the shallow pn junction may be selectively removed after the thermal diffusion. In order to omit the process and simplify the manufacturing process, it is preferable to make the interlayer insulating film and the impurity blocking film transparent to the light to be received.

In the method of manufacturing a light emitting and receiving diode of the sixth invention, in manufacturing the light receiving and emitting diode of the third invention, a step of forming a first impurity introduction mask on the first semiconductor layer, and a first impurity introduction mask. Forming a first window on the
A deep pn is formed by introducing impurities into the first semiconductor layer through the first window.
Forming a second semiconductor layer for forming a junction, and then
A step of removing the first impurity introduction mask, a step of forming an interlayer insulating film also serving as a second impurity introduction mask on the first and second semiconductor layers, and a peripheral edge of the second semiconductor layer for forming a deep pn junction A step of forming a second window in the interlayer insulating film to expose the first semiconductor layer in a region adjacent to, and a step of forming a shallow pn junction by introducing impurities into the first semiconductor layer through the second window. And a step of forming two semiconductor layers. As the impurity introduction technique, thermal diffusion, ion implantation or any other suitable technique can be used.

According to the sixth aspect, the width of the shallow pn junction can be increased as the first semiconductor layer exposed through the second window is expanded.

In the method of manufacturing a light receiving and emitting diode according to the seventh invention, in manufacturing the light receiving and emitting diode according to the third invention, the lower interlayer insulating film and the upper interlayer insulating film also serving as impurity introduction masks are sequentially provided in the first semiconductor. Forming a first window on the upper interlayer insulating film, and leaving a part of the lower interlayer insulating film on the inner region of the first window to form a lower interlayer insulating film on the region. A step of forming a second window, and a step of introducing an impurity into the first semiconductor layer through the first window and the second window to form a second semiconductor layer for forming a shallow pn junction and a deep pn junction. It is characterized by comprising. As the impurity introduction technique, thermal diffusion, ion implantation or any other suitable technique can be used.

According to the seventh aspect of the invention, the introduction depth of impurities is made shallower by increasing the film thickness of the lower interlayer insulating film or by arbitrarily selecting the material of the lower interlayer insulating film. You can Therefore, by introducing the impurities through the first and second windows, a deep pn junction is formed in the inner region of the second window which is not covered with the lower interlayer insulating film, while being covered with the lower interlayer insulating film. A shallow pn junction can be formed in the region inside the first window. Moreover, the width of the shallow pn junction can be increased as the lower interlayer insulating film exposed through the second window is expanded.

In the method of manufacturing a light emitting and receiving diode according to the eighth aspect of the present invention, in manufacturing the light receiving and emitting diode according to the third aspect of the present invention, a step of forming an interlayer insulating film also serving as an impurity introduction mask on the first semiconductor layer, and an interlayer insulating film. A step of forming a window in the film, a step of introducing an impurity into the first semiconductor layer through the window of the interlayer insulating film to form a second semiconductor layer for forming a deep pn junction, and a step of partially forming the second semiconductor layer. A step of selectively covering the second semiconductor layer with the etching prevention film, and partially etching the second semiconductor layer to reduce the layer thickness of the second semiconductor layer to a shallow p
and a step of forming a second semiconductor layer having a thin layer thickness for forming an n-junction.

According to the eighth aspect of the invention, as the area of the second semiconductor layer not covered with the etching prevention film is expanded, the shallow p
The width of the n-junction can be increased.

[0040]

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the drawings are merely schematic representations so that the invention can be understood, and therefore the invention is not limited to the illustrated examples.

First, an embodiment of the second invention will be described as a preferred embodiment of the first invention. 1 and 2 are a plan view and a sectional view schematically showing the configuration of an embodiment of the second invention,
FIG. 2 shows a cross section taken along line II-II in FIG.

In the light receiving and emitting diode of this embodiment, a shallow pn junction 40a for photoelectric conversion and a deep pn junction 40b for light emission are provided in contact with each other in the light receiving and emitting region 40, and a shallow pn junction with respect to the width of the deep pn junction 40b is provided. The width of the joint 40a is increased.

In this embodiment, the light emitting / receiving area 40 is set to the pixel 1
The area is to receive and emit light for each piece. And shallow p
By providing the n-junction 40a meandering along the periphery of the light receiving / emitting region 40, the area of the shallow pn junction 40a in the light receiving / emitting region 40 for one pixel is increased. Shallow pn junction 4
0a has a photoelectric conversion function, and the deep pn junction 40b has a light emission function.

The second semiconductor layer 44, eg, p-Ga, is formed on the surface layer on one side of the first semiconductor layer 42, eg, n-GaAsP substrate.
An AsP layer is provided, and p is formed by these semiconductor layers 42 and 44.
The n-junctions 40a and 40b are formed. Then, the interlayer insulating film 46 and the p-side electrode 48 are sequentially provided on the surface layer on one side of the first semiconductor layer 42. The p-side electrode 48 and the second semiconductor layer 44 are electrically connected through the window 46a of the interlayer insulating film 46. The interlayer insulating film 46 is a film having a one-layer structure, such as a SiN film or S.
The film is an iO film or a SiON film, or a film having a multi-layered structure, for example, a two-layered film composed of a SiN film and a SiON film sequentially provided on the first semiconductor layer 42. The p-side electrode 48 is an Al electrode. Then, on the other side of the first semiconductor layer 42, this layer 42
An n-side electrode 50 that is electrically connected to is provided.

Next, a manufacturing process of the light emitting / receiving diode of FIG. 1 will be described as an embodiment of the fourth invention. FIG. 3 (A)-
(C) is a sectional view schematically showing a main manufacturing process step of the fourth invention, and each drawing of FIG. 3 shows a section corresponding to the section of FIG. 2.

First, the inter-layer insulation film 46 also serving as an impurity introduction mask is formed on the first semiconductor layer 42. In this embodiment, an n-GaAs _0.8 P _0.2 substrate is prepared as the first semiconductor layer 42 in order to set the emission wavelength of the light emitting / receiving diode to a wavelength at which a large sensitivity is obtained with respect to the photosensitive drum, for example, a wavelength of about 740 nm. . Then, an interlayer insulating film 46 that is substantially impermeable to impurities is stacked on this layer 42 (FIG. 3A). The interlayer insulating film 46 is a film that is transparent to light to be received, for example, visible light having a wavelength of about 550 nm. As such an interlayer insulating film 42, a SiN film or SiO 2 is used.
A film or a SiON film is laminated. The interlayer insulating film 42 may be either a single-layer structure film or a multi-layer structure film, but here it is a single-layer structure film.

Next, a window 46a is formed in the inter-layer insulation film 46 with its window edge meandering. In this embodiment, a photolithography and etching technique is used to selectively remove the interlayer insulating film 46 in the window formation planned region 51 to form a window 46a (FIG. 3).
(B)). The periphery of the window 46a is meandered in a polygonal line or a curved line (see FIG. 1). In addition, the first semiconductor layer 42 in the window formation planned region 51 is exposed through the window 46a.

Next, the interlayer insulating film 4 is formed on the first semiconductor layer 42.
The impurities are selectively thermally diffused through the window 46a of No. 6,
A second semiconductor layer 44 for forming the shallow pn junction 40a and the deep pn junction 40b is formed. In this example,
Zn is diffused as an impurity to form a deep pn junction 40b in the first semiconductor layer 42 in the window formation region 51 exposed through the window 46a, and a shallow pn junction 40a is formed below the interlayer insulating film 46 at the periphery of the window 46a. To form (Fig. 3
(C)).

According to the thermal diffusion, impurities are contained in the first semiconductor layer 4
2 is diffused not only in the direction perpendicular to the surface but also in the direction along the surface of the first semiconductor layer 42. Therefore, even if the interlayer insulating film 46 does not transmit the impurities, the impurities can be diffused at the periphery of the window 46a.
It can be diffused to the lower side. This interlayer insulating film 46
The diffusion depth of impurities on the lower side becomes shallower as the distance from the window 46a increases. Therefore, even if diffusion is performed by setting diffusion conditions such as diffusion time and diffusion temperature so that the diffusion depth in the first semiconductor layer 42 exposed from the window 46 becomes deep,
The diffusion depth below the interlayer insulating film 46 can be made shallow. Therefore, the pn junction 40a having a shallow junction depth can be formed in parallel with the formation of the deep pn junction 40b having a distance (junction depth) from the surface layer of the first semiconductor layer 42 to the pn junction interface.

As the first semiconductor layer 42, n-GaAs _0.8
When the P _0.2 substrate is used, the emission output intensity of the light emitting and receiving diode can be increased by forming the deep pn junction 40b having a junction depth of about 5 to 10 μm.
For visible light with a wavelength of about 550 nm, the shallow pn junction 40 has a junction depth of, for example, about 0.3 to 0.7 μm or less.
In a, photoelectric conversion can be efficiently performed.

Next, p, which is electrically connected to the second semiconductor layer 44, is formed.
The side electrode 48 is formed. Further, an n-side electrode 50 electrically connected to the first semiconductor layer 42 is formed to complete a light emitting / receiving diode (see FIGS. 1 and 2).

According to this embodiment, the width of the shallow pn junction 40a can be increased only by making a simple design change in which the window periphery of the interlayer insulating film 46 also serving as an impurity introduction mask is meandered. Further, since the interlayer insulating film 46 is a film transparent to the light to be received, the shallow pn junction 40 is formed.
The step of removing the interlayer insulating film 46 in the portion covering a can be omitted. Moreover, since the shallow pn junction 40a and the deep pn junction 40b can be formed in parallel by thermal diffusion, the manufacturing process can be simplified, and the shallow pn junction 40a can be increased while suppressing an increase in manufacturing cost.

FIGS. 4A and 4B are sectional views for explaining the minimum junction depth J _m of the shallow pn junction.
A cross section taken along line IV-IV is shown.

The shallow pn junction 40a is formed by diffusion of impurities in the direction along the surface of the first semiconductor layer 42 (hereinafter referred to as side diffusion). Therefore, if the width W of the interlayer insulating film 46 is too narrow, the minimum junction depth J _{m of the} shallow pn junction 40a becomes deep, and photoelectric conversion cannot be performed efficiently.
The width W is the distance between the side wall surfaces 46a1 and 46a2 of the interlayer insulating film 46 (these side wall surfaces are also the wall surface of the window 46).

Here, the diffusion distance of impurities side-diffused from one side wall surface 46a1 to the lower side of the interlayer insulating film 46 is J _S1 , and the diffusion distance of impurities side-diffused from the other side wall surface 46a2 to the lower side of the interlayer insulating film 46. The distance is expressed as J _S2 . As the width W becomes smaller than the sum of the diffusion distances J _S1 and J _S2 , the overlapping portion of the impurity diffusion regions formed by the side diffusion from the one and the other side wall surfaces 46a1 and 46a2 becomes larger, and as a result, the minimum The junction depth J _m becomes deeper (FIG. 4 (B)). When the received light wavelength is around 550 nm, the junction depth is 0.3 to 0.
Photoelectric conversion can be efficiently performed in the shallow pn junction 40a of about 7 μm or less. In this case, the minimum junction depth J
_The width W may be set so that _m is 0.3 to 0.7 μm or less.

On the other hand, when the width W is equal to or larger than the sum of the diffusion distances J _S1 and J _S2 , the shallow pn junction 4
The minimum junction depth J _m of 0a may be substantially zero (Fig. 4 (A)). A region L where the shallow pn junction 40a has a junction depth of 0.3 to 0.7 μm or less (in FIG. 4A,
A region surrounded by a dotted circle) is a linear region having a small width in the direction Y intersecting with the sidewall surface of the interlayer insulating film 46. However, by forming the shallow pn junction 40a in a meandering manner, the total length of the shallow pn junction 40a can be increased, and thus the width of the shallow pn junction 40a can be made wider than in the conventional case.

When Zn is thermally diffused in GaAsP, the diffusion distances J _S1 and J _S2 are the diffusion distance (diffusion depth) J _d of impurities in the direction perpendicular to the surface of the first semiconductor layer 42.
It is empirically known to be about 1.3 times. As described above, when GaAs _0.8 P _0.2 is used, in order to increase the emission output intensity, the diffusion depth J _d is 5 to 10 μm.
The deep pn junction 40b may be formed. Therefore, if the diffusion depth J _d is, for example, 5 μm, the side diffusion distances J _S1 and J _S2 are about 6.5 μm.

Next, the first embodiment of the third invention will be described as a preferred embodiment of the first invention. 5 and 6 are a plan view and a sectional view schematically showing the configuration of the first embodiment of the third invention, and FIG. 6 shows a section taken along line VI-VI in FIG.

The light emitting and receiving diode of this embodiment is provided with a shallow pn junction 52a for photoelectric conversion and a deep pn junction 52b for light emission in contact with each other in the light receiving and emitting region 52, and a shallow pn with respect to the width of the deep pn junction 52b. The width of the joint 52a is increased.

In this embodiment, the light receiving / emitting area 52 is set to the pixel 1
It is an area for receiving and emitting light for each piece. By providing the shallow pn junction 52a on the peripheral edge s of the light receiving / emitting area 52 and the area t inside the peripheral edge t, the area of the shallow pn junction 52a in the light receiving / emitting area 52 for one pixel is increased. The shallow pn junction 52a has a photoelectric conversion function, and the deep pn junction 52b has a light emitting function.

The first semiconductor layer 54 and the second semiconductor layer 56 form pn junctions 52a and 52b. The first semiconductor layer 54 is an n-GaAsP substrate, and the second semiconductor layer 56 is a p-GaAsP layer. The second semiconductor layer 56 is provided on the surface layer on one side of the first semiconductor layer 54, and the interlayer insulating film 58 and the p-side electrode 60 are sequentially provided on the surface layer on the one side. The interlayer insulating film 58 has a window 58a that exposes the second semiconductor layer 56, and electrically connects the p-side electrode 60 and the second semiconductor layer 56 through the window 58a. In addition, the first semiconductor layer 54
An n-side electrode 62 electrically connected to this layer 54 is provided on the other side of the.

Next, as a fifth embodiment of the invention, a manufacturing process of the light emitting / receiving diode of FIG. 4 will be described. FIG. 7 (A)-
FIG. 7C is a sectional view schematically showing a main manufacturing process step of the fifth invention, and each drawing of FIG. 7 shows a section corresponding to the section of FIG.

First, an interlayer insulating film 58 which also serves as an impurity introduction mask is formed on the first semiconductor layer 54. In this embodiment, an n-GaAs _0.8 P _0.2 substrate is prepared as the first semiconductor layer 54, and an interlayer insulating film 58 that is substantially impermeable to impurities is laminated on this layer 54 (FIG. 7A). As the interlayer insulating film 58, a SiN film, a SiO film or a SiON film is laminated. The interlayer insulating film 58 may be either a single-layer structure film or a multi-layer structure film, but here it is a single-layer structure film.

Next, a window 58a is formed in the interlayer insulating film 58, and the first semiconductor layer 5 in the inner region 62 of this window 58a is formed.
An impurity blocking film 64 is formed on the film 4. In this example,
By selectively etching the interlayer insulating film 58 in the window formation planned region 66 using photolithography and etching techniques, the formation of the window 58a and the formation of the impurity blocking film 64 are performed in parallel (FIG. 7A). (FIG. 7B). On this occasion,
The interlayer insulating film 58 in the window formation region 66 is etched so as to partially remain, and the impurity blocking film 64 made of the remaining portion of the interlayer insulating film 58 is formed. By performing the etching in this manner, the window 58a exposing the first semiconductor layer 54 in the window formation scheduled region 66 and the impurity blocking film 64 located in the inner region 62 of the window 58a can be formed in parallel.

Next, an interlayer insulating film 58 is formed on the first semiconductor layer 54.
The impurity is thermally diffused through the window 58a and the impurity blocking film 64 to form the second semiconductor layer 56 for forming the shallow pn junction 52a and the deep pn junction 52b. In this embodiment, Zn is diffused as an impurity and a deep pn junction 52 is formed.
b is formed in the first semiconductor layer 54 exposed from the window 58a without being covered with the impurity blocking film 64, and the shallow pn junction 52a is formed below the interlayer insulating film 64 and below the interlayer insulating film 58 at the periphery of the window 58a. To form.

Next, p, which is electrically connected to the second semiconductor layer 56, is formed.
The side electrode 60 is formed. Further, an n-side electrode 62 electrically connected to the first semiconductor layer 54 is formed to complete a light emitting / receiving diode (FIGS. 5 and 6).

According to this embodiment, the width of the shallow pn junction 52a can be reduced by simply changing the design of the etching mask used for forming the window 58a and the impurity blocking film 64 by etching the interlayer insulating film 58. Can be increased. Further, since the interlayer insulating film 58 is formed as a film transparent to light to be received and the impurity blocking film 64 is formed using this interlayer insulating film 58, the interlayer insulating film 58 and the impurity blocking film 64 covering the shallow pn junction 52a are formed. The step of removing can be omitted. Moreover, due to thermal diffusion, the shallow pn junction 52a and the deep p
Since the n-junction 52b can be formed in parallel, the manufacturing process can be simplified and an increase in manufacturing cost can be suppressed.

8 and 9 are a plan view and a sectional view schematically showing the constitution of the second embodiment of the third invention, and FIG. 9 is a sectional view taken along line IX-IX in FIG. Show.

In the above-described first embodiment of the third invention, the shallow p provided in the region t inside the peripheral edge s of the light emitting / receiving region 52.
The n-junction 52a is formed in a closed loop shape elongated in one direction, for example, a rectangular shape, and a plurality of closed-loop shallow pn junctions 52a are provided in parallel in the inner region t. Shallow pn junction 52a in region t
Is formed in a closed loop shape, for example, a square shape, which extends in substantially equal distances in one direction and the other direction orthogonal to each other, and one closed loop shallow pn junction 52a is provided in the central portion of the inner region t.

The manufacture of the light emitting and receiving diode of this embodiment is as follows.
It may be performed in the same manner as the first embodiment of the third invention. In FIG. 8, for example, the planar shape of the window region 58a and the impurity blocking film 64 is a square, and the area of the impurity blocking film 64 is the window region 58a.
And a shallow pn junction 5 having a closed loop shape with a diffusion depth J _d of 5 μm for forming the deep pn junction 52b.
When one 2a is formed in the inner region t, the total length of the shallow pn junction 52a in this embodiment is about 1.3 times that in the case where the shallow pn junction 52a is not provided in the inner region t.

FIG. 10 shows an experimental result regarding photoelectric conversion characteristics when the light emitting and receiving diode of this example is used as a light receiving element. In the same figure, the cross-sectional structure of the main part of the light emitting and receiving diode of this embodiment is shown together with the experimental results. The position X in the direction along this cross section is the abscissa of the experimental results, and the scanning light is the semiconductor layer 56 at the position X Indicates the photoelectric conversion current generated when 54 is irradiated on the vertical axis of the experimental results. In the experiment, a light emitting / receiving diode whose emission wavelength was designed to be 740 nm was used, and scanning light having a spot size sufficiently smaller than that of the second semiconductor layer 56 was irradiated from a direction perpendicular to this layer 56. . And the wavelength of the scanning light is 550 nm
Then, the scanning light was scanned and the photoelectric conversion current at the position X was measured.

As can be understood from the figure, the light emitting / receiving region 5
In addition to the peripheral edge s of 2, the photoelectric conversion is also performed in the central portion of the area t inside the peripheral edge. Therefore, the amount of light received in the light emitting / receiving area 52 can be detected more accurately than in the conventional case, and the light receiving sensitivity can be increased more than in the conventional case.

11 and 12 are a plan view and a sectional view schematically showing the configuration of the third embodiment of the third invention.
2 shows a cross section taken along line XII-XII in FIG.

In this embodiment, the shallow pn junction 52a in the inner region t is formed into a closed loop shape, for example, a square shape, which extends at equal distances in one direction and the other direction orthogonal to each other, and a plurality of closed loop shallow pn junctions are formed. The joints 52a are provided so as to be scattered so as to surround the central portion of the inner region t.

The manufacture of the light emitting and receiving diode of this embodiment is as follows.
It may be performed in the same manner as the first embodiment of the third invention. In FIG. 11, for example, the planar shape of the window region 58a and the impurity blocking film 64 is a square, and the area of the impurity blocking film 64 is the window region 58a.
And a shallow pn junction 5 having a closed loop shape with a diffusion depth J _d of 5 μm for forming the deep pn junction 52b.
When four 2a are formed in the inner region t, the total length of the shallow pn junction 52a in this embodiment is about 1.7 times that in the case where the shallow pn junction 52a is not provided in the inner region t.

FIG. 13 shows an experimental result regarding photoelectric conversion characteristics when the light emitting and receiving diode of this embodiment is used as a light receiving element. In this figure, the same experiment as in the experiment of FIG. 13 was performed, and the cross-sectional structure of the essential part of the light emitting and receiving diode of this example was shown together with the experimental results. Also, as in the case of FIG. 13, the horizontal axis of the experimental results shows the photoelectric conversion current and the vertical axis shows the position X.

As can be understood from the figure, the light emitting / receiving region 5
In addition to the peripheral edge s of 2, the photoelectric conversion is also performed in the central portion of the area t inside the peripheral edge. Therefore, the amount of light received in the light emitting / receiving area 52 can be detected more accurately than in the conventional case, and the light receiving sensitivity can be increased more than in the conventional case.

14 and 15 are a plan view and a sectional view schematically showing the configuration of the fourth embodiment of the third invention, and FIG.
5 shows a cross section taken along line XIV-XIV in FIG.

In this embodiment, the shallow pn junction 52a in the inner region t is a wide planar region in the direction Y intersecting the side wall surface of the interlayer insulating film 58. The shallow pn junction 52a is provided on the entire or part of the peripheral edge s of the light receiving / emitting region 52, here the entire peripheral edge s, and the shallow pn junction 52a extends from the peripheral edge s to the inner region t.

Next, a manufacturing process of the light emitting / receiving diode shown in FIG. 14 will be described as an embodiment of the sixth invention. FIG. 16 (A)
17 (C) and 17 (A) to 17 (C) are cross-sectional views schematically showing the main manufacturing process steps of the sixth invention, and each of these drawings shows a cross section corresponding to the cross section of FIG.

First, a first impurity introduction mask 68 is formed on the first semiconductor layer 54. In this embodiment, an n-GaAs _0.8 P _0.2 substrate is prepared as the first semiconductor layer 54, and a first impurity introduction mask 66 that is substantially impermeable to impurities is laminated on this layer 54 (FIG. 16A). ).

Next, the first window 68a is formed in the first impurity introduction mask 68. In this embodiment, the first window 68a is formed by selectively removing the first impurity introduction mask 68 in the first window formation scheduled region 70 using photolithography and etching techniques (FIGS. 16A to 16 ( B)). The first semiconductor layer 54 in the first window formation scheduled region 70 is exposed through the first window 68a.

Next, an impurity is introduced into the first semiconductor layer 54 through the first window 68a to form the second semiconductor layer 56 for forming the deep pn junction 52b, and thereafter, the first impurity introduction mask is formed. Remove 68. In this embodiment, Zn as an impurity is introduced by thermal diffusion to form a deep pn junction 52b.
Is exposed from the first window 68a.
(FIG. 16C). The impurities may be introduced by thermal diffusion, ion implantation, or any other suitable method.

Next, an interlayer insulating film 58 which also serves as an impurity introduction mask is formed on the first semiconductor layer 54 and the second semiconductor layer 56. In this embodiment, the first semiconductor layer 54 and the deep p
On the second semiconductor layer 56 for forming the n-junction 52b,
An interlayer insulating film 58 that is substantially impermeable to impurities is stacked (FIG. 17A). The interlayer insulating film 58 is a film that is transparent to the light of the emission wavelength of the light emitting / receiving diode, such as a SiN film or S
It is an iO film or a SiON film.

Next, the second window 58b exposing the first semiconductor layer 54 in the region v adjacent to the peripheral edge u of the second semiconductor layer 56 for forming the deep pn junction 52b is provided with the interlayer insulating film 58.
To form. In this embodiment, the second window 58 is formed by selectively etching the interlayer insulating film 58 in the second window formation scheduled region 72 using photolithography and etching techniques.
b is formed (FIGS. 17A and 17B). The peripheral edge u of the second semiconductor layer 56 and the first semiconductor layer 54 in the adjacent region v are exposed through the second window 58b, and the second semiconductor layer 56 in the region inside the peripheral edge u and the first region other than the adjacent region v are exposed. The semiconductor layer 54 and the interlayer insulating film 58 are covered. Here, the second window 58
b is a closed loop window exposing the entire periphery of the peripheral edge u and the first semiconductor layer 54 in the adjacent region v corresponding to the entire periphery,
Therefore, the interlayer insulating film 58 is formed in an island shape in the region inside the peripheral edge u.
Remains.

The second window 58b is a window exposing a part of the peripheral edge u and the corresponding first semiconductor layer 54 in the adjacent area v, and the remaining peripheral edge u and the remaining adjacent area v are the interlayer insulating film. You may make it cover with 58.

Next, impurities are introduced into the first semiconductor layer 54 through the second window 58b to form the second semiconductor layer 56 for forming the shallow pn junction 52a. In this example,
A shallow pn is formed by introducing Zn as an impurity by thermal diffusion.
The junction 52a is formed in the portion of the first semiconductor layer 54 exposed through the second window 58b.

Next, the interlayer insulating film 58 inside the peripheral edge u.
Part or all of the window 5 for selectively electrically removing the whole and electrically connecting the p-side electrode 60 and the second semiconductor layer 56.
8a is formed, and thereafter, the p-side electrode 60 electrically connected to the second semiconductor layer 56 is formed. Further, an n-side electrode 62 electrically connected to the first semiconductor layer 54 is formed to complete a light emitting / receiving diode (FIGS. 14 and 15).

According to this embodiment, the width of the shallow pn junction 52a can be increased as the first semiconductor layer 54 exposed through the second window 58b is expanded.

When the interlayer insulating film 58 is a film transparent to the light of the emission wavelength, the deep pn junction 52 contributing to the light emission.
Even if a part of the region corresponding to b is covered with the interlayer insulating film 58, the decrease in light emission efficiency can be almost eliminated. The interlayer insulating film 5
8 may be a film opaque to the light of the emission wavelength, and after the impurities are introduced, the interlayer insulating film edge film 58 in the region corresponding to the deep pn junction 52b may be selectively removed.

Next, a manufacturing process of the light emitting / receiving diode shown in FIG. 14 will be described as an embodiment of the seventh invention. FIG. 18 (A)
19C and FIG. 19A to FIG. 19B are cross-sectional views schematically showing main manufacturing process steps of the seventh invention, and each of these drawings shows a cross section corresponding to the cross section of FIG.

First, a lower interlayer insulating film 581 and an upper interlayer insulating film 582, which also serve as an impurity introduction mask, are sequentially formed on the first semiconductor layer 54. In this embodiment, an n-GaAs _0.8 P _0.2 substrate is prepared as the first semiconductor layer 54,
A lower interlayer insulating film 581 and an upper interlayer insulating film 582 are sequentially stacked on this layer 54, and these films 581 and 582 are formed.
To obtain an interlayer insulating film 58 having a multi-layered structure (FIG. 18).
(A)). The lower interlayer insulating film 581 is the upper interlayer insulating film 58.
A material that is not substantially etched by the first etchant or etching gas used for etching the second layer, such as SiO 2.
The upper interlayer insulating film 582 is composed of
A material that is not substantially etched by the second etchant or etching gas used for etching the first element, such as SiN
Consists of.

Next, the first window 58 is formed in the upper interlayer insulating film 582.
2a is formed. In this embodiment, the upper interlayer insulating film 582 in the window formation scheduled region 74 is selectively etched using photolithography and etching techniques to form the first window 582a (FIGS. 18A to 18B). . First window 582
The lower interlayer insulating film 581 is exposed via a. The first etchant or etching gas used for etching the upper interlayer insulating film 582, for example, the etching gas CF ₄ has a small etching rate with respect to the lower interlayer insulating film 581 and therefore does not substantially etch the lower interlayer insulating film 581.

Next, a part of the lower interlayer insulating film 581 of the inner region 76 of the first window 582a is left, and the second window 581a is formed in the lower interlayer insulating film 581 of the region 76. In this embodiment, the lower interlayer insulating film 581 of the window inner region 76 is selectively etched by using photolithography and etching technique to form the second window 581a (FIG. 18 (B)-
FIG. 18C). The second etchant or etching gas, such as etchant HF, used for etching the lower interlayer insulating film 581 has a small etching rate with respect to the upper interlayer insulating film 582, and thus does not substantially etch the upper interlayer insulating film 582.

If the portion remaining in the inner region 76 of the lower interlayer insulating film 581 is expressed as a remaining portion 581b, the remaining portion 58 will be described.
1b is provided all around the periphery of the inner region 76, and the remaining portion 581b extends from the periphery of the inner region 76 toward the center of the inner region 76. Then, the first semiconductor layer 54 at the center of the inner region 76 is exposed through the second window 581a. Impurities are not substantially transmitted through the overlapping portions of the upper interlayer insulating film 582 and the lower interlayer insulating film 581, and the upper interlayer insulating film 58
The remaining portion 581b which is not covered with 2 substantially permeates impurities. The remaining portion 581b functions as a film for adjusting the impurity introduction depth, and the impurity introduction depth is controlled by, for example, arbitrarily changing the film thickness and material of the remaining portion 581b.

The remaining portion 581b can be provided at any suitable position in the inner area 76. For example, the remaining part 5
81b may be provided only in a part of the peripheral edge of the inner region 76, and the remaining portion 581b may extend from the peripheral edge of the inner region 76 to the central portion of the inner region 76, or the residual portion 581b.
May be provided only in the central portion of the inner region 76 without being provided at the peripheral edge of the inner region 76. Further, the remaining portion 581b may be provided so as to extend continuously, or may be isolated in an island shape and provided intermittently.

Next, the first window 582a and the second window 581a.
The impurity is introduced into the first semiconductor layer 541 through the
A second semiconductor layer 56 for forming the n-junction 52a and the deep pn junction 52b is formed. In this embodiment, Zn as an impurity is thermally diffused to form a deep pn junction 52b in the portion of the first semiconductor layer 54 exposed through the second window 581a, and a shallow pn junction 52a is formed in the lower interlayer insulating film. It is formed on the first semiconductor layer 54 below the remaining portion 581b of the film 581 (FIG. 19B). The impurities can be introduced by using thermal diffusion, ion implantation or any other suitable technique.

The remaining portion 581b acts so as to reduce the impurity introduction depth of the first semiconductor layer 54 below this portion 581b. Therefore, even if the impurity introduction conditions for the first semiconductor layer 54 below the residual portion 681b and the impurity introduction conditions for the first semiconductor layer 54 exposed through the second window 581a are the same, the impurity introduction depth of the residual portion 581b is It becomes shallower than the impurity introduction depth of the first semiconductor layer 54 exposed through the second window 581a. Therefore, by introducing impurities through the first window 582a and the second window 581a,
The shallow pn junction 52a and the deep pn junction 52b can be formed in parallel.

Next, the remaining portion 581b is removed by etching to form the window 58a of the interlayer insulating film 58 and expose the shallow pn junction 52a below the remaining portion 581b (FIG. 19B). When the lower interlayer insulating film 581 is made transparent to the light to be received, the light remaining portion 581
It is not always necessary to remove b.

Next, p which is electrically connected to the second semiconductor layer 56 is formed.
The side electrode 60 is formed. Further, an n-side electrode 62 electrically connected to the first semiconductor layer 54 is formed to complete a light emitting / receiving diode (FIGS. 14 and 15).

According to this embodiment, the shallow pn junction 52a is formed.
And the deep pn junction 52b can be formed in parallel. As the area of the remaining portion 581b is increased,
The width of the shallow pn junction 52a can be increased.

20 and 21 are a plan view and a sectional view schematically showing the structure of the fifth embodiment of the third invention.
1 shows a cross section taken along line XXI-XXI in FIG.

In this embodiment, the shallow pn junction 52a in the inner region t is a wide planar region in the direction Z intersecting the side wall surface of the interlayer insulating film 58. And shallow pn junction 52
a is provided on a part of the peripheral edge s of the light emitting / receiving region 52, and the shallow pn junction 52a extends from the peripheral edge s to the inner region t.

The manufacture of the light emitting and receiving diode of this embodiment is as follows.
It may be carried out in the same manner as the fourth embodiment of the third invention.

22 and 23 are a plan view and a sectional view schematically showing the structure of the sixth embodiment of the third invention.
3 shows a cross section taken along line XXIII-XXIII in FIG.

In this embodiment, the shallow pn junction 52a in the inner region t is a wide planar region in the direction Z intersecting the side wall surface of the interlayer insulating film 58. And shallow pn junction 52
a is provided on a part of the peripheral edge s of the light emitting / receiving region 52, and the shallow pn junction 52a extends from the peripheral edge s to the inner region t.

Next, a manufacturing process of the light emitting and receiving diode shown in FIG. 22 will be described as an embodiment of the eighth invention. FIG. 24 (A)
25 (C) and FIGS. 25 (A) to 25 (B) are cross-sectional views schematically showing main manufacturing process steps of the eighth invention, and each of these drawings shows a cross section corresponding to the cross section of FIG. 23.

First, an interlayer insulating film 58 which also serves as an impurity introduction mask is formed on the first semiconductor layer 54. In this embodiment, an n-GaAs _0.8 P _0.2 substrate is prepared as the first semiconductor layer 54, and an interlayer insulating film 58 that is substantially impermeable to impurities is laminated on this layer 54 (FIG. 24A). As the interlayer insulating film 58, a SiN film, a SiO film or a SiON film is laminated. The interlayer insulating film 58 may or may not be transparent to the light to be received or the light of the emission wavelength.

Next, a window 58a is formed in the interlayer insulating film 58. In this embodiment, a photolithography and etching technique is used to selectively remove the interlayer insulating film 58 in the window formation scheduled region 78 to form a window 58a (FIG. 24A to FIG.
(B)). The first semiconductor layer 54 in the window formation scheduled region 78 is exposed through the window 58a.

Next, an interlayer insulating film 58 is formed on the first semiconductor layer 54.
Impurities are introduced through the window 58a of the deep pn junction 52b.
A second semiconductor layer 56 for forming is formed. In this embodiment, Zn is diffused as an impurity, and a deep pn junction 52b is formed in the first semiconductor layer 54 in the window formation scheduled region 78 exposed through the window 58a (FIG. 24C).

Next, the second semiconductor layer 56 is partially covered with the etching prevention film 80. The second semiconductor layer 56 in the region where the deep pn junction 52b is to be formed is covered with the etching prevention film 80, and the second semiconductor layer 56 in the region where the shallow pn junction 52a is to be formed is exposed without being covered with the etching prevention film 80.
In this embodiment, the etching prevention film 80 is made of resist. Then, the area inside the window 58a is the area 82 at the boundary K.
It is divided into a and a region 82b. An etching prevention film 80 is extended on the second semiconductor layer 56 and the interlayer insulating film 58 located on the one region 82a side from the boundary K, and the second semiconductor layer 56 and the interlayer insulating film 58 located on these one side. Is covered with an etching prevention film 80. Further, the second semiconductor layer 56 and the interlayer insulating film 58 located on the other region 82b side from the boundary K are exposed without being covered with the etching prevention film 80 (FIG. 25A).

Next, the second semiconductor layer 56 is etched through the anti-etching film 80 to partially reduce the layer thickness of the second semiconductor layer 56 to form a shallow pn junction 52a. Two semiconductor layers 56 are formed. In this embodiment, the second semiconductor layer 56 in the region 82b exposed from the window 58a without being covered with the etching prevention film 80 is selectively etched, and the second semiconductor layer 56 having a thin layer thickness is formed in the region 82b.
Are formed (FIG. 25B). A shallow pn junction 52a can be formed by reducing the layer thickness of the second semiconductor 56.

Next, the etching prevention film 80 is removed, and thereafter, the p-side electrode 60 electrically connected to the second semiconductor layer 56 is formed. Further, an n-side electrode 62 electrically connected to the first semiconductor layer 54 is formed to complete the light emitting / receiving diode (FIG. 2).
2 and FIG. 23).

According to this embodiment, the etching prevention film 8 is formed.
The second semiconductor layer 56 in the region 82b exposed without being covered with 0
The width of the shallow pn junction can be increased in accordance with the increase in width.

The light emitting / receiving diodes of the above-mentioned second and third inventions are suitable for use in constructing a light receiving / emitting diode array. For example, a plurality of light receiving / emitting diodes are arranged in a straight line or in a staggered pattern. To form a light emitting and receiving diode array. This array can be used as an exposure light source of a photosensitive drum in electrophotographic printing and as an image sensor in an image reading apparatus, and therefore, the array is suitable for use in an apparatus having the dual functions of electrophotographic printing and image reading. Is.

The invention is not limited to the above-mentioned embodiments, and therefore, the shape, size, disposition position, forming material and the like of each component can be arbitrarily changed.

[0117]

As is apparent from the above description, according to the light receiving and emitting diode of the first invention, the width of the shallow pn junction is increased with respect to the width of the deep pn junction, so that the light receiving sensitivity is higher than that of the conventional one. Can be increased.

The light emitting and receiving diode of the second invention is a preferred embodiment of the first invention, and according to the second invention, a shallow pn junction is provided so as to meander along the periphery of the light receiving and emitting region, so that the shallow p is formed.
The width of the n-junction can be increased more than ever before. Moreover, since the shallow pn junctions meander, the shallow pn junctions having the light receiving function are arranged in a more dispersed manner than in the conventional case, and therefore the amount of light received in the light emitting / receiving region can be detected more accurately.

The light emitting and receiving diode of the third invention is a preferred embodiment of the first invention. According to the third invention, the shallow pn junction is provided also in the region inside the peripheral edge of the light receiving and emitting region. The width of the can be increased more than before. Moreover, p is shallow even in the area inside the periphery of the light receiving and emitting area.
Since the n-junctions are provided, the shallow pn junctions having a light receiving function are arranged in a dispersed manner as compared with the conventional case, and therefore, the amount of light received in the light emitting / receiving area can be detected more accurately than before.

The method for manufacturing a light emitting and receiving diode according to the fourth aspect of the present invention is one method for manufacturing the light receiving and emitting diode according to the second aspect of the present invention. According to the fourth aspect of the present invention, impurities are heated through the window of the interlayer insulating film. By diffusing, formation of a deep pn junction and formation of a shallow pn junction can be performed in parallel. Moreover, a meandering shallow pn junction can be formed by merely making a simple design change in which the window periphery of the interlayer insulating film also serving as an impurity introduction mask is meandered. Therefore, the area of the shallow pn junction can be increased while avoiding the complication of the manufacturing process.

The manufacturing method of the light receiving and emitting diode of the fifth invention is one method for manufacturing the light receiving and emitting diode of the third invention. According to the fifth invention, the window of the interlayer insulating film and the impurity blocking film are formed. By thermally diffusing the impurity through the formation of the deep pn junction and the shallow pn junction can be performed in parallel. Therefore, while avoiding complication of the manufacturing process, shallow p
The width of the n-junction can be increased.

The method for manufacturing a light emitting and receiving diode according to the sixth invention is one method for manufacturing the light receiving and emitting diode according to the third invention. According to the sixth invention, the second method for forming a deep pn junction is used. A first semiconductor layer in a region adjacent to the periphery of the semiconductor layer is exposed from the second window of the interlayer insulating film, and impurities are introduced into the first semiconductor layer through the second window to form a shallow pn junction. Two semiconductor layers are formed. Therefore, the width of the shallow pn junction can be increased as the first semiconductor layer exposed from the second window is widened, so that the shallow pn junction spreading in a planar shape can be easily formed. In order to detect the amount of light received in the light emitting / receiving region with higher accuracy, it is advantageous to form the shallow pn junction in a planar shape.

The method for manufacturing a light emitting and receiving diode according to the seventh invention is one method for manufacturing the light receiving and emitting diode according to the third invention. According to the seventh invention, the film thickness of the lower interlayer insulating film is increased. According to the above, or by appropriately and appropriately selecting the material of the lower interlayer insulating film, the introduction depth of impurities can be made shallow. Therefore, by introducing impurities through the first window of the upper interlayer insulating film and the second window of the lower interlayer insulating film, a deep pn junction is formed in the region inside the second window not covered with the lower interlayer insulating film. At the same time, a shallow pn junction can be formed in the first window inner region covered with the lower interlayer insulating film. Moreover, since the width of the shallow pn junction can be increased in accordance with the widening of the lower interlayer insulating film exposed through the second window, it is possible to easily form the shallow pn junction that spreads in a plane. In order to detect the amount of light received in the light emitting / receiving region with higher accuracy, it is advantageous to form the shallow pn junction in a planar shape.

The method for manufacturing a light emitting and receiving diode according to the eighth invention is a method for manufacturing the light receiving and emitting diode according to the third invention. According to the eighth invention, the second method for forming a deep pn junction is used. A shallow pn junction is formed by etching the semiconductor layer through the etching prevention film to partially reduce the layer thickness of the second semiconductor layer. Therefore, the width of the shallow pn junction can be increased in accordance with the expansion of the region not covered with the etching prevention film, so that the shallow pn junction spreading in a planar shape can be easily formed. In order to detect the amount of light received in the light emitting / receiving region with higher accuracy, it is advantageous to form the shallow pn junction in a planar shape.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing a configuration of an embodiment of a second invention.

FIG. 2 is a sectional view schematically showing the configuration of an embodiment of the second invention.

3A to 3C are cross-sectional views schematically showing main manufacturing process steps of the fourth invention.

FIGS. 4A and 4B are cross-sectional views for explaining a minimum junction depth J _m of a shallow pn junction.

FIG. 5 is a plan view schematically showing a configuration of a first embodiment of the third invention.

FIG. 6 is a sectional view schematically showing a configuration of a first embodiment of the third invention.

7 (A) to 7 (C) are cross-sectional views schematically showing main manufacturing process steps of the fifth invention.

FIG. 8 is a plan view schematically showing a configuration of a second embodiment of the third invention.

FIG. 9 is a sectional view schematically showing the configuration of a second embodiment of the third invention.

FIG. 10 is a diagram showing experimental results regarding photoelectric conversion characteristics of the second embodiment of the third invention.

FIG. 11 is a plan view schematically showing the configuration of a third embodiment of the third invention.

FIG. 12 is a sectional view schematically showing the configuration of a third embodiment of the third invention.

FIG. 13 is a diagram showing experimental results regarding photoelectric conversion characteristics of the third embodiment of the third invention.

FIG. 14 is a plan view schematically showing a configuration of a fourth embodiment of the third invention.

FIG. 15 is a cross sectional view schematically showing a configuration of a fourth embodiment of the third invention.

16A to 16C are cross-sectional views schematically showing main manufacturing process steps of the sixth invention.

17A to 17C are cross-sectional views schematically showing main manufacturing process steps of the sixth invention.

18A to 18C are cross-sectional views schematically showing main manufacturing process steps of the seventh invention.

19A to 19B are cross-sectional views schematically showing main manufacturing process steps of the seventh invention.

FIG. 20 is a plan view schematically showing the configuration of the fifth embodiment of the third invention.

FIG. 21 is a sectional view schematically showing the configuration of a fifth embodiment of the third invention.

FIG. 22 is a plan view schematically showing the configuration of a sixth embodiment of the third invention.

FIG. 23 is a sectional view schematically showing the configuration of a sixth embodiment of the third invention.

24A to 24C are cross-sectional views schematically showing main manufacturing process steps of the eighth invention.

25 (A) to (B) are cross-sectional views schematically showing main manufacturing process steps of the eighth invention.

FIG. 26 is a perspective view of a principal part showing an example of the structure of a printing / reading integrated apparatus.

27 (A) and 27 (B) are a plan view and a cross-sectional view schematically showing a configuration of a main part of an LED array.

FIG. 28 is a diagram showing the relationship between the pn junction depth of an LED and the emission intensity.

FIG. 29 is a diagram showing experimental results regarding photoelectric conversion characteristics when an LED is used as a light receiving element.

FIG. 30 is a diagram showing changes in the absorption coefficient of GaAs _0.8 P _0.2 with respect to the incident light wavelength.

[Explanation of symbols]

 40, 52: light emitting and receiving regions 40a, 52a: shallow pn junction 40b, 52b: deep pn junction 42, 54: first semiconductor layer 44, 56: second semiconductor layer 46, 58: interlayer insulating film 46a, 58a: window 58b 581a: second window 581: lower interlayer insulating film 582: upper interlayer insulating film 62, 76: window inner region 68: first impurity introduction mask 68a, 582a: first window 80: etching prevention film

Front page continuation (72) Inventor Takaatsu Shimizu 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Kazuo Tokura 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Incorporated (72) Inventor Yasuo Iguchi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (8)

[Claims] 1. A light emitting and receiving diode comprising a light receiving and emitting region in which a shallow pn junction for photoelectric conversion and a deep pn junction for light emission are provided in contact with each other. A light emitting and receiving diode characterized in that it is made up of a large number. 2. The light emitting and receiving diode according to claim 1, wherein a shallow pn junction is provided along the periphery of the light receiving and emitting region in a meandering manner. 3. The light receiving and emitting diode according to claim 1, wherein a shallow pn junction is provided at a peripheral edge of the light receiving and emitting area and an area inside the peripheral edge of the light receiving and emitting area. 4. In manufacturing the light emitting and receiving diode according to claim 2, a step of forming an interlayer insulating film also serving as an impurity introduction mask on the first semiconductor layer, and the interlayer insulating film having a window periphery meandering. A step of forming a window, and a step of thermally diffusing impurities into the first semiconductor layer through the window of the interlayer insulating film to form a second semiconductor layer for forming a shallow pn junction and a deep pn junction. A method of manufacturing a light emitting and receiving diode, comprising: 5. In manufacturing the light emitting and receiving diode according to claim 3, a step of forming an interlayer insulating film also serving as an impurity introduction mask on the first semiconductor layer, and a step of forming a window in the interlayer insulating film. A step of forming an impurity blocking film on the first semiconductor layer in the window inner region of the interlayer insulating film, and thermally diffusing the impurities in the first semiconductor layer through the window of the interlayer insulating film and the impurity blocking film, And a step of forming a second semiconductor layer for forming a deep junction and a deep pn junction. 6. In manufacturing the light emitting and receiving diode according to claim 3, a step of forming a first impurity introduction mask on the first semiconductor layer, and a step of forming a first window in the first impurity introduction mask. And a step of forming a second semiconductor layer for forming a deep pn junction by introducing impurities into the first semiconductor layer through a first window, and then removing the first impurity introduction mask. A step of forming an interlayer insulating film also serving as a second impurity introduction mask on the first and second semiconductor layers, and exposing the first semiconductor layer in a region adjacent to the periphery of the second semiconductor layer for forming a deep pn junction Forming a second window in the interlayer insulating film, and forming a second semiconductor layer for forming a shallow pn junction by introducing impurities into the first semiconductor layer through the second window. Manufacture of a light emitting and receiving diode characterized by comprising Build method. 7. A method of manufacturing the light emitting / receiving diode according to claim 3, wherein a lower interlayer insulating film and an upper interlayer insulating film also serving as an impurity introduction mask are sequentially formed on the first semiconductor layer, A step of forming a first window in the upper interlayer insulating film, and a step of partially leaving the lower interlayer insulating film in the inner region of the first window to form a second window in the lower interlayer insulating film of the region And introducing impurities into the first semiconductor layer through the first window and the second window to form a second semiconductor layer for forming a shallow pn junction and a deep pn junction. A method of manufacturing a light emitting and receiving diode characterized. 8. In manufacturing the light emitting and receiving diode according to claim 3, a step of forming an interlayer insulating film also serving as an impurity introduction mask on the first semiconductor layer, and a step of forming a window in the interlayer insulating film. A step of introducing an impurity into the first semiconductor layer through a window of an interlayer insulating film to form a second semiconductor layer for forming a deep pn junction; And a step of covering the second semiconductor layer with an etching stopper film to partially reduce the thickness of the second semiconductor layer to form a second semiconductor layer having a small thickness for forming a shallow pn junction. A method of manufacturing a light emitting / receiving diode, comprising: