JPH06314347A - Neural network learning circuit - Google Patents

Abstract

PURPOSE:To provide a neural network learning circuit which does not deteriorate the fast learning performance and also reduces the occurrence of crosstalks by superposing a specific orthogonal code pattern on the corresponding weight or the threshold output signal and multiplying the acquired error signal by one of orthogonal code patterns for integration to directly calculate a changed variable of the energy relation caused by the change of the weight or the threshold. CONSTITUTION:A learning circuit includes a means which compares the output signal of a neural network with a teacher signal to produce an error signal in a learning mode of the neural network. In such a circuit, the orthogonal code patterns are defined as P1-Pn and an array of orthogonal code patterns Pi is defined as Pi=(Pi1,...,Pim) where Pik=+ or -1 and 1<=k<=m are satisfied. Under such conditions, a means produces an orthogonal code pattern where each orthogonal pattern satisfied the preceding equation. Then the result obtained by multiplying the output of the error signal production means by the orthogonal code pattern is integrated in a time range. Then the weight or the threshold value of the neural network is decided according to the output the integration output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a neural network learning circuit, and more particularly to a neural network learning circuit incorporating a learning technique for correcting internal parameters input to a neural network according to input / output conditions.

[0002]

2. Description of the Related Art Conventionally, a neural network having a function similar to human intelligence activity such as pattern recognition, inference, optimization problems, etc., which is constructed by using a large number of processing elements for adding / subtracting and non-linearly processing an input signal. In
In order to obtain a desired input / output characteristic, a learning process of modifying internal parameters according to input / output conditions is necessary. However, the conventional neural network learning is realized on a simulator or emulator using a digital circuit or software, and it is desired to establish a learning method for the neural network circuit realized by an analog circuit.

FIG. 13 shows the structure of a three-layer neural network. FIG. 3A shows a three-layer perseprotron,
FIG. 2B shows the configuration of the neuron element.

[0004] Neural network shown in FIG (a), the signal input terminal 11 _-1 ～11- _4, an input layer 12, middle layer 13. The output layer 14 output terminal 15 _-1 to 15 _-4, and each neuron element It consists of 16. The neuron element shown in FIG. 2B is roughly divided into a product-sum operation unit Σ and a function output unit f. The product-sum calculation unit multiplies each of the plurality of inputs I ₁ ... I _n by different weights w ₁ ... W _n , and adds the multiplied value to a value obtained by further adding a threshold value θ that does not change due to the above input. Is output. The function output unit performs function processing on the output of the product-sum calculation unit and outputs the result. At this time, generally, the same result is output plural times. After all, the output O of the neuron element is

[Equation 3] Is expressed as

Here, the function f is generally a monotonic function and has a non-linear characteristic with respect to the input. Usually, a function S of the following form called a sigmoid function is used.

[0006]

[Equation 4] However, s is a parameter that determines the steepness of the slope of the function.

A neuron element 16 of FIG. 13 (b) is arranged in layers as shown in FIG. 13 (a), and neurons between layers are connected to each other to form a multilayer neural network. This neural network corrects the weight and threshold of each neuron element from the difference (error) between the desired output and the actual output for a certain input so that the desired output corresponding to various inputs can always be obtained. You can

FIG. 14 shows a configuration example of an analog neural network element. The neural network element shown in the figure has an input terminal 21 for inputting an input signal to the element, an input terminal 22 for inputting a weight to the element, an output terminal 23 for outputting an output signal, and an output proportional to an input signal and a weight. , A threshold circuit 25 for adding an output corresponding to a threshold, an adder circuit 26 for outputting the result of adding the outputs of the multiplier circuit 24 and the threshold circuit 25, and a non-linear function value for the output of the adder circuit 26. It is composed of a non-linear function generating circuit 27 which outputs to the terminal 23. Each multiplication circuit 24
And the output current of the threshold circuit 25 is added through the adder circuit 26 and processed by the non-linear function generating circuit 27,
Is output.

The learning of the multilayer neural network as described above is generally executed based on the following equation.

[Equation 5] Here, Δw _i is a weight or a correction amount of the threshold value w _i , η is a learning coefficient representing the learning speed of the system, and E is an energy function. Further, O _i and T _i are an output signal and a teacher signal, respectively.

When simulating the learning operation of the multilayer neural network by a computer, it is generally assumed that the input / output characteristic of each neuron element is a sigmoid function, and the correction amount of the weight or the threshold value is calculated from the above equation, Finally, the correction is repeated until the difference between the output signal and the teacher signal becomes sufficiently small. However, even if the weight or the threshold value obtained by the computer simulation is given to the analog neural network element as it is as shown in FIG. 13, the characteristic of each multiplication circuit 24, the threshold circuit 25 and the non-linear function generating circuit 27 of the element is offset. Since there are variations such as the above, the element does not always operate according to the simulation. Therefore, in order to perform the correct learning operation even for such a variation element, the value of the variation ∂E / ∂w of the energy function is directly measured by some method, and the weight or the threshold value is corrected based on this. A learning method to do is required.

Conventionally, as a learning method for directly measuring ∂E / ∂w, a method called a multi-frequency vibration method has been proposed.

FIG. 15 is a diagram for explaining a neural network learning circuit based on the multi-frequency vibration method.
FIG. 1A shows an outline of a neural network learning circuit based on the multi-frequency vibration method. In the figure, the neural network learning circuit includes an analog neural network element 31, an input signal generating circuit 32 for the neural network element 31, a teacher signal generating circuit 33 corresponding to a signal from the input signal generating circuit 32, and a neural network element 31. Output and corresponding teacher signal generation circuit 3
Error sum-of-squares generation circuit 34 that outputs the sum of squares (squared error) of the difference from each output of FIG. 3, weight / threshold control circuit 35 (details in FIG. 14B), and outputs a sine wave of a single frequency. Oscillation circuit 131, multiplication circuit 13 that outputs the product of two inputs
2, a low-pass filter circuit 133 that outputs only the low-frequency component of the input signal, an inverter 134 that inverts the positive and negative of the input signal to output, an integrating circuit 135 that outputs a value obtained by integrating the input signal in the time domain, and two inputs The adder circuit 136 outputs the sum of

Each weight / threshold control circuit 35 is connected to the corresponding weight or threshold input of the neural network element 31. Also, each weight
The oscillation circuits 131 connected to the threshold value control circuit 35 all oscillate at frequencies different from each other. Further, the cutoff frequency of the low-pass filter circuit 133 of each weight / threshold control circuit 35 is set to be sufficiently low with respect to the interval between the adjacent oscillation frequencies of the oscillation circuit 131.

At this time, when one oscillating circuit 131 (amplitude a, frequency f) in each weight / threshold control circuit 35 is operated, the corresponding weight or threshold value in the neural network element 31 has the amplitude a, frequency. The vibration component of f is superimposed. This vibration component propagates to each output terminal of the neural network element 31, and finally the output of the error sum of squares generation circuit 34 is proportional to the energy function of the neural network element 31, as is apparent from the function of the circuit. Therefore, if the amplitude a is small, the ratio of the amplitudes a ′ and a of the component of the frequency f of the error sum of squares generation circuit 34 to the absolute value of the change of the energy function caused by the minute change of the weight or the threshold. The value, that is, | ∂E / ∂w | will be directly expressed.

Further, ignoring the phase delay when the superimposed signal propagates through the neural network element 31 and the error sum of squares generation circuit 34, the output of the oscillation circuit 131 and the output of the component of the frequency f of the error square sum generation circuit 34. If and are in phase, the value of the change ∂E / ∂w of the energy function is positive, and if the phase is opposite, it is negative.

The output of the error sum of squares generation circuit 34 on which the component of the frequency f is superimposed is distributed to each weight / threshold control circuit 35, and is multiplied by the sine wave of the oscillation circuit 131 in the multiplication circuit 132, and the low-pass filter circuit. By passing through 133,
An output proportional to ∂E / ∂w appears only in the weight / threshold control circuit 35 having the oscillation circuit 131 that has generated the frequency f.
No output appears in the other control circuits 35. By inputting this output to the integration circuit 135 via the inverter 134, the output of the integration circuit 135 is ∂E per unit time.
It will be corrected in proportion to / ∂w, ∂E / ∂w
Learning that directly measures is realized.

Each control circuit 35 individually detects only the frequency component of its own oscillator and operates independently even when all the oscillators 131 of each control circuit 35 operate simultaneously. Therefore, even in such a case, the learning function of each control circuit 35 is maintained as it is. At this time, all weights / thresholds in the neural network element 31 are simultaneously corrected, so that high-speed learning is achieved.

As described above, the neural network learning circuit based on the multi-frequency vibration method can perform high-speed learning even for a neural network element whose internal circuit has variations.

[0019]

However, in the above-mentioned conventional method, the switching cycle of the input pattern to the neural network element needs to be equal to or lower than the cutoff frequency of the low-pass filter circuit 133, which impedes high-speed learning. There is a problem that is.

In order to control a large number of weights or thresholds at the same time, it becomes necessary to input a large number of frequency components into the neural network element. This means that when the neural network elements are integrated and miniaturized, a large number of signal lines with different frequency components are concentrated in a small area. There is a possibility that a talk may be caused, learning efficiency may be reduced, or learning may be impossible.

The present invention has been made in view of the above points, solves the above-mentioned conventional problems, and does not impede the high-speed learning by improving the superimposed signal that gives a slight change to each weight or threshold, and It is an object of the present invention to provide a neural network learning circuit that hardly causes crosstalk.

[0022]

FIG. 1 shows the first principle configuration of the present invention.

According to the present invention, a plurality of neural network input ports, at least one neural network output port, a plurality of processing elements for performing weighted addition and nonlinear processing on an input signal, and a plurality of processing elements connected to each other are provided. Connection element, input signal generating means 1002 for generating an input signal to be learned in the neural network, teacher signal generating means 1003 for generating a teacher signal corresponding to the input signal, and output of the neural network during learning of the neural network 1001. in the learning circuit for comparing the signal and the teacher signal is connected to a neural network comprising an error signal generator 1004 for generating an error signal, the orthogonal code patterns respectively P _1, P _2, ..., and P _n, the orthogonal The array of patterns P _i is P _i = {p _i1 , p _i2 , ..., p _im }
If (p _ik = ± 1, 1 ≦ k ≦ m), each orthogonal pattern is

[0024]

[Equation 6]

Orthogonal code pattern generating means 1005 for generating an orthogonal code pattern satisfying the above condition, integrating means 1006 for integrating the result of multiplying the output of the error signal generating means 1004 by the orthogonal code pattern, and integrating means 1006. The neural network 100 according to the output of the means 1006
The parameter control means 1007 for determining the input of the weight of 1 or the threshold value, the input signal to the neural network 1001 and the teacher signal store their respective values for at least one cycle of the orthogonalization code pattern, and the orthogonalization code pattern Start of one cycle and neural network 1001
Means 100 for synchronizing the switching of the input signal to the
8 and.

FIG. 2 shows a second principle configuration of the present invention.

According to the present invention, the input ports of a plurality of neural networks, the output ports of at least one neural network, and a plurality of processing elements that perform weighted addition and nonlinear processing on an input signal are connected to each other. A plurality of connecting elements, an input signal generating means 1002 for generating an input signal to be learned in the neural network, a teacher signal generating means 1003 for generating a teacher signal corresponding to the input signal, and a neural network In a learning circuit connected to a neural network including an output signal and an error signal generating means 1004 for generating an error signal between the output signal and the teacher signal, each of m elements of n pulse trains P _i synchronized with the clock signal is denoted by P. _ik (1 ≦ i ≦
n, 1 ≦ k ≦ m, P _ik = ± 1),

[0028]

[Equation 7]

An orthogonal code pattern generating means 1005 for generating an orthogonal code pattern satisfying the above conditions and the time required for all inputs of the input signals to be learned by the neural network 1001 are defined as one cycle, and the output of the error signal generating means 1004 is Integrating means 1 for integrating in the time domain during the period of one cycle
060 and the output of the integration means 1060 multiplied by the output of the orthogonalization code pattern generation means 1005, and the addition means 1090 that adds the result for each cycle for each pulse train, and the neural network 100 according to the output of the addition means 1090.
Parameter control means 1007 for determining the weighting or threshold input of 1 and synchronization means 1080 for synchronizing the start of one cycle and the switching of the orthogonalization pattern and holding the value of the orthogonalization pattern for at least one period. including.

FIG. 3 is a block diagram of the third principle of the present invention.

According to the present invention, a plurality of network input ports, at least one neural network output port, a plurality of processing elements for performing weighted addition and nonlinear processing on an input signal, and a plurality of wirings for connecting the processing elements to each other. An element, an input signal generating means 1002 for generating an input signal to be learned, and a teacher signal generating means 1003 for generating a teacher signal corresponding to the input signal.
And a learning circuit connected to the neural network including an error signal generating means 1004 for generating an error signal by comparing the output signal of the neural network 1001 and the teacher signal during learning of the neural network 1001. A plurality of pulse signals, and the pulse widths of the individual pulse signals are equal to each other,
At the same time, the pulse signal generating means 1050 outputs only one pulse signal of the plurality of pulse signals, and the output of the error signal generating means 1004 is the pulse signal generating means 1.
Integrating means 1061 for integrating in the time domain in synchronization with the pulse signal output by 050, and parameter controlling means 1007 for changing the weight or threshold input of the neural network 1001 according to the output of the integrating means 1061.
The input signal and the teacher signal to the neural network 1001 retain their respective values for at least the time required to output all of the plurality of pulse signals, and the start of the output of the plurality of pulse signals and the neural network 1001. Synchronization means 1081 for synchronizing the switching of the input signal to.

FIG. 4 is a block diagram of the fourth principle of the present invention.

According to the present invention, a plurality of network input ports, at least one neural network output port, and a plurality of processing elements for performing weighted addition and non-linear processing with respect to the input signal are connected to each other. A plurality of connection elements, an input signal generating means 1002 for generating an input signal to be learned, and a teacher signal generating means 100 for generating a teacher signal corresponding to the input signal.
3 and the error signal generating means 1004 for generating an error signal by comparing the output signal of the neural network 1001 and the teacher signal during learning of the neural network 1001.
In the learning circuit connected to the neural network 1001 including, the time required for all inputs of the input signal to be learned by the neural network 1001 is one cycle, and the output of the error signal generating means 1004 is timed during one cycle. A first integrating means 1062 for integrating in a region, a pulse signal generating means 1051 for generating a plurality of pulse signals synchronized with a clock signal and having the same pulse width so as not to overlap in time, and a first integrating means 1062. The output of is integrated according to the gate signal synchronized with the pulse signal,
Second integration means 106 for adding the integration result and the pulse signal
3 and parameter control means 1007 for determining the weight or threshold input of the neural network 1001 according to the output of the second integration means 1063, and the start of one cycle is synchronized with the switching of the pulse signal, and the period of at least one cycle Inside is a synchronizing means 1082 for holding the value of the pulse signal.
Including and

[0034]

According to the present invention, an orthogonalization code pattern satisfying a predetermined condition is superposed on a corresponding weight or threshold output signal, and the obtained error signal and one of the orthogonalization code patterns are multiplied and integrated. , The weight corresponding to the multiplied orthogonal code pattern or the change ∂E / ∂w of the energy function with the change of the threshold value is directly obtained. By holding the input signal and the teacher signal corresponding to the input signal during the period in which the orthogonal code pattern is output for one cycle, the variation ∂E / ∂w of the energy function with respect to the input signal can be obtained. Further, the learning operation can be performed on all the input signals by obtaining the change amount of the corresponding energy function for all the input signals and correcting the corresponding weight or the threshold output based on the result. .

Further, according to the present invention, a plurality of orthogonal code patterns satisfying a predetermined condition are superposed on corresponding weight or threshold output signals, and the orthogonal code patterns to be superposed during the period of inputting all the input signals. The error signal obtained while being held is integrated, and the integrated signal and the orthogonalization code pattern 1
The period for multiplying two and inputting all the above input signals is 1
By performing the operation of sequentially adding as a cycle for all of the above-mentioned orthogonalized code pattern sequences, the change amount ∂E / ∂w of the energy function due to the change of the weight or the threshold value corresponding to the multiplied orthogonal code pattern is , The change amount with respect to all the input signals is summed or averaged. Therefore, if the corresponding weight or threshold value output is corrected based on the change amount, the learning operation can be performed with respect to all the input signals.

Further, according to the present invention, a plurality of pulse signals in which widths of individual pulse signals are equal to each other and at most one pulse is generated at the same time are superimposed on corresponding weight or threshold output signals. Then, the obtained error signal is integrated only during the period when one of the pulse signals is generated, and the difference from the integrated value when all the pulse signals are not generated is measured, and this pulse signal is supported. Change in energy function due to change in weight or threshold value ∂E / ∂w
Ask directly. By holding the input signal and the teacher signal corresponding to the input signal during the period of outputting one cycle of the pulse signal, the change amount of the energy function with respect to the input signal ∂E / ∂
w is required. Furthermore, the learning operation can be performed for all input signals by obtaining the amount of change in the corresponding energy function for all input signals and modifying the corresponding weight or threshold output based on the result. it can.

Further, according to the present invention, a plurality of pulse signals in which the widths of individual pulse signals are equal to each other and at most one pulse is generated at the same time are superimposed on corresponding weight or threshold output signals. , Having a first integrating means for integrating the error signal obtained while holding the pulse signal to be superimposed while inputting all the input signals, and executing the first integration result obtained by this The second integration means included in the weight or threshold control circuit corresponding to the pulse signal in which the pulse is generated is integrated for a certain period of time, and the integrated value and the difference when all the pulse signals are not generated are measured. By executing the operation for one cycle of the pulse signal,
The change ∂E / ∂w of the energy function due to the change of the weight or the threshold value corresponding to each pulse signal is directly obtained. The change ∂E / ∂w of the energy function obtained at this time is the sum or average of the changes for all input signals, so if the corresponding weight or threshold output is modified based on this change. , The learning operation can be performed on all input signals.

As described above, according to the present invention, a binary pulse code string signal synchronized with a certain timing signal, which is completely different from the conventional sine wave, is superimposed on the weight or threshold value, and the obtained error signal is superimposed. Since the change amount ∂E / ∂w of the energy function due to the change of the weight or the threshold value is directly obtained by the calculation operation with the signal, the crosstalk between the superimposed signals can be reduced and the efficiency can be reduced as compared with the conventional method. Learning operation becomes possible.

[0039]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 5 shows the configuration of the neural network circuit according to the first embodiment of the present invention. FIG. 3A shows the entire neural network circuit. The neural network circuit 100 includes an analog neural network element 41, an input signal generation circuit 42 that generates a signal to be input to the neural network element 41, and a teacher signal generation circuit that generates a teacher signal corresponding to the signal of the input signal generation circuit 42. 43, an error square sum circuit 4 that outputs the sum of squares (square error) of the difference between each output of the neural network element 41 and each output of the corresponding teacher signal generating circuit 43.
4, a weight / threshold control circuit 45, a clock generation circuit 47 that outputs a clock signal for synchronization of the entire system, an input pattern switching of the input signal generation circuit 42, or a function of controlling the operation timing of the weight / threshold control circuit 45 And a timing generation circuit 47 having

As the error sum of squares circuit 44, the circuit used in the conventional multi-frequency vibration method can be applied as it is.

The weight / threshold control circuit 45 will be described in detail.

FIG. 5B shows the configuration of the weight / threshold control circuit of the neural network circuit according to the first embodiment of the present invention. The weight / threshold control circuit 45 includes the clock generation circuit 4
Clock signal from 7 or timing generation circuit 4
7. An orthogonal code pattern circuit 141 that outputs an orthogonal code pattern signal synchronized with the timing signal from 7; a multiplication circuit 142 that outputs a product of the output E2 of the error sum of squares circuit 44 and two inputs of the orthogonal code pattern signal; and a multiplication circuit 142. Circuit 143 that outputs a value obtained by integrating the input signal from the input circuit in the time domain, an inverter 144 that outputs the input signal from the integrating circuit 143 by inverting the positive and negative signs, and the timing generation circuit 4
7 in synchronization with the timing signal (SYN)
Latch circuit 145 having the function of holding the signal No. 3 and attenuator 14 for attenuating the output of orthogonal code pattern circuit 141
It is composed of an adder circuit 147 which outputs the sum of 6 and 2 inputs.

The orthogonal code pattern generated by the orthogonal code pattern circuit 141 is a fixed length code pattern that takes a binary value of "+1" or "-1", and each weight / threshold control circuit 4
The code patterns of 5 all have the same pattern length and are different from each other.

Here, each weight / threshold control circuit 45 has
Orthogonal code pattern P_1,P ₂,…, P_nage,
Pattern P_iArray is P₁= {P_i1, P_i2，… ，
p_im} (P_ik= ± 1, 1 ≦ k ≦ m)
Each pattern

[Equation 8] Shall be satisfied. However, m is the number of patterns and P _ik is an orthogonal pattern. In general, an orthogonal code pattern satisfying the above equation can be realized only when the pattern length m is a multiple of 4, and conversely, when m is a multiple of 4, the maximum (m−
1) Types of orthogonal code patterns can be created.

FIG. 6 shows the timing of each signal in the first embodiment of the present invention.

In the figure, IN-1 to IN-3 are input signals supplied from the input signal generating circuit 42, OUT-1 is an output signal of the neural network element 41, and TEACH.
-1 represents the output signal of the teacher signal generating circuit 43, and E2 represents the output of the error square sum generating circuit 44.

Further, the numerical values 1 to 1 attached to the upper part of FIG.
Reference numerals 8 respectively indicate one input pattern, and the input pattern is switched by the broken line portion at the boundary.

Each orthogonal pattern circuit 141 outputs an orthogonal code pattern in synchronization with the clock signal (CLK) output from the clock generation circuit 46. The input signal generation circuit 42 and the teacher signal generation circuit 43 hold the same input pattern and the teacher pattern corresponding thereto while at least each orthogonal code pattern circuit 141 outputs the orthogonal code pattern for one cycle. There is. Therefore, the timing generating circuit 47 detects the timing of one cycle of the orthogonal code pattern from the clock signal and sends the input pattern switching signal to the input signal generating circuit 42.

As is apparent from the configuration of FIG. 5B, a minute orthogonal code pattern is superimposed on the output of each weight / threshold control circuit 45. When the amplitude of the superimposed orthogonal code pattern is D, the error sum of squares generation circuit 4 when the i-th bit of the orthogonal code pattern (i-th clock cycle from the start of the orthogonal code pattern) is output
The output E _i of 4 is approximately

[Equation 9]Is expressed as However, E₀Is when there is no superimposed signal
This is the output of the error sum of squares generation circuit 44. This signal is
Only one of the orthogonal code patterns in the threshold / threshold control circuit 45
It is multiplied by the multiplication circuit 142 and integrated by the integration circuit 143.
It Therefore, in the jth weight / threshold control circuit 45
Integral circuit output change S after one cycle of orthogonal code pattern output _pj
Is

[Equation 10] Becomes However, in the above equation, C is a constant, τ is a clock period, and δ is a Kronecker delta symbol. That is, only the component proportional to ∂E / ∂w _j appears as the change of the integrating circuit 143 due to the property of the orthogonal code pattern. Therefore, if this signal is inverted by the inverter 144 and the output is held by the latch circuit 145 every time the orthogonal code pattern is output for one cycle, the weight or threshold value proportional to ∂E / ∂w _j is corrected. .

In this embodiment, all the circuits operate in synchronization with the clock, so that there is an advantage that they are not easily affected by crosstalk. Also, even if the scale (number of neurons) of the neural network element to be applied changes,
There is an advantage that it can be easily dealt with by correcting the orthogonal code pattern length and adjusting the timing generation circuit 47 accordingly.

Next, a second embodiment of the present invention will be described.

FIG. 7 shows the configuration of the neural network circuit according to the second embodiment of the present invention. FIG. 3A shows the entire neural network circuit 200. In the figure, the same components as those in FIG. 5 are designated by the same reference numerals.

In this embodiment, in addition to the configuration of the first embodiment, the output of the error square sum generating circuit 44 is provided with an integrating circuit 68 and an inverter 6.
9 and a latch circuit 70 are added.

Therefore, the configuration shown in FIG. 9A has an analog neural network element 41, an input signal generation circuit 42 for the neural network element 41, a teacher signal generation circuit 43 corresponding to the signal of the input signal generation circuit 42, and a neural network. An error square sum generation circuit 44 that outputs the sum of squares (square error) of the difference between each output of the network element 41 and each output of the corresponding teacher signal generation circuit 43, the weight / threshold control circuit 55, and the synchronization of the entire system. A clock generation circuit 47 that outputs a clock signal for changing the input pattern of the input signal generation circuit 42 or a timing generation circuit 47 that has a function of controlling the operation timing of the weight / threshold control circuit 55, and integrates the input signal in the time domain. Output the value
The integration circuit 68 reset in synchronization with the timing signal (SYN) which is the output of the timing generation circuit 47, the inverter 69 for inverting the positive and negative of the input signal and outputting the signal, and the signal of the integration circuit 68 in synchronization with the timing signal. Latch circuit 7 having a function of holding and outputting (L-OUT)
It is composed of 0.

FIG. 10B shows the configuration of the weight / threshold control circuit in the neural network circuit 200. Timing signal (SY) output from the timing generation circuit 47
N), an orthogonal code pattern circuit 161 that outputs an orthogonal code pattern signal, a multiplication circuit 162 that outputs a product of two inputs, and an input (SUM- from the multiplication circuit 162 in synchronization with the timing signal (SUM-E). i) is added and the result is latched and output in synchronization with the timing signal of the orthogonal code pattern circuit 161 and the attenuator 16 that attenuates the output of the orthogonal code pattern circuit 161.
4. The addition circuit 165 outputs the sum of the output of the attenuator 164 and the two inputs of the synchronous addition circuit 163.

In this embodiment, the input patterns of the neural network element 61 are switched at high speed, and the orthogonal code pattern of each weight / threshold control circuit 55 is switched every time the input patterns are switched for one cycle.

FIG. 8 shows an example of the timing of each signal according to the second embodiment of the present invention. In the figure, IN-1 to IN-3
Is an input signal supplied from the input signal generating circuit 42, O
UT-1 represents the output signal of the neural network element 41, TEACH-1 represents the output signal of the teacher signal generating circuit 43, E2 represents the output of the error sum of squares generating circuit 44, and INT represents the output of the integrating circuit 68. Further, INT-E is a signal for controlling the operating state of the integrating circuit 68, and when it is at a high level, it is in an integrating operation, and when it is at a low level, it is in a latching state. Further, INT-R is a reset signal for the integrator circuit 68, and when it is at a high level, the integrator circuit 68 is in a reset state and the output is 0. Further, LTCH-E is a control signal of the latch circuit 70. When the level is high, the output of the latch circuit 70 follows the input, and when the level is low, the output is latched.

P-1 to n are output signals from the orthogonal code pattern circuit 161 in each weight / threshold control circuit 55, and SYN.
Is a timing signal indicating the start / end of one cycle of the input pattern. In this case, the rising edge indicates the start of one cycle of the input pattern and the falling edge indicates the end. SUM-1 to n represent outputs of the synchronous addition circuit 163 in each weight / threshold control circuit 55. Further, SUM-E is a control signal of the synchronous addition circuit 163, and the synchronous addition circuit 163 sequentially adds the inputs at the time when SUM-E becomes high level, and outputs the result.

The numbers 1 to m in the upper part of the figure each represent one bit of the orthogonal code pattern, and at the same time the orthogonal code pattern is switched at the boundary portion, the output of the integrating circuit 68 is latched and each weight is weighted. The process is performed in the threshold control circuit 55.

The final output _S'pk of the integrating circuit 68 in the cycle in which each orthogonal code pattern circuit 161 outputs the kth bit is

[Equation 11] Is expressed as Where C is a constant, τ'is the clock period, and D
Is the amplitude of the superimposed orthogonal code pattern, and E ′ ₁ is the output of the error sum of squares generation circuit 44 for the i-th input pattern. The change S ′ _r of the synchronous addition circuit 163 in the r-th weight / threshold control circuit 55 at the stage when all the bits of the 1st to mth orthogonal code patterns are output from this equation is

[0062]

[Equation 12]

It is expressed as As is clear from this equation,
The output change of the synchronous addition circuit 163 is proportional to the sum of ∂E / ∂W _r for all the input patterns in a state where all the bits of the 1st to mth orthogonal code patterns are output. Therefore, each time the output of one cycle of the orthogonal code pattern ends, the output of this synchronous addition circuit 163 is latched,
If the weight or the threshold is modified, the weight proportional to the change ∂E / ∂w _j of the energy function or the threshold is modified.

In this embodiment, the input pattern of the neural network element 41 is switched at high speed, while the weight or the threshold is switched at low speed, as compared with the first embodiment. Therefore, crosstalk between signal lines for inputting weights / thresholds to the neural network element 41 can be significantly reduced. Also,
In this embodiment, since the input patterns are switched at the highest speed, the most efficient learning can be performed even in the case of the high speed signal processing neural network element.

In the inverters used in the first and second embodiments, the correction amount of each weight or threshold is ∂E.
This is to make the phase opposite to the value of / ∂w. Therefore, the insertion position may be any one of the paths from the output of the error sum of squares generation circuit 44 to the addition circuit input for superimposing the orthogonal code pattern in each of the weight / threshold control circuits 45 and 55. The present invention does not particularly limit the insertion position.

Next, a third embodiment of the present invention will be described.

FIG. 9 shows the configuration of a neural network circuit according to the third embodiment of the present invention. In the figure, the same components as those in FIGS. 5 and 7 are designated by the same reference numerals. FIG. 1A shows the overall configuration of the neural network circuit 300. The neural network circuit 300 includes an analog neural network element 41, an input signal generation circuit 42 for generating an input signal to the neural network element 41,
The teacher signal generating circuit 43 for generating a teacher signal corresponding to the signal of the input signal generating circuit 42, each output of the neural network element 41, and the circuit used in the conventional multi-frequency vibration method are used as they are to generate a corresponding teacher signal. An error square sum generation circuit 44 that outputs the sum of squares (square error) of the difference from each output of the circuit 43, a weight / threshold control circuit 65, a clock generation circuit 46, and a clock that outputs a clock signal for synchronization of the entire system. Switching of the input patterns of the generation circuit 46 and the input signal generation circuit 42, or the weight / threshold control circuit 6
5 is composed of a timing generation circuit 47 for controlling the operation timing.

FIG. 11B shows the structure of the weight / threshold control circuit 46. The weight / threshold control circuit 46 shown in the figure is a pulse generation circuit 141 that outputs a pulse signal synchronized with a clock signal or a timing signal, and a gate signal is ON.
Only in the state, the analog switches 142-1 and 142-2 that output the input signal as they are, the integration circuit 144 that amplifies and outputs the difference between the plus (+) side input signal and the minus (−) side input signal, An integration circuit 144 that outputs a value obtained by integrating the input signal in the time domain, a timing signal (LTC
DH-E) is a latch circuit 145 that takes in the signal of the integration circuit 144 in synchronization with it, an attenuator 146 that attenuates the output of the pulse generation circuit 141, and an addition circuit 147 that outputs the sum of the two inputs. .

FIG. 10 shows an example of the timing of each signal according to the third embodiment of the present invention.

In the figure, IN-1 to IN-3 are input signals supplied from the input signal generating circuit 42, and OUT-1 is
Output signal of the neural network element 41, TEAC
H-1 represents the output signal of the teacher signal generating circuit 43, and E2 represents the output of the error square sum generating circuit 44. Further, the synchronization signal SYN is a timing signal indicating the start of a learning operation for one input pattern output from the timing generation circuit 47, and P-1 to n are each weight / threshold control circuit 6.
5, the output signal from the pulse generation circuit 141 in FIG.
-E is a signal that is output from the timing generation circuit 47 and that indicates the timing of latching the output of the integration circuit 144 that is output from the timing generation circuit 47. Also, IN
T-1 to n are integration circuits 1 in each weight / threshold control circuit 65.
44 output.

The numerals 1 to 8 in the upper part of the figure show the periods in which one input pattern is held, and the input patterns are switched at the broken line part of the boundary.

Each pulse generation circuit 141 synchronizes with the clock signal (CLK) supplied by the clock generation circuit 46 from the clock cycle next to the SYN signal, and the first pulse generation circuit 141 outputs the first clock cycle, 2 The second pulse generation circuit 141 outputs the pulse signal every one clock cycle, such as the second clock cycle. Input signal generation circuit 42
The teacher signal generation circuit 43 holds the same input pattern and the teacher pattern corresponding to the same input pattern while all the pulse generation circuits 141 are outputting the pulse signals.
For this reason, the timing generation circuit 47 outputs LTCCH- after the pulse signal of the last pulse generation circuit 141 is output.
E signal is sent out and the integrator 1 of each weight / threshold control circuit 65
By latching the output of 44, the weight or threshold value is updated, and an input pattern switching signal is sent to the input signal generation circuit 42 to switch the input pattern. After that, the timing generation circuit 47 again sends the SYN signal to each weight / threshold control circuit 65, whereby each weight / threshold control circuit 65 starts the operation for the next new input pattern.

The synchronization signal (SYN) from the timing generation circuit 47 is supplied to the analog switch 142-1 of each weight / threshold control circuit 65 to close it. Therefore, the error sum of squares signal E2 is input to the plus (+) side of the differential amplifiers 143 in all the weight / threshold control circuits 65 and to the integrator 144. On the other hand, the i-th weight
When the pulse generation circuit 141 in the threshold control circuit 65 generates the pulse signal P-i, this pulse signal is the analog switch 142-2 in the i-th weight / threshold control circuit 65.
Supplied to and closed.

Therefore, the sum of squared error signal E2 is input to the minus (−) side of the differential amplifier 143 in the i-th weight / threshold control circuit 65 and to the integrator 144. By the way, the synchronization signal (SY
S) At the time of output, all pulse generation circuits 141 are in a state of not outputting pulses, and at the time of P-i signal output, only the output of the i-th pulse generation circuit 141 is superimposed on the corresponding weight or threshold. It is in a state of being. Therefore, if both the pulse lengths of the SYN signal and the P-i signal are equal to the clock cycle τ, the output change E ₀ of the integration circuit 144 and the P-i signal in the SYN signal output period in the i-th weight / threshold control circuit 65. The output change E _i of the integrating circuit 144 during the output period is

[0075]

[Equation 13]

It is expressed as However, E is the E2 signal output when the synchronization signal (SYN) is output from the timing generation circuit 47, and C is a constant. From this equation, the change ΔE _i of the integrator output latched by the latch circuit 145 is

[0077]

[Equation 14]

It is represented by That is, the output of the latch circuit 145 is directly corrected as it is in proportion to −∂E / ∂w _i . Therefore, the learning operation of the neural network is realized by supplying the output of the latch circuit 145 to the neural network element 41 via the adding circuit 147 as a weight or as a threshold signal.

In this embodiment, all the circuits operate in synchronization with the clock, so that there is an advantage that they are not easily affected by crosstalk. Further, even if the scale of the neural network element to be applied (the number of neurons) changes, there is an advantage that it can be easily dealt with by adjusting the timing circuit 47 corresponding to the number of neurons.

Next, a fourth embodiment of the present invention will be described.

FIG. 11 shows a neural network circuit according to the fourth embodiment of the present invention. In the figure, the same components as those in FIG. 9 are designated by the same reference numerals.

FIG. 10A shows a neural network circuit. The neural network circuit 400 includes an analog neural network element 61, an input signal generating circuit 62 for the neural network element 61, a teacher signal generating circuit 63 for generating a teacher signal corresponding to a signal of the input signal generating circuit 62, and a neural network element 61. An error square sum generation circuit 64 that outputs the sum of squares (square error) of the difference between each output and each output of the corresponding teacher signal generation circuit 63, a weight / threshold control circuit 75, and a clock signal for synchronizing the entire system. , A timing generation circuit 67 having a function of switching the input pattern of the input signal generation circuit 62 or a timing generation circuit 67 for controlling the operation timing of the weight / threshold control circuit 75, and outputting a value obtained by integrating the input signal in the time domain. Integration that is reset in synchronization with the timing signal (INT-R) It constituted by road 68.

FIG. 11B shows the structure of the weight / threshold control circuit. The weight / threshold control circuit 75 includes a pulse generation circuit 261 that outputs a pulse signal synchronized with the timing signal (INT-E), an analog switch 262-1 that directly outputs the input signal only when the gate signal is in the ON state,
262-2, a differential amplifier 263 that amplifies and outputs the difference between the plus (+) side input signal and the (−) side input signal, and an integrating circuit 26 that outputs a value obtained by integrating the input signal in the time domain.
4. Latch circuit 2 that takes in the signal of the integration circuit 264 in synchronization with the timing signal (LTCH-E) and holds it
65, an attenuator 266 for attenuating the output of the pulse generation circuit 261, and an adder circuit 267 for outputting the sum of the two inputs of the attenuator 266 and the latch circuit 265.

In this embodiment, switching of the input pattern to the neural network element 61 is performed at high speed, and a pulse signal is sequentially generated from one of the weight / threshold control circuits 75 every time the input pattern is switched for one cycle. It is a method to let.

FIG. 12 shows an example of the timing of each signal in the fourth embodiment of the present invention. In the figure, IN1 to IN3
Is an input signal supplied from the input signal generation circuit 62 and is synchronized with the clock signal (CLK) of the clock generation circuit 66. Further, OUT-1 is an output signal of the neural network element 61, TEACH-1 is an output signal of the teacher signal generating circuit 63, and E2 is an error square sum generating circuit 64.
, INT represents the output of the integration circuit 68, respectively.
Further, INT-E is a signal for controlling the operating state of the integrating circuit 68, and when it is at a high level, it is in an integrating operation, and when it is at a low level, it is in a latching state. The INT-E signal is also used as a timing signal for each weight / threshold control circuit 75. INT-R is a reset signal for the integrator circuit 68, and when it is at a high level, the integrator circuit 68 is in a reset state and the output is 0.

P-1 to n are each weight / threshold control circuit 75.
It is an output signal from the inside pulse generation circuit 261. SU
M-E is the gate signal of the analog switch 262-1 in each weight / threshold control circuit 75, and DIFF-E _i is the analog switch 262- in the i-th weight / threshold control circuit 75.
2 gate signal. LTCH-E is a latch circuit 27
5 is a control signal, and the latch circuit 265 is at a high level.
Output follows the input, and when low, the output is latched. Further, INT-1 to n represent outputs of the integrating circuit 164 in each weight / threshold control circuit 75.

Further, the numerical values 0 to n in the upper part of the figure each indicate one cycle of switching the input pattern, and in the cycle 0, the outputs of the pulse generation circuits 261 in all the weight / threshold control circuits 75 are 0. In other cycles, the pulse generation circuit 261 in the corresponding weight / threshold control circuit 75 is
Only outputs a pulse.

[0088] If the final output (INT-R received immediately before the output) the E _'0 of the integrating circuit 68 in the period 0 above,
In the cycle 0, since the output of all the pulse generation circuits 262 is 0,

[0089]

[Equation 15]

It becomes However, C is a constant, and T1, T2. Are the input start time and end time of the input pattern sequence, respectively. E is an E2 signal output when the outputs of all the pulse generation circuits 261 are 0. On the other hand, in the cycle i, the pulse output of the i-th pulse generation circuit 261 is superimposed on the corresponding weight or threshold signal w _i . Therefore,
The final output E _'i of the integration circuit 68 in the period i is

[0091]

[Equation 16]

It is represented as However, D is the magnitude of the pulse signal to be superimposed. Therefore, if the pulse widths of the SUM-E signal and all DIFF-E _i signals are equal to each other, the latch circuit 2 in the i-th weight / threshold control circuit 75 is
The change ΔE ′ _{i in} the output of the integrating circuit 264 latched by 65 is

[0093]

[Equation 17]

It becomes Where C'is a constant and τ'is SU
It is the pulse width of the ME signal and the DIFF-E _i signal.
As is clear from this equation, the change ΔE ′ _{i in} the output of the latch circuit 265 is proportional to −∂E ′ ₀ / ∂w _i . Therefore, if the output of the latch circuit 265 is supplied to the neural network element 61 via the adder circuit 267 as a weight or a threshold signal, the desired learning operation can be realized.

In this embodiment, the input pattern of the neural network element is switched at a higher speed than in the third embodiment, while the weight or the threshold is switched at a lower speed. Therefore, the weight of the neural network element and the crosstalk between the signal lines for inputting the threshold value can be greatly reduced. Further, in this embodiment, since the input patterns are switched at the highest speed, the most efficient learning can be performed in the case of the high speed signal processing neural network element.

In the first and second embodiments described above, one orthogonal coded pulse train is assigned to each weight or threshold control circuit, and this pulse train is superimposed on the corresponding weight or threshold output, resulting in the error signal generation. To measure (multiply and integrate) the correlation between the error signal output from the circuit (orthogonal coded pulse train equal to the number of weights or thresholds to be controlled is superimposed) and the assigned orthogonal coded pulse train. Detects only the change amount of the error signal due to the influence of the superposition of the assigned orthogonally encoded pulse train.
In this method, since it is necessary to generate as many orthogonalized coded pulse trains as the number of weights or thresholds to be controlled, the circuit becomes complicated, but ∂E / ∂w can be detected with high accuracy.

Further, in the third and fourth embodiments, the pulse signals shifted in time are assigned to the respective weight or threshold control circuits, and the pulse signals are superposed on the corresponding weight or threshold outputs, and as a result, This is a method of observing how much the error signal output from the error signal generation circuit changes due to superposition of pulse signals. In this case, since nothing is superimposed on the weight to be observed or the output of the weight or threshold control circuit other than the threshold control circuit, there is no need to perform the correlation operation as in the first and second embodiments. ∂E / from the difference between the error signals with and without pulse superposition
The circuit for detecting ∂w can be simplified.

Further, in the first and third embodiments, the orthogonal coded pulse train or pulse signal for one period is superimposed, and ∂
In this method, the weight or threshold value is corrected for each neural network input by holding the input to the neural network while detecting E / ∂w. In this method, since learning is completed for each neural network input, it can be applied to random inputs.

In the second and fourth embodiments, the orthogonal coded pulse train to be superposed or one bit output of the pulse signal is held while all the neural network inputs are completed. By repeating this operation for the number of bits of the pulse signal, the total or average of ∂E / ∂w for all neural network inputs is observed. This method requires a means for repeatedly generating the same input pattern, but it is possible to switch overlaid signals of overwhelmingly more weights or threshold control circuit outputs than at the input at a low speed. It is possible to significantly reduce the problem of crosstalk between them.

[0100]

As described above, according to the present invention, the high speed of the analog neural network element is not hindered,
In addition, it is possible to realize a neural network learning circuit that is not easily affected by crosstalk.

[Brief description of drawings]

FIG. 1 is a first principle configuration diagram of the present invention.

FIG. 2 is a second principle configuration diagram of the present invention.

FIG. 3 is a third principle configuration diagram of the present invention.

FIG. 4 is a fourth principle configuration diagram of the present invention.

FIG. 5 is a configuration diagram of a neural network circuit according to a first embodiment of the present invention.

FIG. 6 is a diagram showing the timing of each signal in the first embodiment of the present invention.

FIG. 7 is a configuration diagram of a neural network circuit according to a second embodiment of the present invention.

FIG. 8 is a diagram showing the timing of each signal in the second embodiment of the present invention.

FIG. 9 is a configuration diagram of a neural network circuit according to a third embodiment of the present invention.

FIG. 10 is a diagram showing the timing of each signal in the third embodiment of the present invention.

FIG. 11 is a configuration diagram of a neural network circuit according to a fourth embodiment of the present invention.

FIG. 12 is a diagram showing the timing of each signal in the fourth embodiment of the present invention.

FIG. 13 is a configuration diagram of a three-layer neural network and a configuration of a neuron element.

FIG. 14 shows a configuration example of an analog neural network element.

FIG. 15 is a diagram for explaining a neural network learning circuit based on the multi-frequency vibration method.

[Explanation of symbols]

11 signal input terminal 12 input layer 13 intermediate layer 14 output layer 15 signal output terminal 16 neuron element 21 signal input terminal 22 weight input terminal 23 signal output terminal 24 multiplication circuit 25 threshold circuit 26 adder circuit 27 nonlinear function generating circuit 31, 41, 61 analog neural network element 32, 42, 62 input signal generation circuit 33, 43, 63 teacher signal generation circuit 34, 44, 64 error square sum generation circuit 35 weight / threshold control circuit 45, 55, 65, 75 weight / threshold control Circuit 46, 66 Clock generation circuit 47, 67 Timing generation circuit 68, 135, 144, 264 Integration circuit 69, 134 Inverter 70 Latch circuit 100, 200, 300, 400 Neural network circuit 131 Oscillation circuit 132 Multiplication circuit 133 Low-pass filter circuit 36 addition circuit 141 pulse generation circuit 142 analog switch 143 differential amplifier 145 latch circuit 146 attenuator 147 adder 161 orthogonal code pattern circuit 162 multiplication circuit 163 synchronous addition circuit 164 attenuator 165 addition circuit 261 pulse generation circuit 262 analog switch 263 difference Dynamic amplifier 264 Integration circuit 265 Latch circuit 266 Attenuator 267 Adder 1001 Neural network 1002 Input signal generating means 1003 Teacher signal generating means 1004 Error signal generating means 1005 Orthogonal code pattern generating means 1006, 1060, 1061, 1062, 1063
Integration means 1007 Parameter control means 1008, 1080, 1081, 1082 Synchronization means 1050, 1051 Pulse signal generation means 1061 1090 Addition means

Front page continuation (72) Inventor Masafumi Koga 1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation (72) Takao Matsumoto 1-1-6 Uchiyuki-cho, Chiyoda-ku, Tokyo Nihon Telegraph Phone Co., Ltd.

Claims (4)

[Claims] 1. A plurality of neural network input ports, at least one neural network output port, a plurality of processing elements for performing weighted addition and nonlinear processing on an input signal, and a plurality of wirings for connecting the processing elements to each other. An element, an input signal generating means for generating an input signal to be learned in the neural network, a teacher signal generating means for generating a teacher signal corresponding to the input signal, and an output signal of the neural network during learning of the neural network In a learning circuit connected to a neural network including an error signal generating means for generating an error signal by comparing with the teacher signal, n orthogonal code patterns are respectively P ₁ , P ₂ , ..., P.
_n, and the array of the orthogonal patterns P _i is P _i = {p _i1 ,
If p _i2 , ..., P _im } (p _ik = ± 1, 1 ≦ k ≦ m), then each orthogonal pattern is given by An orthogonalization code pattern generating means for generating an orthogonalization code pattern satisfying the following, an integrating means for integrating a result obtained by multiplying an output of the error signal generating means by the orthogonalization code pattern, and an output of the integrating means. Parameter control means for changing the input of the weight or the threshold value of the neural network, and the input signal to the neural network and the teacher signal store their respective values for at least one cycle of the orthogonalization code pattern. A neural network learning circuit, comprising: a synchronizing means for synchronizing the start of one cycle of the orthogonalization code pattern and the switching of the input signal to the neural network. 2. A plurality of neural network input ports, at least one neural network output port, and a plurality of processing elements that perform weighted addition or non-linear processing on input signals, and the processing elements are mutually connected. A plurality of elements, an input signal generating means for generating an input signal to be learned, a teacher signal generating means for generating a teacher signal corresponding to the input signal, and an output signal of the neural network during learning of the neural network , A learning circuit connected to a neural network including an error signal generating means for generating an error signal with the teacher signal, m elements of n pulse trains P _i synchronized with the clock signal are represented by P _ik (1 ≤ i ≤ n, 1 ≤ k ≤ m, P _ik = ± 1) The orthogonalization code pattern generating means for generating an orthogonalization code pattern that satisfies the following, and the time required for all inputs of the input signals to be learned by the neural network are defined as one cycle, and the output of the error signal generating means is defined as one cycle. An integrating means for integrating in the time domain during the period, an adding means for adding the result of multiplying the output of the integrating means by the output of the orthogonalization code pattern generating means for each pulse cycle, and the adding means. Parameter control means for changing the weight or the threshold value input of the neural network according to the output of the neural network and the start of the one cycle and the switching of the orthogonalization pattern are synchronized, and the orthogonalization is performed at least during the period of the one cycle. A learning circuit for a neural network, comprising: a synchronization means for holding a pattern value. 3. A plurality of network input ports, at least one neural network output port, a plurality of processing elements that perform weighted addition and non-linear processing on an input signal, and a plurality of wiring elements that interconnect the processing elements. An input signal generating means for generating an input signal to be learned and a teacher signal generating means for generating a teacher signal corresponding to the input signal; and an output signal of the neural network and the teacher signal during learning of the neural network. In a learning circuit connected to a neural network including an error signal generating means for generating an error signal by comparison, a plurality of pulse signals synchronized with a clock signal, and the pulse widths of the individual pulse signals are equal to each other, and One pulse signal of the plurality of pulse signals at the same time A pulse signal generating means for outputting only the error signal, an integrating means for integrating the output of the error signal generating means in the time domain in synchronization with the pulse signal output by the pulse signal generating means, and an output of the integrating means. Parameter control means for changing the weight or threshold value input of the neural network, and the input signal and the teacher signal to the neural network have respective values during at least the time required to output all of the plurality of pulse signals. And a synchronization circuit for holding the start of the output of the plurality of pulse signals and the switching of the input signal to the neural network. 4. A plurality of processing elements that perform weighted addition and non-linear processing on input signals of a plurality of network input ports and at least one neural network output port, and a plurality of processing elements that mutually connect the processing elements. Connection element, input signal generating means for generating an input signal to be learned, teacher signal generating means for generating a teacher signal corresponding to the input signal, an output signal of the neural network and a teacher during learning of the neural network. In a learning circuit connected to a neural network including an error signal generating means for comparing an error signal to generate an error signal, a time required for all inputs of an input signal to be learned by the neural network is defined as one cycle, Integrating the output of the error signal generating means in the time domain during the period of the one cycle; Integrating means, pulse signal generating means for generating a plurality of pulse signals synchronized with the clock signal and having the same pulse width so that they do not overlap in time, and the output of the first integrating means is synchronized with the pulse signal. Second integration means for performing integration according to the gate signal to be added and adding the integration result and the pulse signal, and parameter control means for changing the weight or threshold input of the neural network according to the output of the addition means, Synchronizing the start of one cycle with the switching of the pulse signal,
A neural network learning circuit comprising: a synchronizing means for holding the value of the pulse signal at least during the period of the one cycle.