JPH06310311A - Semiconductor integrated circuit element and its bias adjusting method - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit element which can be manufactured at low costs, whose usage method is easy and which constitutes an electronic circuit such as an amplifier circuit by solving the problem of the complication of a biascurrent adjusting process for the semiconductor integrated circuit element which is used mainly for a mobile communication operation or the like. CONSTITUTION:The grounding side of a voltage dividing resistance 2 which constitutes a bias current is provided with a resistance array 8 which can be fused and adjusted by a laser trimmer. A probing operation is performed to an element on a wafer. While a voltage is applied and a current is being monitored, the laser trimmer which has been installed at the upper part of a prober is moved, and the resistance array 8 is fused and adjusted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to high frequency communication equipment for amplification,
The present invention relates to a semiconductor integrated circuit element essential for oscillation.

[0002]

2. Description of the Related Art In recent years, communication devices such as mobile phones, car phones, cordless telephones, etc. have been improved in performance.

In particular, in the case of these mobile communications, there is a strong demand for miniaturization, and semiconductor devices which are used parts are also rapidly miniaturized. In this trend, what has conventionally used a module having a hybrid structure using discrete elements is becoming an integrated circuit having a monolithic or multi-chip structure. In particular, monolithic microwave integrated circuits for power amplifiers using compound semiconductors centering on GaAs (hereinafter,
The MMIC (abbreviated as MMIC) is most suitable for mobile communication because of its high-frequency characteristics and high power utilization efficiency, and has recently been receiving attention.

FIG. 7 shows a conventional GaAs field effect transistor.
The circuit diagram of the power amplifier MMIC using (FET) is shown. 1 is a FET, 2 is a voltage dividing resistor, 3 is a matching circuit, 4
Is a gate voltage application terminal, 5 is a drain voltage application terminal, 6
Is a high frequency input terminal, and 7 is a high frequency output terminal. FET
Reference numeral 1 constitutes a one-stage amplifier circuit, and the high frequency input / output terminals 6 and 7 are adjusted so as to be matched to 50Ω in the frequency band used. Since the bias condition of the FET1 is determined by the two resistors of the voltage dividing resistor 2 fixed to the optimum value in design, it is used as an amplifier circuit only by applying the drain voltage Vdd and the gate voltage -Vgg to this MMIC. it can.

FIG. 8 shows another circuit diagram of a conventional power amplifier MMIC using a GaAs FET, which is a gate voltage applying terminal 4 so that a bias condition can be adjusted from the outside.
Is withdrawn. FET1 is applied to the gate voltage applying terminal 4.
Predetermined characteristics can be obtained by applying an optimum bias voltage for

[0006]

However, in the configuration as shown in FIG. 7, the bias condition is fixed by the voltage dividing resistor 2, and on the other hand, the power utilization efficiency and the gain are increased because the characteristics of the FET 1 vary. , Bias cannot be set stably at the optimum points of characteristics such as distortion and adjacent channel leakage power suppression ratio. Therefore, there are drawbacks that the characteristics of the MMIC as an amplifier circuit vary greatly and the yield is low.

Further, in the structure as shown in FIG.
Since the bias condition can be controlled by the gate voltage applying terminal 4 of the external terminal, the condition can be set to the best condition characteristically, but on the other hand, the device manufacturer using this needs to adjust the bias individually, so that the man-hours and the manufacturing cost are increased. Was increasing. Further, it is necessary to mount a component for bias adjustment such as a variable resistor, which has a drawback of occupying a wiring board space to be mounted.

In view of the above-mentioned drawbacks, it is an object of the present invention to provide a semiconductor integrated circuit device in which a voltage dividing resistor can be adjusted inside the device after a wafer is manufactured and a bias adjusting method therefor.

[0009]

In order to solve the above-mentioned problems and to achieve the object, the invention of claim 1 of the present invention is to optimize the bias condition by melting the metal wiring part of the resistor arrayed by the laser trimmer. Forming a semiconductor integrated circuit. According to the second aspect of the invention, a resistance array for resistance adjustment is formed between the gate of the FET and the ground. Claim 3
In the invention of (1), a mark for pattern recognition is formed on the fusing part by the laser trimmer. According to the invention of claim 4, the resistance adjustment by the laser is performed on-wafer while monitoring the actual operating current. According to a fifth aspect of the invention, the resistance of the semi-finished hybrid semiconductor integrated circuit device is adjusted by a laser on an operation test device while monitoring the actual operation current.

[0010]

According to the present invention, an array of resistors that can be blown and adjusted by a laser trimmer is provided on the ground side of a voltage dividing resistor that constitutes a bias circuit, and this semiconductor integrated circuit device is probed on-wafer to apply a voltage. Then, a laser trimmer provided on the upper part of the prober is moved while monitoring the current to adjust the fusing of the resistor array, whereby an inexpensive and easy-to-use semiconductor integrated circuit device can be obtained.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a GaAsFE according to an embodiment of the present invention.
The circuit diagram of MMIC for power amplifiers using T is shown. In FIG. 1, the same components as those in FIGS. 7 and 8 are designated by the same reference numerals, and the description thereof will be omitted. Reference numeral 8 in the drawing is a resistor array which serves as a voltage dividing resistor according to the present invention. A resistor array 8 is inserted between the gate voltage application terminal 4 of the FET 1 and the ground. As shown in the perspective view of the main part of FIG. 2, the ground side wiring of each resistance element of the resistance array 8 is adjusted by melting (cutting) with the laser beam 9 of the laser trimmer, and the minimum bias condition for the FET 1 is set. give. The bias condition of the FET 1 is an important parameter that determines basic characteristics such as gain, power efficiency, distortion, and adjacent channel leakage power as an amplifier, and therefore it must be adjusted as accurately as possible. Therefore, in the present embodiment, the laser trimmer cutting is performed in four steps as an example.

Also, in order to adjust the resistance effectively, the resistance of the first cut resistance should be lower than that of the IC.
The aspect ratio of the resistance pattern is small. By arranging the values of the individual resistors in a geometric progression, the gate voltage can be changed in voltage steps at equal intervals.

FIG. 3 is a pattern diagram in which the equivalent circuit of FIG. 1 is directly patterned into an IC. Resistor wiring part 8 of the resistor array 8 which is cut by the laser trimmer
r is thinner than the other portion 8R, and serves as a mark for pattern recognition for accurately applying the laser beam, and at the same time reduces the generation of scraps during fusing.

FIG. 4 is a schematic sectional view taken along the line AA 'of FIG.
Reference numeral 10 is a protective film, 11 is a metal wiring layer, 12 is an interlayer film, 13 is a resistance formation region by impurity diffusion, and 26 is a GaAs substrate. In this way, the protective film 10 above the wiring portion of the resistor that is cut by the laser beam 9 of the laser trimmer is removed. This makes it possible to easily cut the wiring, and the metal scraps at the time of fusing cause insufficient cutting,
It is possible to prevent the occurrence of defects by the melted fragments of the metal adhering to other portions.

Here, the cutting portion is the ground side of the resistor placed between the gate and the ground. By fixing the voltage dividing resistance between the gate and power supply and not adjusting it, it becomes easy to monitor the gate current by measuring the voltage between the -Vgg terminal (5) and RFin terminal (6). Further, by making the cutting portion as close to the ground (GND) side as possible, the variation in impedance due to cutting is minimized.

FIG. 5 is a view for explaining a bias adjusting method for an on-wafer semiconductor integrated circuit device in one embodiment of the present invention. 14 is a wafer prober, 15 is a probe needle, 16 is an operating current detection circuit, 17 is a comparator, 18 is a moving stage of the laser trimmer head 22, 19 is an XY stage, 20
Is a semiconductor integrated circuit device to be inspected, 21 is an MMIC wafer to be inspected, and 22 is a laser trimmer head. Computer-controlled 0.5 mm in the X-axis direction above the wafer prober 14
A laser trimmer head 22 is provided that can move a span of about a degree in the direction of arrow aa with high precision.

As a result, the operating voltage is applied to the semiconductor integrated circuit element 20 to be tested on the wafer probe bar 14, and the operating current is monitored by the probe needle 15 while the operating current detecting circuit is being operated.
16 detects the operating current, comparator 17 compares it with the reference current,
Based on the comparison output, the movement of the moving stage 18 of the laser trimmer head 22 is controlled, and the laser trimmer head 22 is caused to emit light so that the cutting of the resistor array 8 of the semiconductor integrated circuit element 20 to be tested proceeds in sequence. Then, when the operating current is closest to the optimum value, the movement of the laser trimmer head 22 is stopped and the light emission is stopped. By performing this bias adjustment process at the same time as the inspection process, the time of the adjustment process can be reduced.

FIG. 6 is a diagram for explaining a bias adjusting method for a semiconductor integrated circuit device having a hybrid structure according to an embodiment of the present invention. Reference numeral 23 is an integrated circuit element chip having no adjustment resistor, 24 is a package, and 25 is a contact pin. A semi-finished product in which the semiconductor integrated circuit element 20 having a resistance for adjustment which is die-bonded to the package 24 and the integrated circuit element chip 23 having no resistance for adjustment are wire-bonded to each other or to the lead portion of the package 24. It is in the state of. In this state, a characteristic inspection device having a laser trimmer head 22 which can be moved by computer control at the top is applied.

In this characteristic inspection, necessary voltages, currents and signals are applied from the contact pins 25 of the characteristic inspection device to inspect various characteristics and simultaneously adjust the bias. That is, while the operating current of the semiconductor integrated circuit element to be tested is monitored, the laser trimmer head is caused to emit light to sequentially cut the resistor array, and the movement of the laser head is stopped when the operating current value is closest to the optimum value. At the same time, the light emission is stopped.

Since this bias adjustment process can be performed simultaneously with the inspection process, a great reduction in the number of steps can be realized. Further, since it is possible to adjust the bias for hybrid semiconductor integrated circuit elements including a plurality of chips such as an active element chip and an adjustment passive element chip, it is expected to improve the overall yield. Further, a multifunctional semiconductor integrated circuit device can be easily constructed and adjusted to the optimum conditions.

[0021]

As described above, in the semiconductor integrated circuit device according to the present invention, the semiconductor integrated circuit device having the voltage dividing resistance that is melted and adjusted by the laser trimmer is formed on the surface of the semiconductor device substrate. Stable bias adjustment can be performed by using the metal wiring portion of the voltage dividing resistor in the form of an array that is fused by the laser beam. By providing a mark for pattern recognition on the fusing part of the voltage dividing resistor by the laser trimmer, the laser trimmer head provided on the upper part of the voltage dividing resistor is moved while automatically monitoring the current actually flowing on the wafer draw bar. The bias can be adjusted by fusing the resistance. It is also possible to perform bias adjustment by simultaneously performing characteristic inspection and resistance adjustment by fusing of the voltage dividing resistors on the semi-finished hybrid semiconductor integrated circuit device.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a power amplifier MMIC using a GaAs FET according to an embodiment of the present invention.

FIG. 2 is a perspective view of a main part of FIG. 1 for explaining a method of adjusting a voltage dividing resistance using a laser trimmer according to the present invention.

FIG. 3 is a pattern diagram in which the equivalent circuit of FIG. 1 is directly patterned into an IC.

FIG. 4 is a schematic sectional view taken along the line AA ′ of FIG.

FIG. 5 is a diagram illustrating an on-wafer semiconductor integrated circuit device bias adjusting method according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating a bias adjusting method for a semiconductor integrated circuit device having a hybrid configuration according to an embodiment of the present invention.

FIG. 7: M for power amplifier using conventional GaAs FET
It is a circuit diagram of MIC.

FIG. 8: M for power amplifier using conventional GaAs FET
It is another circuit diagram of MIC.

[Explanation of symbols]

1 ... Field effect transistor (FET), 2 ... Voltage dividing resistor, 3 ... Matching circuit, 4 ... Gate voltage applying terminal, 5 ...
Drain voltage application terminal, 6 ... High frequency input terminal (RFi
n), 7 ... High frequency output terminal (RFout), 8 ... Resistor array, 9 ... Laser beam, 10 ... Protective film, 11 ... Metal wiring layer, 12 ... Interlayer film, 13 ... Resistance forming region, 14 ... Wafer prober, 15 … Probe needle, 16… Operating current detection circuit, 17… Comparator, 18… Moving stage, 19… X
-Y stage, 20 ... Semiconductor integrated circuit device under test, 21 ...
Tested MMIC wafer, 22 ... Laser trimmer head,
23 ... Integrated circuit element chip without adjusting resistor, 24 ... Package, 25 ... Contact pin, 26 ... GaAs substrate.

Claims (5)

[Claims] 1. A voltage dividing resistor for determining a bias condition of a semiconductor integrated circuit element forming an amplifier circuit is composed of a resistor array connected in parallel to a surface of a semiconductor element substrate, and each of the resistor arrays of the resistor array. A semiconductor integrated circuit device characterized in that a metal wiring portion of a resistor is sequentially blown by a laser trimmer to adjust the resistance and the bias condition is adjusted to an optimum condition. 2. The semiconductor integrated circuit element according to claim 1, wherein the voltage dividing resistor is provided between the gate of the field effect transistor which is an active element and the ground. 3. A metal wiring portion which is blown by a laser beam of a voltage dividing resistor has a mark for pattern recognition, and at the same time, the protective film provided on the surface of the semiconductor element is removed. The semiconductor integrated circuit device according to claim 1, which is characterized in that. 4. The resistance adjustment is performed on-wafer while controlling the movement of a laser trimmer head provided on a wafer draw bar to actually monitor a current flowing through a semiconductor element. Bias adjusting method for semiconductor integrated circuit device. 5. A hybrid semiconductor integrated circuit device comprising a plurality of chips, the semiconductor integrated circuit device having the voltage division resistance according to claim 1, 2 or 3 on at least one of the chips, after die-bonding and wire-bonding, 2. The semiconductor integrated device according to claim 1, wherein the resistance adjustment is performed on the device while controlling the movement of the laser trimmer provided on the operation test device to monitor the current actually flowing through the semiconductor element before the sealing. Circuit element bias adjustment method.