JPH0630500B2 - General-purpose access method for high-speed time division multiplex transmission line - Google Patents

Description

TECHNICAL FIELD The present invention is used as a high-speed time division multiplex bus for a transmission control device of a digital network, and a line or packet data having a capacity of 64 kb / s × n can be transmitted to the same transmission line. The present invention relates to a general-purpose access method for a high-speed time division multiplex transmission line used for accommodating.

2. Description of the Related Art Conventionally, this type of data transmission apparatus has been realized in an opposed transmission line, and in loop type and bus type networks, multiplexing of low-speed data of 64 kb / s or less has been the center.

Problems to be Solved by the Invention Therefore, in the above-mentioned conventional data transmission control device, since different types of lines that can be accommodated in the same transmission line are mainly low-speed data, 1.
There is a problem that general-purpose access of 64 kb / s × n circuits including high-speed circuits such as 5 Mb / s cannot be performed, and that different transmission modes such as packet transmission cannot be accommodated in the same transmission path.

The present invention solves such conventional problems,
It is possible to provide an excellent data transmission control device in which various lines can access loop type, bus type, and opposite type transmission lines.

Means for Solving the Problems In order to achieve the above object, the present invention provides a parallel transmission and reception data signal and a frame header timing signal with a delay of several bytes for accessing a loop type and a bus type. And a reception and transmission clock, and a time slot address signal that can be added if necessary,
It is provided with a transmission permission signal for various access devices to be accommodated and a transmission permission signal for all devices, and these signals are configured in a bus format.

Effect of the Invention The present invention, which is configured as described above, has an effect that it can be applied to a transmission line of any type or a line with a transmission capacity, and that packet transmission can be performed using an arbitrary time slot.

Embodiment FIG. 1 shows the structure of an embodiment of the present invention. In FIG. 1, reference numeral 11 is a relay station apparatus connected to a transmission line to perform serial / parallel conversion of data and frame synchronization, and includes a reception data bus 12, a transmission data bus 13, and timing signals and clocks for time slot addresses. Control signal bus 14 is provided as a signal inside the node device. Reference numerals 15, 16 and 17 are line control devices for transmitting and receiving data using these time division multiplexed buses. Second
The figure shows a timing chart of the control signal bus 14. In FIG. 2, a is a slot address signal, which is 8K as a pulse having a width of one cycle of the reception clock b.
Repeated in cycles. d is a reception CRV (Code Rule Viola)
C) in the transmission code between the relay terminal devices 11.
When RV is applied, the code is detected and provided to the control signal bus 14 as a pulse width for one cycle of the reception clock b. e and f are a synchronous data receivable status and an asynchronous data receivable status, respectively, and each data can be accessed when these signals are in the enabled state. The two signals have mutually opposite logics. g is a CRC (Cyclic redundancy check) error display, and CR is included in the reception information of a specific area between the relay terminal devices.
This indicates that a C error has occurred. i and j
Is a synchronous data transmission request and an asynchronous data transmission request, respectively.
Can send each data to the relay transmission device 11.

Next, the operation of the above embodiment will be described. In the above embodiment, when the relay terminal equipment 11 establishes the frame synchronization by the transmission between the relay terminal equipments, one-eighth of the transmission / reception clock of the transmission path is used as the reception clock b of the time division multiplexing bus, and A frame synchronization timing signal is provided on the bus as a slot address synchronization signal a. At that time, if CRV is detected, the fact is transmitted to the bus. Usually, CRV is used for frame synchronization. When the time slot areas of the synchronous data and the asynchronous data are mixed, the information is detected from the frame header, and the statuses e and f indicating the access right of each area are provided on the bus. On the other hand, the line control devices 15, 16, 1
7 refers to this status signal and refers to the time slot address and slot synchronization signal 2 assigned to itself.
The data C on the reception data bus 12 can be taken into the own device by detecting a match between 1 and the value counted by the reception clock b. Similarly, if there is data to be sent to the relay terminal station device 11, each of the line control devices 15, 16 and 17 will delay that data at a timing delayed by four reception clocks from the reception time slot position assigned to itself. h is sent to the transmission data bus 13. At the same time, it is possible to make a transmission request by transmitting a synchronous or asynchronous data transmission request i or j onto the bus.

In addition to these control signals related to data transmission / reception, a CRV generation request signal for generating a CRV in a frame to be used as a frame synchronization or a packet data delimiter, a status signal indicating acquisition or release of a packet data transmission right, and a frame header transmission This control signal bus is configured by a request signal, a switching signal between the reception clock and the internal clock, etc., and facilitates standardization and generalization of the time division multiplex bus. The reception data bus 11 and the transmission data bus 1
Reference numeral 3 is an 8-bit parallel data bus. As described above, according to the above-described embodiment, when the relay terminal station device 11 establishes frame synchronization, the time division multiplexing bus obtains the specified timing,
Serial data transfer rate of 8 for serial-parallel conversion of data
Arbitrary by allocating a time slot with a transmission capacity of 64 kb / s × n, which has the effect of time-division multiplexing on the bus at a speed of one-half and can be used in advance by the line control devices 15, 16, 17. It is possible to support a line with a capacity of. In the above embodiment, the time slot number is obtained by each line control device counting clocks, but the time slot address may be provided to the time division multiplex bus by the relay terminal station device 11. In this case, 1
It is possible to obtain an effect that can be configured with one time slot counting circuit.

EFFECTS OF THE INVENTION As is apparent from the above embodiment, the present invention is capable of accommodating synchronous and asynchronous lines having various transmission capacities in the same time division multiplex bus, and various terminals and transmission devices. , It has the advantage that a switching device can be connected. Further, since the signals are in the bus format, there is an effect that a plurality of line control devices can be connected.

[Brief description of drawings]

FIG. 1 is a block diagram of a general-purpose access method for a high-speed time division multiplex transmission line in one embodiment of the present invention, and FIG. 2 is a signal waveform diagram in the same device. 11 ... Relay terminal device, 12 ... Reception data bus, 13
...... Transmission data bus, 14 ...... Control signal bus, 15, 1
6, 17 ... Line control device.

Claims (1)

[Claims] 1. Serial / parallel conversion of data and establishment of a frame synchronization signal to a relay terminal device connected to a digital network, and parallel transmission / reception data, frame header timing signal of time division signal, transmission / reception clock and transmission. A control signal including a permission signal is placed on each of a transmission data bus, a reception data bus, and a control signal bus to couple between the relay terminal device and a plurality of line control devices, and the plurality of line control devices are the same. A general-purpose access method for high-speed time division multiplex transmission lines that enables time-division access to the bus.