JPH06303634A - Drive circuit for display device - Google Patents

Abstract

PURPOSE:To realize the drive circuit for a display device in which a linearity characteristic of an output amplitude and a terminal voltage is excellent and production of non-output state of a video signal in a final output is prevented. CONSTITUTION:The circuit is provided with a 1st clamp circuit 15 applying clamp processing to an input video signal to feed back the processed signal to an input section of the video signal, a slice circuit 13 applying slice processing to the input video signal, a gain control amplifier 12 adjusting a video signal level outputted from the slice circuit 13 to a level in response to a predetermined control voltage and a 2nd clamp circuit 16 implementing clamp processing to the output video signal of the gain control amplifier 12 to feed back the result to the output side of the gain control amplifier 12.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a CRT (Cathode Ray T
ube) is related to the drive circuit of the display.

[0002]

2. Description of the Related Art Generally, in a CRT type color display or the like, there are three types of CRT red (R), green (G) and blue (B) light emitters (phosphors) as shown in FIG. 6 (a). A drive circuit is provided to correct the difference in luminous efficiency and to adjust so as to reproduce correct white with respect to the reference white signal, as shown in FIG.

In a CRT type color display or the like, in order to achieve high resolution, that is, wide band, R
It is advantageous to use one package for each GB.
In the case of 1 channel 1 package, it is necessary to combine the drive control with the contrast control pin voltage.
A circuit system that improves the linearity characteristics of output amplitude and terminal voltage is essential.

FIG. 7 is a block diagram showing a configuration example of a drive circuit of a conventional CRT type color display. In FIG. 7, 1 is a predrive amplifier, 2 is an inverting amplifier, 3 is a CRT, V _IN is a signal source, C _IN is an input capacitor, V _BRT is a brightness control power supply, and C
_SH is a sample and hold capacitor, and r ₁ and r ₂ are resistance elements.

The pre-drive amplifier 1 is integrated into an IC, and has an input side amplifier 11 and a gain control amplifier 1.
2, a sync (SYNC) slice circuit 13, an output side amplifier 14, a first clamp circuit 15, a second clamp circuit 16 and a reference voltage source V _B. The pre-drive amplifier 1 includes a video signal input terminal T _IN , a contrast control signal CONT input terminal T _CONT , a video signal output terminal T _OUT , a divided voltage input terminal T _V , and a brightness control signal input terminal T _BRT. , Sample hold terminal T _SH and clamp pulse input terminal T
_{Have a CLP} .

[0006] In such a configuration, a video signal by the signal source V _IN is through a capacitor C _IN, is inputted to the terminal T _IN of the pre-drive amplifier 1. Pre-drive amplifier 1
The video signal input to is input to the gain control amplifier 12 via the amplifier 11. At this time, the contrast control signal CONT whose level is adjusted externally is input to the gain control amplifier 12 via the terminal T _CONT . Gain control amplifier 12
Then, the amplitude of the video signal is amplified to a predetermined level and adjusted according to the input level of the contrast control signal CONT, and is output to the slice circuit 13.

In the slice circuit 13, so-called SYNC is sliced to a black level in accordance with the input of the output video signal of the gain control amplifier 12 and the reference level V _REF of the reference voltage source V _B , and the first clamp circuit 15 and the output side. It is output to the amplifier 14. First clamp circuit 1
5, the black level of the video signal is set to the reference level V _REF in accordance with the input of the output video signal of the slice circuit 13 and the reference level V _REF of the reference voltage source V _B , and the input side amplifier 1
It is returned to the input of 1. That is, the feedback circuit operates so that the black level of the video signal becomes the reference level V _REF .

The video signal outputted from the slice circuit 13 and inputted to the output side amplifier circuit 14 is inputted to the inverting amplifier 2 via the terminal T _OUT after being subjected to a predetermined level adjusting action, and becomes the output signal of the inverting amplifier 2. The image for which the white balance has been adjusted on the basis is displayed on the CRT 3. In this case, the output level of the inverting amplifier 2 is the resistance elements r ₁ and r ₂
Divided by and fed back to the pre-drive amplifier 1,
It is input to one input terminal of the second clamp circuit 16 via the terminal T _V.

A brightness control signal BRT adjusted by the brightness control power source V _BRT is applied to the other input terminal of the second clamp circuit 16 at a terminal T.
It is input via the _BRT , the reference level of the output signal is set to the brightness control signal BRT level, and is fed back to the output side amplifier 14. As a result, the final output level is adjusted to the level of the brightness control signal BRT and input to the CRT 3.

FIG. 8 shows a specific circuit configuration of the gain control amplifier 12 in the predrive amplifier 1 of FIG. As shown in FIG. 8, the gain control amplifier 12 includes npn-type transistors (hereinafter simply referred to as transistors) q _{121 to} q ₁₂₇ , input resistance elements R _IN1 and R _{IN 2} , constant current sources i ₁₂₁ and i ₁₂₂ , and a voltage source. V _B2
˜V _{B5 and the} load resistance element R _L.

Specifically, transistors q ₁₂₃ and q ₁₂₄ , whose emitters are connected to each other, and transistor q ₁₂₅
Two first and second differential pairs of Q q ₁₂₆ and q ₁₂₆ are connected in parallel, and a transistor q ₁₂₁ and a constant current source i ₁₂₁ are connected to the first differential pair of transistors q ₁₂₃ and q _124. A second differential pair of transistors q ₁₂₅ and q ₁₂₆ , which are connected to each other, are connected to a transistor q ₁₂₂ and a constant current source i.
₁₂₂ is connected.

The input resistance element R_IN2Is the input side
Output of the amplifier 11 and the transistor q of the first differential pair₁₂₁D
Input resistor element R_IN1Is the input side
The output of the amplifier 11 and the transistor q of the second differential pair₁₂₂
Connected between the emitters of the
Dista q_{one two Three}And q₁₂₅A constant voltage is supplied to the base of
Langista q₁₂₄And q₁₂₆Contrast control on the base
Voltage ΔV adjusted by the input of the trawl signal CONT
Is supplied to the second differential pair of transistors q ₁₂₆The
Transistor q connected to the₁₂₇Collector and negative
Load resistance element R _LGain adjusted from the midpoint of connection with
The image signal is input to one input terminal of the first clamp circuit 15.
Is output.

The gain control amplifier 12 is constructed as a grounded base amplifier of a transistor, and the maximum and minimum of the gain G ₁₂ are expressed by the following equation (1) and
It is given by equation (2). G _{12 (maximum) = R L / R IN1 ...} (1) G 12 ( _{minimum) = R L / R IN2 ...} (2) ( provided that, R _IN2> R _IN1)

FIG. 9 shows the relationship between the contrast control voltage and the output voltage of the circuits of FIGS. 7 and 8.
FIG. 10 shows the relationship between the contrast control voltage and the input clamp DC in the circuits of FIGS. 7 and 8.

Further, as a drive circuit of a conventional display, a so-called blanking level control is performed after a video signal amplitude portion of a video signal is adjusted by a gain control amplifier in a pre-drive amplifier and a blanking amplitude portion is sliced by a slicing circuit. A circuit is known which is configured to obtain the signal amplitude by adjusting and adding the amplitude of the blanking level portion by the function.

FIG. 11 shows a blanking level controller.
Circuit showing a configuration example of a conventional drive circuit having a function
It is a figure. 11, the same components as those of FIG. 7 are the same.
It is represented by a code. That is, 1a is a Pridra
Eve amplifier, 3 CRT, 4 drive amplifier, V _INIs
Signal source, C_INIs an input capacitor, V_BRTBrighton
Control power supplies are shown respectively.

The pre-drive amplifier 1a includes an input side amplifier 11, a gain control amplifier 12, a SYNC slice circuit 13, a clamp circuit 15, a blanking level resistance element R _BLK , a blanking level switching circuit SW _BLK , and a blanking level. It has a current source I _BLK and a power amplifier 17. The pre-drive amplifier 1a also includes a video signal input terminal T _IN , a contrast control signal CONT input terminal T _CONT , a video signal output terminal T _OUT , a blanking level control signal BLKCNT input terminal T _BLKCNT , and a brightness control signal input. Terminal T _BRT , blanking pulse BL
It has a KPLS input terminal T _BLKPLS and a clamp pulse input terminal T _CLP .

Further, FIG. 12 shows a pre-drive amplifier 1a.
3 is a diagram showing specific circuit configurations of an amplifier 11 and a gain control amplifier 12 of FIG. As shown in FIG.
The amplifier 11 is composed of transistors q ₁₁₁ and q ₁₁₂ and current sources i ₁₁₁ and i ₁₁₂ , whose input is composed of the base of the transistor q ₁₁₁ , and whose output is the emitter of the transistor q ₁₁₂ and the constant current source q ₁₁₂ . It is composed of the connection midpoint of. The gain control amplifier 12 includes transistors q _{123 to} q ₁₂₆ and a constant current source i.
₁₂₁ , i ₁₂₂ , load resistance elements R _L1 , R _L2 and voltage sources V _B , ΔV _B , the inputs of which are the midpoint of connection between the emitters of transistors q ₁₂₃ and q ₁₂₄ and the constant current source i ₁₂₁ . is constituted by a connection point, the output is configured by the connection point between the collector and the load resistance element R _L2 of the transistor q _124.

In this circuit, the output of the amplifier 11 and the input of the gain control amplifier 12 are connected via the resistance element R _IN . In addition, gain control amplifier 1
The output of 2 is connected to one input of the slice circuit 13,
The other input of the slice circuit 13 is connected to the brightness control signal input terminal T _BRT.

[0020] In the circuit of FIG. 11 and FIG. 12, a video signal by the signal source V _IN is through a capacitor C _IN, is inputted to the terminal T _IN of the pre-drive amplifier 1a. The video signal input to the pre-drive amplifier 1a is supplied to the amplifier 11
Is input to the gain control amplifier 12 via.
At this time, the gain control amplifier 12 receives the contrast control signal CON whose level is adjusted externally.
T is input through the terminal T _CONT . In the gain control amplifier 12, the video amplitude portion of the video signal is amplified and adjusted to a predetermined level according to the input level of the contrast control signal CONT, and output to the slice circuit 13.

In the slice circuit 13, the blanking amplitude portion of the video signal is removed in response to the input of the output video signal of the gain control amplifier 12 and the brightness control signal BRT, and the video amplitude portion from which the blanking amplitude portion is removed is mainly composed. The video signal to be applied is applied to the blanking level resistance element R _BLK and is also output to one input terminal of the clamp circuit 15.

At this time, a blanking level control voltage BL is applied to the blanking level constant current source I _BLK.
KCNT is supplied, which causes the predetermined current I to flow. Also, the blanking level switching circuit SW
_A blanking pulse BLKPLS is input to _BLK . As a result, a blanking amplitude section based on the voltage drop R · I of the resistance element R _BLK and the current I is newly added to the video signal mainly output from the slice circuit 13. .

The video signal in which the video amplitude portion adjusted to the desired level and the blanking amplitude portion are combined in this way is output from the terminal T _OUT via the amplifier 17. The video signal output from the pre-drive amplifier 1a is input to the drive amplifier 4, the output of the drive amplifier 4 is input to the CRT 3 via an inverting amplifier (not shown), and the white-balance-adjusted video is displayed on the CRT 3.

Further, in the clamp circuit 15, the output video signal of the slice circuit 13 and the reference level V of the reference voltage source V _B.
With the input of _REF , the black level of the video signal is the reference level V
_It is set to _REF and fed back to the input of the input side amplifier 11. That is, the black level of the video signal is the reference level V _REF.
The feedback circuit works as follows.

[0025]

However, in the drive circuit of FIG. 7, since R _IN2 is also used as the input resistance element in addition to R _IN1 as shown in FIG.
There is a problem in that the gain control characteristic is as shown by the solid curve, and even if the contrast control signal is narrowed (even if it is reduced), it cannot be completely narrowed down and the linearity characteristic is inferior.

To solve this problem, in the above-mentioned CRT type color display or the like, it is advantageous to use one package for each RGB for one channel in order to achieve a high resolution, that is, a wide band. In this case, it is necessary to control the drive adjustment that absorbs the variations in the luminous efficiency of R, G, and B on the tube surface of the CRT 3 with one contrast control, and a circuit system that improves the linearity characteristics of the output amplitude and the terminal voltage is essential. It will be contrary to the condition.

In order to solve this problem, it is conceivable to remove the input resistance element R _IN2 . Actually, by removing the input resistance element R _IN2 , as shown by the broken line in FIG. The linearity seems to be improved and effective, but in this case, as shown in FIG. 10, the input DC level fluctuates when the contrast control voltage is changed, and when the contrast control voltage is narrowed down, it becomes an IC. Pre-drive amplifier 1
However, there is a problem in that the first clamp circuit 15 in 1 is turned off and the video signal is not output to the final output. Hereinafter, this problem will be described in detail.

In the circuit of FIG. 8, the feedback circuit works so that the black level of the video signal becomes the reference level V _REF .
When a black signal is input, the potential P ₁ on the output side of the amplifier 11 and the potential P on the emitter side of the transistor q ₁₂₄ in FIG.
₂ is not necessarily equal. Assuming that P ₁ <P ₂ , the currents flowing in the transistors q ₁₂₁ and q ₁₂₂ are (I ₀ + α ′) and (I ₀ + α), respectively, and the output voltage V _OUT has a gain control coefficient K. _{Assuming that} the supply voltage of the voltage source V _B5 is E, the following equation is obtained. V _OUT = E−R _L {K (I ₀ + α) + (1−K) (I ₀ + α ′)} = E−R _L {I ₀ + Kα + (1−K) α ′} (3)

Here, assuming a configuration in which the input resistance element R _IN2 is removed in order to improve the linearity characteristic, since α ′ in the equation (3) is eliminated, the equation (3) is changed to the following equation. Can be rewritten. V _OUT = E− _RL (I ₀ + Kα) (4) Since the reference level V _REF by the reference voltage source V _B is fixed, for example, if the reference level V _REF is set as in the following equation (5), The first clamp circuit 15 has equations (4) and (5).
Operates so that the expression and are always equal. V _REF = E− _RL (I ₀ + α) (5)

Under such conditions, the coefficient K is changed by changing the contrast control voltage CONT.
The value of changes. At this time, in an extreme case, K = 0.
In the case of 1, when α in the above equation (5) is α ″, the above equation (4) can be rewritten as the following equation (6), and the first clamp circuit 15 changes the equation (6) into (5 ) operates to be equal to the value of the _{expression. V OUT = E-R L} · I 0 -R L · 0.1 · α "... (6)

That is, α ″ so that α ″ = 10α
And the voltage drop of (α ″ · R _IN1 ) causes the output side potential P ₁ of the amplifier 11 to become lower than the emitter side potential P ₂ of the transistor q _124. As a result, the amplifier 11 is turned off. Since the first clamp circuit 15 is cut off, the video signal is not output to the final output.

The circuit of FIG. 11 requires the drive amplifier 4 for simultaneously changing the gains and blanking levels of the video signals R, G, B in order to adjust the white balance of the CRT. However, there is a problem in that the number of adjustments and the number of adjustment steps increase.

On the other hand, as shown in FIG. 13, the drive amplifier 4 is built in the pre-drive amplifier 1a and the IC
However, this configuration has problems such as deterioration of frequency characteristics and increase of current consumption.

In the drive circuits of FIGS. 11 to 13, the normal blanking level constant current source I _BLK is n.
It is composed of a pn-type transistor, and the product C · R of C _CS and the blanking level resistance element R _BLK causes deterioration of frequency characteristics. That is, the drive circuit of the display having the conventional blanking level control function has a configuration that causes deterioration of the frequency characteristic.

The present invention has been made in view of the above circumstances, and an object thereof is to have a good linearity characteristic of an output amplitude and a terminal voltage, and to prevent a non-output state of a video signal at final output, Another object of the present invention is to provide a display drive circuit capable of preventing an increase in the number of components, an increase in power consumption, and a deterioration in frequency characteristics.

[0036]

In order to achieve the above object, according to the present invention, a first clamp circuit for performing clamp processing on an input video signal and feeding back to the input portion of the video signal, and a slice processing for the input video signal are provided. Slice circuit to perform, gain control amplifier that adjusts the output video signal level of the slice circuit to a level according to a predetermined control signal, and clamp processing to the output video signal of the gain control amplifier to feed back to the output side of the gain control amplifier And a second clamp circuit.

In the present invention, the control coefficient of the first control signal is controlled by the slice circuit for extracting only the video amplitude portion from the input video signal and the video amplitude portion output from the slice circuit connected to the load resistance element. According to the control coefficient of the second control signal, the current value of the current source is adjusted, and a pulse having a level corresponding to the product of the adjusted current and the load resistance element is generated. In addition, a circuit for adding a blanking amplitude section to the level-adjusted video amplitude section and outputting the blanking amplitude section is provided.

Further, the present invention has a circuit for changing the coefficient of the first control signal at a predetermined ratio.

Further, in the present invention, a circuit for changing the coefficient of the second control signal with a predetermined ratio is provided.

Further, in the present invention, a circuit for changing the coefficient of the first control signal and the coefficient of the second control signal with the same ratio is provided.

[0041]

According to the present invention, the clamp processing is performed on the input video signal in the first clamp circuit and is fed back to the input portion of the video signal. The input video signal (including the video signal subjected to the input clamp processing) is input to the slice circuit, and predetermined slice processing, for example, SYNC in the G channel is sliced to the black level, and output to the gain control amplifier. In the gain control amplifier, the SYNC sliced video signal level is adjusted to a level according to a predetermined control signal and output. The output video signal of the gain control amplifier is
The second clamp circuit processes a predetermined clamp and feeds it back to the output side of the gain control amplifier.

According to the present invention, in the slice circuit,
Only the video amplitude part is extracted from the input video signal and output to the circuit in the next stage. In the circuit in the next stage, the video amplitude section output from the slice circuit is adjusted to a predetermined level by the element connected to the load resistance element according to the control coefficient of the first control signal. Also, in this circuit,
The current value of the current source is adjusted according to the control coefficient of the second control signal, a pulse having a level according to the product of the adjusted current and the load resistance element is generated, and the level-adjusted video amplitude section is generated. It is added as a blanking amplitude section. Then, the image amplitude part and the blanking amplitude part are output as a combined video signal.

Further, according to the present invention, the coefficient of the first control signal is changed with a predetermined ratio.

Further, according to the present invention, the coefficient of the second control signal is changed with a predetermined ratio.

Further, according to the present invention, the coefficient of the first control signal and the coefficient of the second control signal can be changed with the same ratio.

[0046]

[First Embodiment] FIG. 1 is a block diagram showing a first embodiment of a drive circuit for a display according to the present invention. The same components as those in FIG. 7 showing a conventional example are designated by the same reference numerals. That is, 1A is a predrive amplifier, 2 is an inverting amplifier, 3 is a CRT, V _IN is a signal source, C _IN is an input capacitor, V _BRT is a brightness control power supply,
C _SH is a sample and hold capacitor, and r ₁ and r ₂ are resistance elements.

The pre-drive amplifier 1A is integrated into an IC, and includes input side amplifiers 11a and 11b, a gain control amplifier 12, a sync (SYNC) slice circuit 13,
The output side amplifier 14, the first clamp circuit 15, the second clamp circuit 16 and the reference voltage source V _B are provided. Further, the pre-drive amplifier 1A has a video signal input terminal T
_IN , contrast control signal CONT input terminal T _CONT , video signal output terminal T _OUT , divided voltage input terminal T _V , brightness control signal input terminal T
_{It has a BRT} , a sample hold terminal T _SH, and a clamp pulse input terminal T _CLP .

The pre-drive amplifier 1A according to this embodiment
Each component is connected as follows. Sanawa
The input of the amplifier 11a is a video signal input terminal T_INContact
And the output is the input and slice circuit of the amplifier 11b.
13 is connected to one input. Output of amplifier 11b
Force is connected to one input of the first clamp circuit 15,
The other input of the first clamp circuit 15 and slice times
The other input of the path is the reference voltage source V_BIt is connected to the. First
The output of the clamp circuit 15 of 1 corresponds to the input of the amplifier 11a.
Image signal input terminal T _INConnected to the midpoint of
The output of the output circuit 13 is the input of the gain control amplifier 12.
Connected to force.

The output of the gain control amplifier 12 is
Control terminal is connected to one input
Contrast control signal CONT input terminal T
_CONTIt is connected to the. The other input of the amplifier 14 is the second
Is connected to the output of the clamp circuit 16 and the output is a video signal.
Output terminal T_OUTIt is connected to the. Second clamp time
One input of path 16 is a brightness control signal.
Input terminal T_BRTAnd the other input is
Force terminal T_VIt is connected to the. Also the first clamp
Control terminal of circuit 15 and second clamp circuit
One control terminal of 16 is for clamp pulse input
Terminal T_CLPConnected to the other of the second clamp circuit 16
Control terminal is a sample and hold terminal T _SHContact
Has been continued.

As described above, the pre-drive amplifier 1A according to the present embodiment performs the input clamp and the SYNC slice for slicing the SYNC in the G channel to the black level before the gain control amplifier 12, and then outputs the contrast control signal CONT. It is configured to perform a corresponding gain control.

FIG. 2 shows a specific circuit configuration of the amplifiers 11a and 11b, the slice circuit 13, the gain control amplifier 12 and the reference voltage source V _B in the predrive amplifier 1A of FIG.

As shown in FIG. 2, the amplifier 11a is a transformer.
Dista (npn type) Q_111aAnd constant current source I_111aBy
The amplifier 11b is configured as a transistor Q._111bAnd constant
Current source I_111bIt is composed by. Slice circuit 13
Is the transistor Q₁₃₁, Q₁₃₂And constant current source I₁₃₁To
It is composed of Gain control amplifier 12
Is the transistor Q₁₂₀~ Q₁₂₈, Constant current source I ₁₂₀~ I
₁₂₂, Voltage source V_B2, ΔV_B2, V_B3, V_B4Input resistor
Child R_INAnd load resistance element R_L1, R_L2Composed by
ing. Reference voltage source V_BIs the voltage source V_B1, Diode D
₁And constant current source I₁It is composed by.

Next, the connection relationship of each of these elements will be described. The base of the transistor Q _111a of the amplifier 11a is connected to the terminal T _IN and the output of the first clamp circuit 15,
The collector is connected to the power supply voltage V _CC , and the emitter is connected to the constant current source I _111a , the base of the transistor Q _111b of the amplifier 11b, and the base of the transistor Q ₁₃₁ of the slice circuit 13. The collector of the transistor Q _111b of the amplifier 11b is connected to the power supply voltage V _CC ,
The emitter is a constant current source I _111b and the first clamp circuit 1
5 is connected to one input. The collector of the transistor Q ₁₃₁ of the slice circuit 13 is connected to the power supply voltage V _CC , the emitter thereof is connected to the emitter of the transistor Q ₁₃₂ , and the middle point of connection between the emitters of both transistors Q ₁₃₁ and Q ₁₃₂ is a constant current source I ₁₃₁ and It is connected to the base of the transistor Q ₁₂₀ of the gain control amplifier 12. Also, the collector of the transistor Q ₁₃₂ has a power supply voltage V
_It is connected to _CC and the base is connected to the output of the reference voltage source V _B1 .

[0054] The constant current source I ₁ of the reference voltage source V _B is is connected to the power source voltage V _CC, is connected to the anode of the diode D _1, the cathode of the diode D ₁ is connected to a voltage source V _B1. The midpoint of connection between the constant current source I ₁ and the anode of the diode D ₁ is connected to the other input of the first clamp circuit 15, and the cathode of the diode D ₁ and the voltage source V _B1.
The middle point of connection with is the transistor Q of the slice circuit 13.
It is connected to the base of _{132 and} the bases of the transistors Q ₁₂₁ and Q ₁₂₂ of the gain control amplifier 12, respectively.

Transition of gain control amplifier 12
Star Q₁₂₀Is the power supply voltage V _CCConnected to the emi
Is a constant current source I₁₂₀And resistance element R_INConnect to one end of
Has been done. Transistor Q₁₂₁Is the reference current source
V_BIs connected to the output of the_{one two Three}
And Q₁₂₄Connected to the emitter of, the emitter is a constant current
Source I ₁₂₁It is connected to the. Transistor Q₁₂₂The ba
Is the reference current source V_BConnected to the output of the
Register Q₁₂₅And Q₁₂₆Connected to the emitter of
Mitter is a constant current source I ₁₂₂And resistance element R_INTouch the other end of
Has been continued. Transistor Q_{one two Three}The base of the voltage source V
_B2Connected to the collector of transistor Q₁₂₆Collect
And transistor Q₁₂₈Connected to the emitter of
It Transistor Q₁₂₄Is the voltage source ΔV_B2Connected to
And the collector is a transistor Q₁₂₅Collector and
Transistor Q₁₂₇Connected to the emitter. Tiger
Register Q₁₂₅The base of the voltage source V_B2Connected to the tiger
Register Q₁₂₆Is the voltage source ΔV_B2Connected to
It Transistor Q₁₂₇The base of the voltage source V_B3Connected to
And the collector is a load resistance element R_L1Voltage source V via_B4
It is connected to the. Transistor Q₁₂₈The base of voltage
Source V_B3Connected to the collector of the load resistance element R_L2Through
And voltage source V_B4Connected to the collector and load resistive element
R_L2Gain control amplifier 12 depending on the midpoint of connection with
The output of is configured. In addition, the voltage source ΔV_B2At terminal T
_CONTThe contrast control signal CONT
And, as a result, the contrast control signal C
The voltage ΔV changed according to ONT is the transistor Q
₁₂₄And Q₁₂₆Supplied to the base of.

Next, the operation of the configuration shown in FIG. 1 will be described.
The video signal from the signal source V _IN passes through the capacitor C _IN ,
It is input to the terminal T _IN of the pre-drive amplifier 1A. The video signal input to the pre-drive amplifier 1A is
It is input to one input terminal of the slice circuit 13 via 1a, and is further input to one input terminal of the first clamp circuit 15 via the amplifier 11b.

In the slice circuit 13, the input video signal and
And reference voltage source V_BReference level V_{RE F}With the input of
In the image signal, SYNC in the G channel has a black level.
Is sliced to the gain control amplifier 12
Is output. In the first clamp circuit 15, the input video signal is
No. and reference voltage source V_BReference level V _REFWith the input of
The black level of the video signal is the reference level V_REFIs set to
It is fed back to the input of the input side amplifier 11a. That is,
The black level of the image signal is the reference level V_REFReturn to be
The circuit works.

The clamp processing at this time is performed by the gain control amplifier 12 which performs the gain adjustment according to the contrast control signal CONT which changes like the conventional circuit.
The so-called input clamp DC does not change even if the contrast control signal CONT fluctuates because it is performed in the front stage instead of the latter stage.

The gain control amplifier 12 has a contrast control signal CO whose level is adjusted externally.
NT is input through the terminal T _CONT . In the gain control amplifier 12, the amplitude of the video signal is amplified and adjusted to a predetermined level according to the input level of the contrast control signal CONT, and is output to the output side amplifier 14.

The video signal output from the gain control amplifier 12 and input to the output-side amplifier circuit 14 is input to the drive amplifier 2 via the terminal T _OUT after undergoing a predetermined level adjusting action, and the output signal of the inverting amplifier 2 is output. An image whose white balance has been adjusted based on is displayed on the CRT 3. In this case, the output level of the inverting amplifier 2 is divided by the resistance elements r ₁ and r ₂ , is fed back to the predrive amplifier 1, and is input to one input terminal of the second clamp circuit 16 via the terminal T _V. To be done.

The other input terminal of the second clamp circuit 16
Is a power supply V for brightness control_BRTAt the level
The adjusted brightness control signal BRT is
Child T _BRTInput via the
Lightness control signal BRT is set and output
It is returned to the side amplifier 14. This allows the final output level
Control to the level of the brightness control signal BRT.
It is adjusted and input to the CRT 3.

In the above operation, when the contrast control signal CONT changes, the output of the gain control amplifier 12 is as follows, where the gain control coefficient is K, as in the case of FIG. 8 showing the conventional example. Since the coefficient K changes from the equation (4) described above, it changes. V _OUT = E− _RL (I ₀ + Kα) (4) However, the second clamp circuit 16 arranged in the subsequent stage.
The final output is determined by the terminal voltage of the power source V _BRT for the brightness control signal by the action of, and only the voltage of the sample-hold capacitor C _SH changes, and the output signal DC (black level) changes with the temperature characteristics and the passage of time. There is nothing to do.

As described above, according to this embodiment,
The input control is performed in the preceding stage of the gain control amplifier 12 that adjusts the gain according to the changing contrast control signal CONT, and the SYNC slice is configured to match the black level, and the gain control amplifier is changed by the change of the contrast control signal CONT. Since the second clamp circuit 16 arranged in the subsequent stage absorbs the fluctuation of the output DC due to the fluctuation of the output of the No. 12 output, the linearity characteristic between the output amplitude and the terminal voltage is good, and the video signal of the final output is It is possible to prevent a non-output state from occurring. Therefore, this circuit is most suitable for 1-channel 1-package IC, and if three of these ICs are used and the terminal voltage is controlled by the microcomputer, drive adjustment that easily absorbs the RGB variations of the CRT is possible. .

[0064]

[Embodiment 2] FIG. 3 is a block diagram showing a second embodiment of a drive circuit for a display according to the present invention, and has the same configuration as FIG. 11 showing a conventional drive circuit having a blanking level control function. The parts are represented by the same symbols. That is, 1a is a pre-drive amplifier,
2 is an inverting amplifier, 3 is a CRT, V _IN is a signal source, C _IN is an input capacitor, V _BRT is a brightness control power supply, V _CONT is a contrast control power supply with a variable coefficient A, and V _BLKCNT is a coefficient B. A variable blanking level control power supply V _DRV indicates a drive control power supply whose coefficient K is variable.

The pre-drive amplifier 1a is an IC, and the input side amplifier 11 and the gain control amplifier 1 are provided.
2, SYNC (sink) slice circuit 13, clamp circuit 15, blanking level switching circuit SW
_{A BLK} , a blanking level current source I _BLK , a power amplifier 17, and multipliers 18 and 19 are provided. The pre-drive amplifier 1a includes a video signal input terminal T _IN , a video signal output terminal T _OUT , a contrast control signal CONT input terminal T _CONT , a blanking level control signal BLKCNT input terminal T _BLKCNT , and a drive control signal DRV. It has an input terminal T _DRV , a brightness control signal BRT input terminal T _BRT , a blanking pulse BLKPLS input terminal T _BLKPLS, and a clamp pulse input terminal T _CLP .

The respective components of the pre-drive amplifier 1a according to this embodiment are connected as follows. That is, the input of the amplifier 11 is connected to the video signal input terminal T _IN , and the output is connected to one input of the slice circuit 13. The other input of the clamp circuit 15 and the other input of the slice circuit 13 are connected to the reference voltage source V _B. The output of the clamp circuit 15 is connected to the input midpoint between the input of the amplifier 11 and the video signal input terminal T _IN, and the output of the slice circuit 13 is connected to the input of the gain control amplifier 12.

The output of the gain control amplifier 12 is connected to the input of the amplifier 17, and the output of the amplifier 17 is connected to the video signal output terminal T _OUT . The contrast control terminal of the gain control amplifier 12 is connected to the output of the multiplier 18, the blanking level control terminal is connected to the output of the switching circuit SW _BLK , and the brightness control terminal is connected to the brightness control signal BRT input terminal T _BRT. ing. The input of the switching circuit SW _BLK is connected to the blanking level current source I _BLK , and the switching circuit SW _BLK is connected.
_BLK control terminal is blanking pulse BLKP
It is connected to the LS input terminal T _BLKPLS . The control terminal of the blanking level current source I _BLK is multiplier 1
9 outputs.

One input of the multiplier 18 is a contrast
Control signal CONT input terminal T_CONTConnected to the
The other input is the end for inputting the drive control signal DRV
Child T _DRVIt is connected to the. One input of the multiplier 19 is
Blanking level control signal BLKCNT input
Terminal T_BLKCNTAnd the other input is connected to the drive controller.
Troll signal DRV input terminal T_DRVConnected to
It

As described above, the pre-drive amplifier 1a according to the present embodiment performs the slicing process and the input clamp before the gain control amplifier 12, and arranges the gain control amplifier 12 at the subsequent stage to respond to the contrast control signal CONT. The gain control of the video amplitude section and the blanking level control according to the blanking level control signal BLKCNT and the blanking pulse BLKPLS are performed.

FIG. 4 shows a specific circuit configuration of the amplifier 11, slice circuit 13 and gain control amplifier 12 in the pre-drive amplifier 1a shown in FIG.
In FIG. 4, the same parts as those in the circuit configuration of FIG. 2 described above are represented by the same reference numerals.

As shown in FIG. 4, the amplifier 11 has a transient
Star (npn type) Q₁₁₁And constant current source I₁₁₁By
Is made. Slice circuit 13 is a transistor
Q₁₃₁, Q₁₃₂And constant current source I₁₃₁Composed by
There is. The gain control amplifier 12 is a transistor
Q₁₂₁~ Q₁₂₈, Constant current source I ₁₂₁~ I₁₂₂, Voltage source
V_B2, ΔV_B2, V_B3, V_BCNT, Input resistance element R_INAnd
And load resistance element R_L1, R_L2It is composed by.

Next, the connection relation of each of these elements will be described.
It Transistor Q of amplifier 11₁₁₁Base is terminal T
_INAnd the collector of the clamp circuit 15
Is the power supply voltage V_CCConnected to a constant current source I ₁₁₁
And the transistor Q of the slice circuit 13₁₃₁Base of
Respectively connected to. Trans of slice circuit 13
Dista Q₁₃₁Is the power supply voltage V_CCConnected to
Mitter is transistor Q₁₃₂Connected to the emitter of both
Transistor Q₁₃₁, Q₁₃₂Midpoint between the emitters of
Is a constant current source I₁₃₁, One input of the clamp circuit 15 and
And resistance element R_INIs connected to one end of. Also, Tran
Dista Q₁₃₂Is the power supply voltage V_CCConnected to the
Is the reference voltage source V_B1It is connected to the.

Transition of gain control amplifier 12
Star Q₁₂₁Is the reference current source V _B1Connected to the output of
And the collector is a transistor Q_{one two Three}And Q₁₂₄Emi
The constant current source I₁₂₁And resistance
Element R_INIs connected to the other end of. Transistor Q₁₂₂
Is the reference current source V_B1Connected to the collector
Register Q₁₂₅And Q₁₂₆Connected to the emitter of
Mitter is a constant current source I₁₂₂And the other of the clamp circuit 15
Connected to the input of. Transistor Q_{one two Three}Base of
Is the voltage source V_B2Connected to the collector of transistor Q
₁₂₆Collector and transistor Q₁₂₈To the emitter of
It is connected. Transistor Q₁₂₄The base of the voltage source
ΔV_B2Connected to the collector of transistor Q₁₂₅The
Rector and transistor Q₁₂₇Connected to the emitter of
ing. Transistor Q₁₂₄And Q₁₂₅The collector of
Switching circuit SW at the middle point of connection_BLKOutput is connected
Has been done.

The base of the transistor Q ₁₂₅ is the voltage source V _B2.
And the base of the transistor Q ₁₂₆ is a voltage source ΔV
_It is connected to _B2 . The base of transistor Q ₁₂₇ is connected to a voltage source V _B3, collector connected to the variable voltage source V _BCNT through the load resistance element R _L1, the gain control by the connection point of the collector and the load resistance element R _L1 The output of the amplifier 12 is configured and connected to the input of the amplifier 17. The base of the transistor Q ₁₂₈ is the voltage source V _B3
And the collector is connected to the variable voltage source V _BCNT via the load resistance element R _L2 .

In the pre-drive amplifier 1a according to this embodiment, a blanking amplitude section based on the product R _L · I of the load resistance element R _L1 and the current I from the blanking level current source I _BLK is newly added. Is configured. Further, the contrast control signal CONT is supplied to the voltage source ΔV _B2 via the terminal T _CONT, and as a result, the voltage ΔV changed according to the contrast control signal CONT is supplied to the bases of the transistors Q ₁₂₄ and Q ₁₂₆ , and is varied. The brightness control signal BRT is supplied to the voltage source V _BCNT via the terminal T _BRT .

Next, the operation of the configuration shown in FIG. 3 will be described.
Signal source V_INThe video signal by is the capacitor C_INThrough
Terminal T of pre-drive amplifier 1a_INEntered in. Puri
The video signal input to the drive amplifier 1a is sliced
It is input to one input terminal of the circuit 13. Slice circuit
In 13, the input video signal and the reference voltage source V_BBy
Sub-voltage V _REFInput, the blank in the video signal
The ring amplitude part is removed. This blanking amplitude part is
The removed video signal, which mainly consists of the video amplitude section, is
One of the troll amplifier 12 and clamp circuit 15
Input to the input terminal.

At this time, the contrast control signal CONT having the coefficient A whose level has been adjusted externally is input to one input of the multiplier 18 through the terminal T _CONT , and the level of the same is also externally adjusted to the other input. Terminal T with coefficient K
_The drive control signal DRV is input via _DRV . The multiplier 18 multiplies both input voltage signals to obtain a contrast control signal CON having a coefficient KA.
T is input to the gain control terminal.

The blanking level control signal BLKCNT of the coefficient B whose level has been adjusted externally is input to one input of the multiplier 19 through the terminal T _BLKCNT , and the coefficient K which is also adjusted externally to the other input. Terminal T _DRV
The drive control signal DRV is input via the. In the multiplier 19, both input voltage signals are multiplied and the blanking level control signal BLKCNT having the coefficient KB is input to the control terminal of the blanking level current source I _BLK . As a result, the current I whose value is adjusted based on the coefficient KB is applied to the switching circuit SW.
Output to _BLK . The blanking pulse BLKPLS is input to the switching circuit SW _BLK at a predetermined timing. Along with this, gain control amplifier 1
2, a predetermined amplifying action is performed on the video signal mainly composed of the video amplitude section output from the slice circuit 13, and the product R _L · I of the load resistance element R _L1 and the current I.
A pulse of a level based on I is generated and newly added as a blanking amplitude portion to the video amplitude portion, and the amplifier 17
Is output to. At this time, the variable voltage source V _BCNT connected to the load resistance elements R _L1 and R _L2 is held at a predetermined value based on the brightness control signal BRT adjusted externally.

The video signal in which the video amplitude portion adjusted to the desired level and the blanking amplitude portion are combined in this way is output from the terminal T _OUT via the amplifier 17. The video signal output from the pre-drive amplifier 1a is input to the inverting amplifier 2, and the image whose white balance has been adjusted based on the output signal of the inverting amplifier 2 is displayed on the CRT 3.

Further, in the clamp circuit 15, the output video signal of the slice circuit 13 and the reference level V of the reference voltage source V _B.
With the input of _REF , the black level of the video signal is the reference level V
_It is set to _REF and fed back to the input of the input side amplifier 11. That is, the black level of the video signal is the reference level V _REF.
The feedback circuit works as follows.

As described above, according to this embodiment, after the blanking amplitude portion of the video signal is removed by the slice circuit 13, the contrast control signal CONT of the coefficient A and the blanking level control signal BKLCNT of the coefficient B are removed. And the drive control signal DRV having the coefficient K are multiplied by using the multipliers 18 and 19, and the gain control amplifier 12 is configured to control the contrast and the blanking level with the same ratio, that is, the coefficient K. Therefore, unlike the conventional case, it is not necessary to provide a drive adjustment amplifier, and there is an advantage that the number of parts and the adjustment man-hour can be reduced and the cost and the power consumption can be reduced.

Further, unlike the conventional circuit shown in FIG. 13, the drive adjusting amplifier is not built in the pre-drive amplifier, and the blanking level resistance element is the load resistance element R _L of the gain control amplifier 12. Since it is configured to be used in common, the frequency characteristics and the like are not deteriorated.

The circuit configuration of the pre-drive amplifier 1a is not limited to that shown in FIG.
As shown in FIG. 5, the output of the inverting amplifier 2 is fed back to the feedback terminal T _FDB of the pre-drive amplifier 1a via the attenuator 5, and the clamp circuit 20 performs the clamp processing based on the brightness control signal BRT, and outputs the output. _May be supplied to the variable voltage source V _BCNT of the gain control amplifier 12.

With such a configuration, there is an advantage that the drive circuit in which the black level (pedestal level) in the output waveform is not influenced by the temperature characteristic can be realized.

The blanking pulse BLKPLS and the clamp pulse CLP in this embodiment have different phases.

As described above, according to the present invention,
The linearity characteristics of the output amplitude and the terminal voltage are good, and it is possible to prevent the occurrence of the non-output state of the video signal at the final output.

Further, according to the present invention, it is possible to reduce the number of parts and the number of adjustment man-hours, the cost and the power consumption, and the frequency characteristic is not deteriorated.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a first embodiment of a drive circuit of a display according to the present invention.

FIG. 2 is a diagram showing a specific circuit configuration of an input side amplifier, a slice circuit, a reference voltage source and a gain control amplifier in the predrive amplifier of FIG.

FIG. 3 is a block diagram showing a second embodiment of the drive circuit of the display according to the present invention.

4 is a diagram showing a specific circuit configuration example of an input side amplifier, a slice circuit, and a gain control amplifier in the predrive amplifier of FIG.

5 is a diagram showing another circuit configuration example of the pre-drive amplifier of FIG.

FIG. 6 is a graph showing general control characteristics of a drive circuit.

FIG. 7 is a block configuration diagram showing a configuration example of a drive circuit of a conventional display.

8 is a diagram showing a specific circuit configuration example of a gain control amplifier in the pre-drive amplifier of the circuit of FIG.

9 is a diagram showing the relationship between the contrast control voltage and the output voltage of the circuits of FIGS. 7 and 8. FIG.

10 is a diagram showing the relationship between the contrast control voltage and the input clamp DC in the circuits of FIGS. 7 and 8. FIG.

FIG. 11 is a diagram showing a configuration example of a conventional drive circuit having a blanking level control function.

12 is a diagram showing a specific circuit configuration of an input side amplifier and a gain control amplifier of the predrive amplifier in FIG.

FIG. 13 is a diagram showing another configuration example of a conventional drive circuit having a blanking level control function.

[Explanation of symbols]

1A ... pre-drive amplifier 11a, 11b ... input amplifier 12 ... gain control amplifier 13 ... sync (SYNC) slice circuit 14 ... output amplifier 15 ... first clamp circuit 16 ... second clamp circuit V _B ... reference voltage source T _IN … Video signal input terminal T _CONT … Contrast control signal CONT input terminal T _OUT … Video signal output terminal T _V … Divided voltage input terminal T _BRT … Brightness control signal input terminal T _SH … Sample hold terminal T _CLP ... clamp pulse input terminal 2 ... inverting amplifier 3 ... CRT V _IN is a signal source C _IN ... input capacitor V _BRT ... brightness control power supply C _SH ... sample and hold capacitors r ₁ , r ₂ ... resistance elements respectively Shows. 1a ... Pre-drive amplifier 11 ... Input side amplifier 12 ... Gain control amplifier 13 ... SYNC (sink) slice circuit 15 ... Clamp circuit 17 ... Power amplifier 18, 19 ... Multiplier SW _BLK ... Blanking level switching circuit I _BLK ... Current source for ranking level T _IN … Video signal input terminal T _OUT … Video signal output terminal T _CONT … Contrast control signal CONT input terminal T _BLKCNT … Blanking level control signal BLK
CNT input terminal T _DRV … Drive control signal DRV input terminal T _BRT … Brightness control signal BRT input terminal T _BLKPLS … Blanking pulse BLKPLS input terminal T _CLP … Clamp pulse input terminal V _BRT … Brightness control power supply V _CONT … Contrast control power supply V _BLKCNT … Blanking level control power supply V _DRV … Drive control power supply

Claims (5)

[Claims] 1. A drive circuit of a display for adjusting the amplitude of an input video signal to display a video, comprising: a first clamp circuit for performing a clamp process on the input video signal and feeding back the video signal to an input section of the video signal; A slice circuit that performs slicing processing on the video signal, a gain control amplifier that adjusts the output video signal level of the slice circuit to a level according to a predetermined control voltage, and a gain control amplifier that performs clamp processing on the output video signal of the gain control amplifier. And a second clamp circuit for feeding back to the output side of the display circuit. 2. A drive circuit of a display for adjusting the amplitude of an input video signal to display a video, the slice circuit extracting only the video amplitude part from the input video signal, and the video amplitude part output from the slice circuit. Is adjusted to a predetermined level according to the control coefficient of the first control signal by an element connected to the load resistance element, and the current value of the current source is adjusted according to the control coefficient of the second control signal. A circuit for generating a pulse having a level corresponding to the product of the generated current and the load resistance element, and adding it as a blanking amplitude section to the level-adjusted video amplitude section for output. Drive circuit. 3. The drive circuit for a display according to claim 2, further comprising a circuit for changing the coefficient of the first control signal with a predetermined ratio. 4. The drive circuit for a display according to claim 2, further comprising a circuit for changing the coefficient of the second control signal at a predetermined ratio. 5. The display drive circuit according to claim 2, further comprising a circuit for changing the coefficient of the first control signal and the coefficient of the second control signal with the same ratio.