JPH06302185A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To simplify a column address generation circuit in a synchronous DRAM. CONSTITUTION:The column address generation circuit 27 is constituted so as to contain the control logic for switching a first mode participating the initial value of a column address in exclusive logical operation and a second mode participating no initial value of the column address in the exclusive logical operation. Thus, in two kinds of column address scanning specified in a burst mode, the column address generation circuit in the synchronous DRAM is simplified by attaining the sharing in one kind of a counter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address decoding technique for generating a control signal for selecting a memory element included in a semiconductor memory device.
RAM (Dynamic Random Access Memory)
Related to effective technology.

[0002]

2. Description of the Related Art In a DRAM, dynamic circuits operating in synchronization with a clock are used for peripheral circuits such as an address buffer, a decoder and a sense amplifier to reduce power consumption. Therefore, external clocks of one to three phases are required, and internal circuit clocks are generated based on these clocks to control or drive the peripheral circuits. In such a DRAM,
Random access is mainly performed, and a memory cell is selected by sequentially reading a row address and a column address for each access. Each part of the peripheral circuit is controlled by an internal clock so as to follow the procedures of row selection, detection of memory cell information, and column selection in order to prevent information destruction of the memory cell. After the read / write operation is completed,
A reset time is required to initialize the internal circuit for the next operation. Therefore, the cycle time of the memory operation becomes longer than the access time.

An example of a document describing DRAM is "LSI Handbook (Page 486-)" issued by Ohm Co., Ltd. on November 30, 1984.

[0004]

A conventional semiconductor memory,
Especially in a DRAM or the like, a SAM of a refresh counter or a display VRAM is used to generate an address inside the chip.
The output of an increment counter such as a serial counter for the (serial access memory) unit is used as an address signal. However, when a synchronous DRAM is realized by extending such a conventional technique, the synchronous DRA
A counter for realizing an interleave mode (also called an Intel scramble mode) and a sequential mode for realizing a column address specified in M burst mode (also called a wrap mode). Two types of counters, a counter and the like, are required, which complicates the configuration of the column address generation circuit.

The present invention aims to simplify the column address generation circuit in the synchronous DRAM.
A further specific object of the present invention is to realize two types of column address scanning designated in the burst mode with one type of counter.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a counter that makes a stepping motion based on the set initial value, an exclusive logic circuit for performing an exclusive logical operation between the output value of this counter and the initial value of the column address, and the column address A column address generation circuit is provided that includes a first mode in which an initial value is involved in the exclusive logical operation and a control logic for switching a second mode in which the initial value of the column address is not involved in the exclusive logical operation. . At this time, the control logic controls the logic level of the input terminal of the exclusive logic circuit so that the output value of the exclusive logic circuit changes in response to the output value of the counter regardless of the initial value of the column address. Can be configured to include a switch element for fixing the. The initial value of the stepping operation of the counter is set to all zeros in the first mode, and is made equal to the initial value of the column address in the second mode.

[0009]

According to the above means, the first mode in which the initial value of the column address is involved in the exclusive logical operation and the second mode in which the initial value of the column address is not involved in the exclusive logical operation are switched. The configuration of the column address generation circuit including the control logic makes it possible to realize two types of column address scanning specified in the burst mode with one type of counter. Achieve simplification.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of the structure of a synchronous DRAM which is an embodiment of the present invention.

The synchronous DRAM shown in FIG.
Although not particularly limited, by a known semiconductor integrated circuit manufacturing technique, it is formed on one semiconductor substrate such as single crystal silicon, and a bit having a burst length preset by a mode setting cycle is clocked from an input column address. By internally incrementing in synchronization with the clock CLK from the input terminal 11, a burst operation of continuously selecting and inputting / outputting data becomes possible.

The memory cell array 2 is not particularly limited.
0A and a memory cell array 20B are formed. The memory cell arrays 20A and 20B include a plurality of word lines WL arranged in parallel with each other and a plurality of complementary bit lines BL arranged so as to intersect the word lines WL. , And a plurality of dynamic memory cells MS arranged in a lattice at intersections of the word lines WL and the complementary bit lines BL.

The word lines WL of the memory cell arrays 20A and 20B are coupled to word drivers (not shown) arranged in the subsequent stages of the row address decoders 21A and 21B corresponding to the memory cells, and the row address decoders 21A and 21B are connected. Based on the decoded output of 21B, one word line in each of the memory cell arrays 20A and 20B is selectively driven to the selected level.
Although not particularly limited, the row address decoders 21A and 21B are supplied with the internal address signals AX0 to AXi in synchronization with the clock CLK from the row address buffer 24 arranged in the preceding stage. Further, the bit lines BL of the memory cell arrays 20A and 20B are coupled to a column selection switch (not shown) which is driven on / off based on the decode output of the corresponding column address decoders 19A and 19B, and selected by this column selection switch. By coupling the generated bit line to the common data line, desired memory cell data can be read and data can be written in the memory cell. Although not particularly limited, the column address decoders 19A and 19B are supplied with the output of the column address bus driver 23 arranged in the preceding stage thereof in synchronization with the clock CLK.

In the synchronous DRAM of this embodiment, the row address signal and the column address address signal share the address input terminal group 30. That is, the start address of the burst operation is taken in row / column order in synchronization with the clock CLK by the address multiplex. The row address signal is taken in through the row address buffer 28 in synchronization with the row address strobe signal RAS * (* means row active or signal inversion), and this is taken in by the row address predecoder 25 at the subsequent stage.
Are pre-decoded by. This predecode signal is input to the address bus driver 24 in the subsequent stage, and the address bus driver 24 drives the row address bus. The column address signal is a column address strobe signal CA.
It is taken in via the column address buffer 29 in synchronization with S *. The least significant bit AY0 of the column address signal
However, since it is used as an operation control signal of the data selectors 16A and 16B, bits other than the least significant bit are
It is supplied to the column address generation circuit 27.

As will be described in detail later, the column address generation circuit 27 has an increment counter that performs a stepping operation based on the set initial value, and an exclusive logic between the output value of the increment counter and the initial value of the column address. An exclusive logic circuit for performing an operation and a control logic for controlling the exclusive logic operation according to a set mode are included so that a column address is generated based on the output of the exclusive logic circuit. It has become.

The least significant bit of the column address is used to select the memory cell arrays 20A and 20B and is input to the data selectors 16A and 16B as its operation control signal. That is, main memories 18A and 18B for amplifying the data on the common data line are arranged,
Data selectors 16A, 16 arranged correspondingly
With B turned on, the main memories 18A, 18
The output of B is selectively transmitted to the input / output buffer 14 in the subsequent stage, and can be externally output via the input / output buffer 14 and further the I / O (input / output) terminal 13. The clock CLK input from the outside is input to the timing generator 12, and the timing generator 12 is configured to generate the operation timing signal of each unit.

At the time of data reading, although not shown in the figure, the data of the selected word line is amplified by the sense amplifiers provided in the respective memory cell arrays and then latched by the latch circuit (both are shown in the figure. (Not shown), the signal of the selected bit line is amplified by the main amplifiers 18A and 18B and then output to the data selector via the data bus. The least significant bit of the column address is assigned for data selection in the data selectors 16A and 16B, and one bit is simultaneously selected in each of the memory cell arrays 20A and 20B. Therefore, data for two cycles of the clock CLK is output to the data selectors 16A and 16B. The least significant bit of the column address and the clock are used to convert the data into the data of each cycle and the data is transmitted to the input / output buffer 14.

The data increment in the burst direction (column address direction) can be performed by incrementing the column address generating circuit, which is incremented by using the output of the column address buffer 29 as an initial value, in a cycle other than the lowest column address. It is said that While the data selectors 16A and 16B convert the double-cycle data into the input / output buffer 14 and output the converted double-cycle data, the next 2 bits are stored in the memory cell arrays 20A and 20B.
It is selectively output from B. Similarly, at the time of data writing, the data input to the input buffer 14 every cycle is allocated by the data selectors 16A and 16B, and the data is written to the memory cell array 19A and 19B in a double cycle.

Next, the details of the column address generating circuit 27 will be described.

As shown in FIG. 2, the column address generation circuit 27 has an increment counter 201 capable of stepping operation based on the set initial value, an address comparison EOR circuit 202 for each position, and a 1st address for each position counter ( A setting circuit 204 for setting an initial address),
1 in the EOR (exclusive OR) circuit for address comparison
Set circuit 205 for setting st address, initial value of column address and EOR circuit 202 for address comparison
, And a multiplexer 203 for selecting the output of, and is basically configured as shown in FIG. still,
In FIG. 3, one of the column addresses of multiple bits is used.
The configuration for bits is typically shown.

The increment counter circuit 201 is mainly composed of a counter unit 32 having a counter control signal input terminal, a carry signal input / output terminal and the like, and performs a count-up operation by the counter control signal. The set circuit 204 includes a set address latch circuit 31 for holding a set address, a switch S1 formed by coupling a p-channel type MOS transistor and an n-channel type MOS transistor, and a switch S1 for switching the column related set signals CSET, MSGB. A 2-input NAND circuit 36 and an inverter for control based on (3), an n-channel MOS transistor M1 for fixing the output terminal of the counter unit 32 to the ground level, and this MO
The 2-input NAND circuit 40 and the inverter 41 for controlling the SFET M1 based on the column set signal CSET and the burst mode switching signal MRGT3, and the MR by inverting the burst mode switching signal MRGT3
It includes an inverter 42 for obtaining GB3. The address comparison EOR circuit 202 includes an EOR gate 33, and a set circuit 205 of the EOR gate 33 outputs the output (set address) of the set address latch circuit 31 to the EO.
A switch S2 for transmitting to one input terminal of the R gate 33, and a switch S2 for switching the column system set signal CSE
T, 2-input NAND gate 38 and inverter 3 for controlling based on the burst mode switching signal MRGT3
9. An n-channel MOS transistor M2 for fixing one input terminal of the EOR gate 33 to the ground level is included. The multiplexer 202 also includes two clocked inverters 34 and 35, and an inverter 43 for controlling the clocked inverters based on the column set signal CSET.

Burst mode addressing is shown in FIG.

The sequential (serial scan) mode in the burst mode is realized as follows.

By turning off the n-channel type MOS transistor M1 and turning on the switch S1, the 1st address (start address) written in the column address latch is set in the increment counter, and at the same time, the n-channel type MOS transistor M2 is set. (At this time, the switch S2 is in the off state) to turn on the logical state of one input terminal of the EOR gate 33,
Fix to the ground level (0 level). Thereby,
A path is formed in which the output of the counter unit 32 is through-outputted to the multiplexer 202 at the subsequent stage. By counting up the counter unit 32 in this state, the sequential mode is enabled.

The interleave mode in the burst mode is realized as follows.

The interleave mode of the burst mode is
This is address scanning in which each bit changes every n to the nth power (n is a digit) in the binary representation. Therefore, in this embodiment, the counter unit 32 counts up from the reset state (A0, A1, A2 = 0, 0, 0), and the carry point of the counter 32 is used as the toggle timing for each digit. To realize the interleaved mode operation of this burst mode, FIG.
In the circuit of, the n-channel MOS transistor M1
(At this time, the switch S1 is turned off) and the counter unit 32 is reset (all zero is set), and at the same time, the switch S2 (at this time, the n-channel MOS transistor M2 is turned off). The 1st address activated and held in the set address latch circuit 31 is set to the input terminal of the EOR gate 202. This forms a path for comparing the output of the counter unit 32 and the set address. In this state, counting up the counter unit 32 enables scanning in the interleave mode.

Since the 1st address in the chip uses the set address itself, the 1st address written in the column address latch is used as the address inside the chip by using the set signal of the counter. The output of the EOR gate 33 is used after the second address. This is realized by the selection operation of the multiplexer 202.

Here, as an extension of the prior art, Synchronous D
When a RAM is implemented, two types of counters are required, a counter for implementing the interleave mode and a counter for implementing the sequential mode, for scanning the column address specified in the burst mode of the synchronous DRAM. Therefore, the configuration of the column address generation circuit becomes complicated, but in the present embodiment, one type of increment counter 201 can be shared in two types of column address scanning designated in the burst mode. Therefore, the column address generation circuit in the synchronous DRAM can be simplified as compared with the above case.

FIG. 5 shows the increment counter 20.
1 and a more detailed configuration example of the set circuit 204, and FIG. 6 shows a more detailed configuration example of the address comparison EOR circuit 202, the set circuit 205, and the multiplexer 203.

The burst mode switching signal MRGT3 used in this circuit is fixed at a high level when the burst mode is the interleave mode, and fixed at a low level when the burst mode is the sequential mode.

As shown in FIG. 5, although not particularly limited, the increment counter 201 is composed of a 2-input NOR gate 51, clocked inverters 58 to 63, and inverters 52 to 57 connected to each other. The counter control signal ICLK1T and the column system set signal CSET are taken in via the 2-input NOR gate 51, and complementary level control signals CFBMST and CFBMSB are generated. The complementary level control signals CFBMST and CFBMSB are used for controlling the operation of the latch circuit formed by coupling the clocked inverter 63 and the inverter 54 and the latch circuit of the same structure in the multiplexer 203. Further, by coupling the clocked inverter 62 and the inverter 57, a latch circuit for holding the counter output state is formed, and this latch circuit has the counter control signal ICLK2T and its inverted by the inverter 56. The operation is controlled by signals.

The set circuit for setting the increment counter 201 is not particularly limited, but the 2-input NAND gates 64 and 65, the clocked inverter 6 are provided.
6, an inverter 67, 68, and a p-channel type MOS transistor M3 are connected. The NAND gate 64 obtains a negative logical product of the column system set signal CSET and the burst mode switching signal MRGT3, and controls the switch operation of the p-channel type MOS transistor M3 coupled to the high potential side power source Vcc according to this output. It is supposed to be done. The output of the NAND gate 64 is I
It is supplied to the address comparison EOR circuit 202 as LASP. Further, the burst mode switching signal MRGT3
Is inverted by the inverter 67 and the negative logical product of the column system set signal CSET is obtained.
5, the operation of the clocked inverter 66 is controlled according to the negative logical product output. Further, the negative logical product output of the NAND gate 65 is the inverter 68.
The control signal AST is formed by being inverted by
This control signal AST is used for the address comparison EOR circuit 20.
2 is supplied.

The initialization operation of the increment counter 201 is performed by the set circuit 204 while the input signal CSE is at the high level. That is, when the address set signal ICSEB (a signal that goes to a low level when set: normally a high level) is set to a low level, the input signal CSE goes to a high level and the MRG
One of the two paths (for interleave mode or for sequential) of the set circuit 203 is selected by T3, and the initial value of the increment counter 201 is output to the output node AA. Is initialized.

As shown in FIG. 6, E for address comparison is used.
The OR circuit 202 is configured to include clocked inverters 71 to 73 and inverters 75 to 76, although not particularly limited, and the set circuit 205 thereof is not particularly limited, but the clocked inverter 70, the inverter 74, and the p channel. Type MOS transistor M4 is coupled.

The clocked inverter 70 for taking in CSABN as the start address is the set circuit 20.
The operation is controlled based on the output ILASP of the NAND gate 64 in FIG. The output terminal of the clocked inverter 70 has a clocked inverter 71 and an inverter 76.
And a latch circuit composed of
p-channel MOS transistor M coupled to s
4, further coupled to the clocked inverter 73.
When the p-channel MOS transistor is turned on by the control signal AST, the output terminal of the clocked inverter 70, the clocked inverter 71 and the inverter 76.
The input terminal of the clocked inverter 73 and the latch circuit constituted by and are set to the low potential side power source Vss level (low level).

The setting operation of the address comparing EOR circuit 202 is carried out by the setting circuit (FIG. 4) at the same timing as the counter setting circuit 204. As the comparison address set in the address comparison EOR circuit 202, the 1st address of each position is set in the interleave mode, and the comparison address and the increment counter 2 are set.
The output of the EOR circuit 202 is output as the in-chip address CABTN. In the sequential mode, the increment counter 201
Since the output of is used as it is as CABTN, all zeros are set in the address comparison EOR circuit 202, and the address comparison EOR circuit 202 is set to the through pass state.

In the interleave mode and the sequential mode, since the 1st column address used in the chip is the same address, the multiplexer 2 is simultaneously initialized with the initialization operation of the increment counter 201.
At 03, it is output to the in-chip address CABTN using the set address latch, and the path from the address comparison EOR circuit 202 is used for the 2nd (second) address and thereafter.

The multiplexer 203 is composed of clocked inverters 78 to 80 and inverters 81 to 84, which are not particularly limited. Address set signal ICSEB is input to clocked inverter 78 via inverters 81, 82, and 83 as its operation control signal. The output of the inverter 83 is a column system set signal CSET. EOR for address comparison above
The outputs of the clocked inverters 72 and 73 in the circuit 202 are taken in by the clocked inverter 79. This clocked inverter 79
Complementary level counter control signals ICLK1T, ICLK
It is controlled by 1B. The clocked inverters 78 and 79 are alternatively turned on,
The output is held in the latch circuit composed of the clocked inverter 80 and the inverter 84 in the subsequent stage, and its output CA
BTN is used as the output of this address generation circuit. The clocked inverter 80 has a complementary level control signal CF.
The operation is controlled by BMST and CFBMSB.

FIG. 7 shows the operation timing of the circuit of this embodiment.

The column address generating circuit 27 has a counter control signal ICLK1T, as shown in FIG.
And ICLK2T are controlled to control the increment counter 201. This counter control signal ICLK
1T and ICLK2T are basically in the opposite phase relationship.
When the address set signal ICSEB is at low level, the counter control signals ICLK1T and ICLK2
Both T are at low level. The counter control signal ICLK2T is a signal that is set as one shot pulse in synchronization with the rising edge of the address set signal ICSEB or the falling edge of the counter control signal ICLK1T.

Increment counter 201 and EOR for address comparison by the address set signal ICSEB
After initializing the circuit 202, the counter control signal ICLK
1-shot pulse at 2T high level causes CCO
The information (address) of CCSMTN which is the next address of TN is taken in by the through latch of the next stage by the counter control signal ICLK2T, and the information (address) of CCSMTN is output to the address comparison EOR circuit 202. The address comparison EOR circuit 202 compares the information (address or L: VSS) set in the address comparison EOR circuit 202 with the information (address) of CCSMTN for each position and outputs the result to the multiplexer 203. . When the counter control signal ICLK1T is at a high level, the multiplexer 203 has an E for address comparison.
The path connected to the OR circuit 202 is activated, and the output of the address comparison EOR circuit 202 is output as CABTN which is the in-chip column address.

Further, the CCOTN of each counter is output to the carry control circuit, and CINTN and CI of the upper counter are output.
By generating the NBN, the increment counter 20
Carry of 1 is controlled (CINBN is CINTN
The opposite phase). 2 is the output of the address latch, that is, the start address (CS
ABN is the opposite phase of CSATN).

Even if the column address generating circuit 27 is configured as described above, one type of increment counter 201 can be shared in two types of column address scanning designated in the burst mode, so that the column address in the synchronous DRAM can be shared. The generation circuit 27 can be simplified, and the same operational effect as that of the circuit shown in FIG. 3 can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, the case where the EOR (exclusive OR) gate is applied has been described in the above embodiment, but an ENOR (exclusive negative OR) gate may be applied instead of the EOR. In the case of the EOR gate, the input terminal of the EOR gate is fixed to the low level (0 level) in the sequential mode, but when the ENOR gate is applied, the input terminal is fixed to the high level (1) level. To do so.

In the above description, the case where the invention made by the present inventor is applied mainly to the synchronous DRAM which is the field of application which is the background of the invention has been described, but the present invention is not limited to this. It can be applied to various data processing devices including.

The present invention can be applied on condition that at least a column address generation circuit is included.

[0048]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the column address including the control logic for switching the first mode in which the initial value of the column address is involved in the exclusive logical operation and the second mode in which the initial value of the column address is not involved in the exclusive logical operation. By configuring the generation circuit, one type of counter can be shared in the two types of column address scanning designated in the burst mode, so that the column address generation circuit in the synchronous DRAM can be simplified. .

[Brief description of drawings]

FIG. 1 is a synchronous DRAM according to an embodiment of the present invention.
2 is an overall configuration block diagram of FIG.

FIG. 2 is a configuration block diagram of a column address generation circuit in the synchronous DRAM.

FIG. 3 is a basic configuration circuit diagram of the column address generation circuit.

FIG. 4 is an explanatory diagram of column address scanning in burst mode in the synchronous DRAM.

FIG. 5 is a detailed configuration example circuit diagram of a part of the column address generation circuit.

FIG. 6 is a detailed configuration example circuit diagram of a part of the column address generation circuit.

FIG. 7 is an operation timing chart of the synchronous DRAM.

[Explanation of symbols]

 27 column address generation circuit 16A data selector 16B data selector 18A main amplifier 18B main amplifier 31 set address latch 32 counter unit 33 EOR gate 34 clocked inverter 35 clocked inverter 201 increment counter 202 address comparison EOR circuit 203 multiplexer 204 set circuit 205 set circuit S1 switch S2 switch M1 n-channel type MOS transistor M2 n-channel type MOS transistor M3 p-channel type MOS transistor M4 p-channel type MOS transistor

Claims (3)

[Claims] 1. A semiconductor memory device having a column address generation circuit for generating a column address, wherein the column address is sequentially changed while a desired word line is selected to enable continuous access of memory cells. In the above, the column address generation circuit includes a counter that performs a stepwise operation based on the set initial value, and an exclusive logic circuit that performs an exclusive logical operation between the output value of this counter and the initial value of the column address. A first mode in which the initial value of the column address is involved in the exclusive logic operation, and a control logic for switching a second mode in which the initial value of the column address is not involved in the exclusive logic operation,
A semiconductor memory device, wherein a column address is obtained based on an output of the exclusive logic circuit. 2. The control logic controls the input terminal of the exclusive logic circuit so that the output value of the exclusive logic circuit changes in response to the output value of the counter regardless of the initial value of the column address. The semiconductor memory device according to claim 1, further comprising a switch element for fixing the logic level. 3. The initial value of the stepping operation of the counter is set to all zeros in the first mode and is made equal to the initial value of the column address in the second mode.
The semiconductor memory device described.