JPH06301487A - Sample clock phase adjusting device - Google Patents

Abstract

PURPOSE:To automatically adjust the phase of a sample clock to the optimum phase against a sampling subject signal even when the waveform of the sampling subject signal of a sampling circuit (A/D converter, etc.) becomes dull by an LPF, etc. CONSTITUTION:A sample clock phase control device is provided with a programmable delay line 32 which variably controls the phase delay of a reference clock and acquires a sample clock to be supplied to an A/D converter 22, an edge detecting circuit 36 which detects the edge of a subject signal AV2 based on the sampling data obtained by the converter 22, an amplitude measuring circuit 38 which measures the amplitude of the edge detected by the circuit 36, and a signal processing circuit 34 which controls the clock phase delay of the line 32 in order to acquire the largest amplitude measured by the circuit 38. In such a constitution, the automatic control is carried out so that the sampling point is approximately coincident with the changing apex of the signal AV2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling circuit (for example, an A / D which converts an analog signal into a digital signal).
The present invention relates to a sample clock phase adjusting device for adjusting the phase of a sample clock (or also referred to as a sampling clock) of an (analog / digital) conversion circuit.

[0002]

2. Description of the Related Art When converting an analog video signal (for example, a video signal) output from a personal computer (personal computer) into an analog video signal (for example, a video signal) having a different frequency, generally, a video as shown in FIG. It was performed by a scanning frequency conversion device (scan converter).

That is, on the personal computer 10 side, the D / A
The (digital / analog) conversion circuit 12 uses the dot clock DCk from the controller 14 to convert the digital video signal DV ₁ into an analog video signal AV ₁ , and the analog video signal AV _{1 is used} for EMI (electromagnetic interference) measures. An analog video signal AV ₂ is output to the video scanning frequency conversion device 20 side via an LPF (low pass filter) 16.

On the video scanning frequency conversion device 20 side, A
A / D (analog / digital) conversion circuit 22 is a PLL
(Phase locked loop) samples an analog video signal AV ₂ from the PC 10 side in the sample clock from circuit 24 into a digital video signal DV _2, the the digital video signal DV ₂ PLL circuit 24
Write to the memory 26 using the memory control signal from.
Then, using the memory control signal from the controller 28, the digital video signal DV ₂ read from the memory 26 at different speeds is converted into an analog video signal AV ₃ by the D / A conversion circuit 30 using the reproduction clock from the controller 28.
Convert to.

The controller 14 on the personal computer 10 side outputs a memory control signal to a built-in memory, and
H to the PLL circuit 24 on the video scanning frequency conversion device 20 side
It outputs a D (horizontal synchronization) signal and a VD (vertical synchronization) signal. Further, the controller 28 on the video scanning frequency conversion device 20 side outputs an HD signal and a VD signal.

[0006]

However, in the conventional example shown in FIG. 4, the A / D conversion circuit 22 on the video scanning frequency conversion device 20 side is switched from the personal computer 10 side by the sample clock from the PLL circuit 24. Of the analog video signal AV ₂ of
Since the PLL circuit 24 converts the sample clock into V ₂ and the sample clock is phase-synchronized with the synchronizing signal (HD signal, VD signal) from the personal computer 10 side, this synchronizing signal (HD signal, VD signal) and analog video If the phase relationship with the signal AV ₂ is not appropriate, the analog video signal AV ₃ converted by the video scanning frequency conversion device 20 will be the original analog video signal A.
There is a problem that does not correctly play the V _1.

For example, as shown in (b) of (a) of FIG. 5, when the original analog video signal AV ₁ corresponds to 1 dot or a vertical line of 1 dot, or (b) of FIG.
When the original analog video signal AV ₁ corresponds to a state where the screen is brighter than a certain part as shown in (b) of (2), if the phase relationship between the analog video signal AV ₁ and the sample clock is not appropriate, There is a problem that image quality is deteriorated. 5 (a) and 5 (b) shows the dot clock DCk.

That is, the analog video signal AV ₂ appearing at the output side of the LPF 16 in FIG.
If the waveform is blunt as shown in (c) of
When the sampling point by the sample clock having the same frequency as the clock DCk is the optimum point indicated by the downward arrow ↓ in the figure, the A / D conversion circuit 22, the memory 26 and the D / A
Analog video signal AV ₃ output via the conversion circuit 30
The waveform of is almost the same as the original analog video signal AV _{1 as} shown in (d) of (a) of FIG. 5, but the sampling point is shifted and the worst point of the worst arrow indicated by the upward arrow ↑ is shown. At this time, the waveform of the analog video signal AV ₃ is as shown in FIG.
As shown in (e), a signal corresponding to a 2-dot vertical line or a 2-dot vertical line having a small amplitude results in deterioration of image quality.

Further, when the analog video signal AV ₂ appearing at the output side of the LPF 16 in FIG. 4 has a blunt waveform as shown in FIG. 5 (b) (c), it has the same frequency as the dot clock DCk. When the sampling point by the sample clock is the optimum point indicated by the downward arrow ↓ in the figure, the waveform of the analog video signal AV ₃ is as shown in FIG.
Of, as shown in (d), but almost the same as the original analog video signal AV _1, when the worst point indicated displaced sampling points upward arrow ↑ in the figure, an analog video signal AV ₃ waveforms Is, as shown in (e) of FIG.
The signal corresponds to a signal having a gentle change, and the image quality deteriorates.

The present invention has been made in view of the above problems, and an analog video signal (for example, a video signal) of a personal computer.
Provide a sample clock phase adjustment device that can automatically adjust the phase of the sample clock to the optimum phase for the analog video signal to be sampled, even if the waveform becomes dull due to LPF, etc. The purpose is to do.

[0011]

Means for Solving the Problems Samples according to the present invention
The clock phase adjusting device detects an edge of a signal to be sampled based on a programmable delay line that variably controls a phase delay of a reference clock and uses it as a sample clock to a sampling circuit, and sampling data by the sampling circuit. An edge detection circuit, an amplitude measurement circuit that measures the amplitude of the edge detected by the edge detection circuit, and a clock phase delay of the programmable delay line so that the amplitude measured by the amplitude measurement circuit becomes a maximum value. And a control circuit that operates.

[0012]

The programmable delay line variably controls the phase delay of the reference clock and outputs it as a sample clock to the sampling circuit (for example, A / D conversion circuit). Therefore, the sampling circuit outputs sampling data obtained by sampling the sampling target signal (for example, analog video signal) with the sample clock.

The edge detection circuit detects the edge of the signal to be sampled based on the sampling data by the sampling circuit, the amplitude measurement circuit measures the amplitude of the edge detected by the edge detection circuit, and the control circuit measures the amplitude measurement circuit. The programmable amplitude is set to the maximum value.
Controls the clock phase delay of the delay line. Therefore, the phase of the sample clock is automatically adjusted so that the sampling point substantially coincides with the peak of the change of the sampling target signal (for example, analog video signal).

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the sample clock phase adjusting device according to the present invention will be described below with reference to FIGS. 1 and 2, the same parts as those in FIG. 4 are designated by the same reference numerals.

FIG. 1 shows a basic configuration of an embodiment of the present invention. In FIG. 1, reference numeral 22 is an A / D conversion circuit as an example of a sampling circuit. The A / D conversion circuit 22 samples an analog video signal (for example, a video signal) AV ₂ output from the personal computer 10 shown in FIG. 4 with a sample clock input via a programmable delay line 32 described later. Digital video signal DV as sampling data
_It is configured to be converted into ₂ and output to the memory 26 or the like of the video scanning frequency conversion device 20 of FIG.

The programmable delay line 32
Is configured to variably control the phase delay of a reference clock based on a delay amount control signal from a signal processing circuit 34, which will be described later, and output the sample clock to the A / D conversion circuit 22. .

Reference numeral 36 denotes an edge detection circuit for detecting the edge of the sampling target signal based on the digital video signal DV ₂ output from the A / D conversion circuit 22. 38
Is an amplitude measuring circuit for measuring the amplitude of the edge detected by the edge detecting circuit 36. The signal processing circuit 34 is
The programmable delay line 3 is configured so that the amplitude data output from the amplitude measuring circuit 38 has a maximum value.
2 is configured to output a delay amount control signal.

Next, the operation of FIG. 1 will be described. The programmable delay line 32 variably controls the phase delay of the reference clock and A / D as a sample clock.
Output to the conversion circuit 22. Therefore, the A / D conversion circuit 2
2 outputs sampling data obtained by sampling a sampling target signal (for example, an analog video signal) with a sample clock.

The edge detection circuit 36 is the A / D conversion circuit 2
The edge of the signal to be sampled is detected based on the sampling data by 2, the amplitude measuring circuit 38 measures the amplitude of the edge detected by the edge detecting circuit 36, and the signal processing circuit 34 determines the amplitude measured by the amplitude measuring circuit 38. The clock phase delay of the programmable delay line 32 is controlled so as to have the maximum value. Therefore, the phase of the sample clock is automatically adjusted so that the sampling point substantially coincides with the peak of the change of the signal to be sampled.

FIG. 2 shows a concrete structure of an embodiment of the present invention. In FIG. 2, the same parts as those in FIG. In FIG. 2, 22 is an A / D conversion circuit, 32 is
Is a programmable delay line, 36 is an edge detecting circuit, 38 is an amplitude measuring circuit, and 40 is the signal processing circuit 3.
4 is a microcomputer as an example, 42 is a measurement line designating circuit, and 44 is a measurement period designating circuit.

The edge detection circuit 36 outputs the digital video signal data D output from the A / D conversion circuit 22.
A D latch circuit 46 for delaying V ₂ by one sample clock, and a subtraction circuit 48 for calculating the difference between the output data DV ₂ from the A / D conversion circuit 22 and the output data from the D latch circuit 46. And an absolute value circuit 50 that outputs the absolute value of the output data of the subtraction circuit 48, and outputs edge slope data corresponding to the slope (that is, the slope of change) of the edge of the sampling target signal of the A / D conversion circuit 22. It is configured to output.

For example, if the slope data when the amount of change of the sampling object signal in one sample clock period is 100 is expressed as 10 of 1/10, the amount of change of the sampling object signal in one sample clock period is 50. The inclination data at this time is 5 which is 1/10 of that.

The measurement line designating circuit 42 receives the HD (horizontal synchronization) signal as a Cp (clock pulse) input, and the inverted signal of the inverted VD (vertical synchronization) signal is R (reset).
The counter 52 which is an input, the Q output signal (A) of the counter 52, and the measurement line designation signal KLS (B) from the microcomputer 40 are compared, and when they match (A = B), a match signal is given. It comprises an output comparator 54.

The measurement period designating circuit 44 includes a first D-FF (flip-flop) 56 which receives the coincidence signal from the comparator 54 as a Cp input and an H level signal as a D (data) input, and the comparator 54. Second D-FF 58 having an inverted signal of the coincidence signal of Cp as an input and an inverted Q output signal of the first D-FF 56 as a D input, a Q output signal of the first D-FF 56 and a Q of the second D-FF 58. An AND circuit 60 that outputs a logical product signal with the output signal as a gate signal G. During the measurement period from the rising edge to the falling edge of the coincidence signal from the comparator 54, the AND circuit 60 outputs the amplitude measuring circuit 38.
And outputs an H level gate signal G to the second D-FF
The Q output terminal of 58 outputs a measurement end signal to the microcomputer 40.

The amplitude measuring circuit 38 compares the edge inclination data (A) from the edge detecting circuit 36 with the reference value data RD (B) from the microcomputer, and the former is larger than the latter (A> B). ), A comparator 62 that outputs a pulse signal as a detection signal, and an AND circuit 64 that outputs a logical product signal of the output signal of the comparator 62 and the gate signal G from the measurement period designating circuit 44,
A counter 66 that receives the output signal of the AND circuit 64 as a Cp input, counts the number of the edge inclination data output from the edge detection circuit 36 that exceeds the reference value data RD, and counts the count value as the edge detection number. The signal EK is output to the microcomputer 40.

Based on the adjustment command signal, the microcomputer 40 sends a measurement line designating signal KLS to the measurement line designating circuit 42 and reference value data RD to the amplitude measuring circuit 38.
A measurement start reset signal is sent to the first D-FF 56 in the measurement period designating circuit 44 and the counter 66 in the amplitude measurement circuit 38, and a second reset signal for the measurement period designating circuit 44 is supplied.
The D-FF 58 is configured to output a set signal for starting measurement.

The microcomputer 40 further takes in the edge detection number signal EK output from the amplitude measuring circuit 38 every time the measurement end signal is inputted from the measurement period designating circuit 44, and takes in the edge detection number signal EK. Are sequentially compared, and the delay amount control signal DS is output according to the comparison output.
Is repeated and the operation of outputting to the programmable delay line is repeated to find a point at which the number of detected edges output from the amplitude measuring circuit 38 is maximum, and when the maximum point is found, the delay amount control signal DS at that time is fixed. In addition, the adjustment end signal is output to the outside.

Next, the operation of the embodiment shown in FIG. 2 will be described with reference to FIG. (B) When an adjustment command signal is input to the microcomputer 40 from the outside, the microcomputer 40 first outputs a measurement start reset signal to the first D-FF 56 of the measurement period command circuit 44 and the counter 66 of the amplitude measurement circuit 38. At the same time as resetting, a set signal for starting measurement is output to the second D-FF 58 of the measurement period command circuit 44 to be set.

Next, the microcomputer 40 supplies the programmable delay line 32 with the initial value DS ₁ of the delay amount control signal DS (for example, delay amount 0) and the amplitude measuring circuit 38.
Initial value RD ₁ of reference value data RD to comparator 62 of
Are output respectively. The initial value RD ₁ is not limited to this, but is set to a low value, for example.

Then, the subtraction circuit 4 of the edge detection circuit 36
8 calculates the difference between the data DV ₂ output from the A / D conversion circuit 22 and the data output from the D latch circuit 46,
Since the absolute value circuit 50 outputs the absolute value of the output of the subtraction circuit 48, the edge detection circuit 36 outputs edge slope data corresponding to the slope of the edge of the sampling target signal of the A / D conversion circuit 22. For example, when the amount of change in the sampling target signal in one sample clock period is 100, the edge slope data 10 is output.

The counter 52 of the measurement line designating circuit 42 counts the number of HD signals for each field (every 1VD) and outputs a count value, and the comparator 54 sets the count value by the measurement line designating signal KLS. Since the coincidence signal is output when the number matches the set number, it is possible to set an arbitrary horizontal scanning line in one field by the measurement line designating signal KLS from the microcomputer 40.

The first D-F of the measurement period designating circuit 44
The F56 and the second D-FF58 are the measurement line designating circuit 4
Since it operates as a latch at the rising and falling edges of the coincidence signal of the second comparator 54, the AND circuit 60 of the measurement period specifying circuit 44 outputs the H level gate signal G during the period from the rising edge to the falling edge of the coincidence signal. It is output to the AND circuit 64 of the amplitude measuring circuit 38.

Further, the comparator 6 of the amplitude measuring circuit 38
2 is the edge inclination data (A) from the edge detection circuit 36 and the initial reference value data RD from the microcomputer.
Compared with ₁ (B), the former is larger than the latter (A> B)
At this time, a pulse signal is output, and this pulse signal is input to a counter 66 via an AND circuit 64 that opens and closes with a gate signal G from the measurement period designating circuit 44, and this counter 66
Counts the number of the edge inclination data that exceeds the reference value data RD _1, and uses the counted value as the edge detection number signal EK.
Output to the microcomputer 40 as

(B) Next, the initial value DS _{1 of} (a) above
With RD ₁ and RD ₁ fixed, the microcomputer 40 slightly changes the measurement line designation signal KLS output to the comparator 54 of the measurement line designation circuit 42 for each field, and outputs the number of edge detections output from the amplitude measurement circuit 38. The signal EK is detected, and the detected edge detection number is determined by searching for an appropriate place where the counter 66 is easy to count.

That is, an arbitrary horizontal scanning line in one field can be set by the measurement line designating signal KLS from the microcomputer 40, and the measurement line (horizontal line designated by the measurement line designating circuit 42 by the measurement period designating circuit 44 (horizontal line) can be set. During the scanning line), the H-level gate signal G is output to the AND circuit 64 of the amplitude measuring circuit 38. Therefore, the microcomputer 40 sends the measurement end signal from the measurement period designating circuit 44 (that is, Q of the second D-FF 58). Output is from H level to L
The edge detection number signal EK output from the amplitude measuring circuit 38 is fetched (that is, the edge detection number is fetched) based on the timing signal which changes to the level).

Then, the microcomputer 40 compares the fetched number of detected edges with a preset value, and if it judges that the number of detected edges is within the preset range, it is easily counted by the counter 66. Determine the measurement line as if it exists. For example, the measurement line at the substantially central portion of the display screen 70 as indicated by the dotted line KL in FIG. 3 is determined.
That is, it is possible to detect a certain number of edges or more and obtain the number of detected edges that is half the maximum count value of the counter 66 (for example, the 262th line in the middle of the 525 horizontal scanning lines in one frame). Horizontal scan line)
Search for and decide. This is because a certain number or more of edges cannot be detected in the measurement line on the screen that changes too little like the upper end of the display screen 70.

(C) When the measurement line is determined in (b), the microcomputer 40 sets the reference value data RD output to the comparator 62 of the amplitude measuring circuit 38 to the amplitude measuring circuit 38.
Set again so that the number of detected edges output from will be small.

(D) Next, the microcomputer 40 gradually changes the delay amount control signal DS output to the programmable delay line 32 for each field, and gradually increases the delay amount in the programmable delay line 32 from 0. While detecting the edge detection number signal EK output from the amplitude measuring circuit 38, the edge detection number before and after the delay amount change is repeatedly compared to search for the point at which the edge detection number becomes maximum.

(D) When the delay amount that maximizes the number of detected edges is found in (c) above, the microcomputer 40 fixes the delay amount control signal output to the programmable delay line 32 to determine the delay amount, and An adjustment end signal is output to the outside to notify that the optimum sample clock phase adjustment is completed.

In the above-described embodiment, the initial delay amount in the programmable delay line 32 is set to 0, the measurement is repeated while gradually increasing the delay amount from 0, and the point at which the number of detected edges is maximized is searched for. ,
The present invention is not limited to this, and for example, the initial delay amount in the programmable delay line 32 is set to 0.
Other values may be used, and the point at which the number of detected edges is maximized may be searched for by repeating the measurement while gradually increasing or decreasing the delay amount from this initial value.

[0041]

As described above, the sample clock phase adjusting device according to the present invention includes a programmable delay line for variably controlling the phase delay of the reference clock to be used as the sample clock for the sampling circuit, and the sampling circuit. An edge detection circuit that detects the edge of the sampling target signal based on the sampling data by, and an amplitude measurement circuit that measures the amplitude of this detection edge,
A control circuit that controls the clock phase delay of the programmable delay line so that the measured amplitude becomes the maximum value, and the phase of the sample clock changes at the sampling point at the sampling target signal (for example, analog video signal). It is configured to be adjusted automatically so that it almost coincides with the apex of.

Therefore, the signal sampled by the sampling circuit is like an analog video signal of a personal computer.
Even if the waveform is blunted by an LPF or the like, the phase of the sample clock can be automatically adjusted to the optimum one for the signal to be sampled. Therefore, when the sampling target signal is a video signal of a personal computer, it is possible to avoid image quality deterioration due to the difference in sample phase.

[Brief description of drawings]

FIG. 1 is a basic schematic configuration diagram showing an embodiment of a sample clock phase adjusting device according to the present invention.

FIG. 2 is a specific schematic configuration diagram showing an embodiment of a sample clock phase adjusting device according to the present invention.

FIG. 3 is an explanatory diagram illustrating an example of a measurement line designated by a measurement line designation circuit of FIG.

FIG. 4 is a diagram showing a schematic configuration of a conventional device in which an analog video signal (for example, a video signal) output from a personal computer side in an A / D conversion circuit (an example of a sampling circuit) on the video scanning frequency conversion device (scan converter) side signal)
FIG. 1 is a conventional schematic configuration diagram showing a device for sampling AV ₂ with a sample clock from a PLL circuit, converting it into a digital video signal DV ₂ and outputting it, and its peripheral devices.

5A and 5B are explanatory views illustrating the operation of FIG.

[Explanation of symbols]

22 ... A / D conversion circuit (an example of sampling circuit), 3
2 ... Programmable delay line 34 ... Signal processing circuit (an example of control circuit) 36 ... Edge detection circuit 38 ...
Amplitude measurement circuit, 40 ... Microcomputer (an example of control circuit),
42 ... Measurement line designation circuit, 44 ... Measurement period designation circuit,
46 ... D latch circuit, 48, 54, 62 ... Comparator, 52, 66 ... Counter, 56, 58 ... D-FF,
60, 64 ... AND circuit, DS ... Delay amount control signal, HD ... Horizontal synchronization signal, G ... Gate signal, KLS
... measurement line designation signal, RD ... reference value data, VD ...
Vertical sync signal.

Claims (2)

[Claims] 1. A programmable delay line that variably controls a phase delay of a reference clock to be a sampling clock for a sampling circuit, and detects an edge of a sampling target signal based on sampling data by the sampling circuit. An edge detection circuit, an amplitude measurement circuit that measures the amplitude of the edge detected by the edge detection circuit, and a clock phase delay of the programmable delay line is controlled so that the amplitude measured by the amplitude measurement circuit becomes a maximum value. A sample clock phase adjusting device comprising a control circuit. 2. An edge detection circuit calculates a difference between sampling data obtained by the sampling circuit and data obtained by delaying the sampling data by one sample clock, and outputs the inclination of the edge of the sampling target signal. The amplitude measuring circuit is mainly composed of a circuit, and the amplitude measuring circuit detects whether the output value of the subtracting circuit exceeds a preset reference value, and the number of outputs from the comparator within a certain period (edge slope value). 2. The sample clock phase adjuster according to claim 1, wherein the counter mainly comprises a counter for counting the number of appearances of edges exceeding a reference value.