JPH06290587A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten a writing time of the same data or a data pattern and to make writing of a certain data pattern possible. CONSTITUTION:In a memory cell array 119 constituted with word lines WL(1)- WL(n) of (n) lines selected by a row decoder and but line pairs BLP(1)-BLP(m) of (m) groups connected to a sense amplifier, after data for writing is written in a memory cell 120 on an arbitrary word line, the prescribed mode setting (function setting for batch writing) is performed. Next, /RAS is made active, after the word line is activated, a sense amplifier activation signal SE is made active, and data is read out to the sense amplifier through BLP(1)211-BLP(m)214. And desired word lines are collectively activated, data held in the sense amplifier is written in memory cells on each word line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a data writing function.

[0002]

2. Description of the Related Art In recent years, large capacity and high performance of dynamic random access memory (hereinafter referred to as DRAM) have greatly contributed to the achievement of high functionality of computer systems and video equipment. Furthermore, in order to greatly improve the image processing function of the device, a multi-port memory with a serial access port added to a general-purpose DRAM is used. This multi-port memory is also called a video memory because it is mainly used in a system that handles image data, and in addition to the random access function, it is equipped with a serial access function that corresponds to the format and handling of image data as a standard function. Furthermore, to handle data at higher speed,
Recently, it is equipped with various optional functions. Among them, regarding the write function of the same data, for example, there is a flash write function described in '91 Mitsubishi Semiconductor Memory DRAM Edition DataBook P.4-37, which is mainly used for high-speed screen clear execution. ing.

A flash write function, which is an example of the conventional same data write function, will be described below with reference to the drawings.

FIG. 29 is equipped with a flashlight function.
1 is a block diagram of a 1 Mbit dual port DRAM. Further, FIG. 30 shows an operation timing chart of the flash write function.

In FIG. 29, 101 is / RAS and 102 is
/ CAS, 103 is a write enable signal (hereinafter, / WE),
104 is / OE, 107 is a special function designation signal (hereinafter, DSF)
Is. Further, 108 is an address signal (A0 to A8), 109
Is a write mask signal / data input / output signal (W / IO0 to W / IO
3). 122 is an address buffer, 129 is a 1M memory cell array, and 124 is the 1M memory cell array 12.
A row decoder for selecting a word line in 9;
A column decoder for selecting the sense amplifier 127 to which the bit line in the memory cell array 129 is connected, a random input / output of data between the sense amplifier 127 and the outside, and a timing generation circuit for the write mask signal 133. A data input / output buffer for transmission to 121. The timing generation circuit 121 includes 101 to 10
7 and 133 signals are input, and each circuit block 12 in the figure
2 is a timing generation circuit that generates a signal for controlling 2 to 132. Reference numeral 132 is a flash write data register.

The operation of the flash write function of the 1 Mbit dual port DRAM configured as described above will be described below.

In the flash write function, first, the data to be written in the memory cell array is taken into the chip (load color cycle), and subsequently, the operation (flash write cycle) of writing the data one row (one word) at a time is performed for all rows. This is a function of writing the same data to all memory cells by performing (all words). As a result, the total writing time is shortened to about 1 / (the number of bits simultaneously written) as compared with the writing of the same data by random access.

First, the load color cycle, which is an essential cycle in the flashlight function, will be described. As shown in FIG. 30, at the fall of / RAS101, / CAS102, / WE103, / OE104 and DSF107 are set high, and the load color cycle is set. Then / CAS
102 and / WE103 are turned off, and at the same time, data for writing to the memory cell is input. This data is stored in the flash write data register 132 via the data input / output buffer 130. Finally, / RAS101, / C
AS 102, / WE 103, / OE 104, and DSF 107 are all set to high to put them in a standby state.

Next, the flash write cycle in the flash write function will be described. As shown in FIG. 30, when / RAS101 falls, / CAS102, / OE
The flash write cycle is set by setting 104 and the DSF 107 to high and / WE103 to low, and at the same time, the row address 108 for writing the data stored in the load color cycle is input. At this time, W / IOn is set high (non-mask) for the plane to which data is written, and W / IOn is set low (mask) for the plane not to be written. The plane here means each I / at the time of random access.
It means a memory cell array corresponding to O. Next, after the word line of each plane (each memory cell array) is activated by the designated row address, the data in the flash write data register 132 is transferred to the sense amplifier 127 of the non-mask plane, The data is written in the memory cell. In the masked plane, the flash write data register 1
The data in 32 is not transferred, but the data read to the bit line is amplified by the sense amplifier 127 and restored in the memory cell. Finally, / RAS101 is set high and precharge is performed to enter the standby state.

[0010]

However, in the above configuration, when writing the same data to all the memory cells in the memory cell array, the / RAS cycle of the number of row addresses (the number of activated word lines) is repeated. Since it must be done, of course, precharging is also performed the above number of times, which is faster than writing the same data by random access, but the total writing time is considerably longer, and the memory capacity will be further increased in the future. As the process progresses, the writing time becomes longer and longer. Further, there is a problem that writing a certain data pattern (for example, a test pattern such as a checker pattern used at the time of a memory test) into the memory cell array cannot be realized with the above configuration. .

In view of the above problems, the present invention provides a semiconductor memory device capable of writing the same data or data pattern at high speed.

[0012]

Further, a first aspect of the present invention is provided.
According to another aspect of the semiconductor memory device of the present invention, the semiconductor memory device includes a memory cell array having a plurality of word lines and a plurality of bit lines, a row decoder for selecting the word lines, and a sense amplifier column connected to the bit lines. In the device, under a predetermined mode setting, within one / RAS cycle, the word line is activated by the address specified at the / RAS input, and the data of the memory cell on the word line is read to the sense amplifier row. After a certain period of time, different one or a plurality of word lines are activated to write the data to the memory cells on the one or a plurality of word lines. is there.

According to a second aspect of the present invention, a semiconductor memory device has a memory cell array having a plurality of word lines and a plurality of bit lines, a row decoder for selecting the word lines, and a bit line. In a semiconductor memory device having a plurality of sets of sense amplifiers to be connected, a word in a memory cell array selected by an address specified at the time of / RAS input in one / RAS cycle under a predetermined mode setting. Line and a sense amplifier column connected to the selected memory cell array, and at the same time activate one or a plurality of word lines in the non-selected memory cell array, to activate the memory cells on the word line in the selected memory cell array. After reading the data to the sense amplifier row, transfer the data to the sense amplifier row connected to the non-selected memory cell array, After a fixed time, the sense amplifier row connected to the non-selected memory cell array is activated to write the data to the memory cells on the one or more word lines. It is a thing.

In a semiconductor memory device according to a third aspect of the present invention, a memory cell array having a plurality of word lines and a plurality of bit lines and row decoders for selecting the word lines are provided on the left and right of the sense amplifier column. In a semiconductor memory device in which the sense amplifier row is arranged and connected to the bit lines of the left and right memory cell arrays via a shared switch, under a predetermined mode setting, within one / RAS cycle, at the time of / RAS input The word line in the memory cell array selected by the designated address is activated, and also one or more word lines are activated in the non-selected memory cell array, and at the same time, the non-selected memory cell array and the sense amplifier row are connected. After deactivating the shared switch control line, the data of the memory cell on the word line in the selected memory cell array Read to the sense amplifier array,
After a certain period of time, by activating a shared switch control line that connects the non-selected memory cell array and the sense amplifier row, the data is written in the memory cells on the one or more word lines. It is characterized by taking.

In the semiconductor memory device according to a fourth aspect of the present invention, a memory cell array having a plurality of word lines and a plurality of bit lines and row decoders for selecting the word lines are provided on the left and right of the sense amplifier column. In a semiconductor memory device in which the sense amplifier row is arranged and connected to the bit lines of the left and right memory cell arrays via a shared switch, under a predetermined mode setting, within one / RAS cycle, at the time of / RAS input A shared switch control line that activates a word line in a memory cell array selected by a designated address and connects the selected memory cell array and the sense amplifier row and a shared switch that connects a non-selected memory cell array and the sense amplifier row. Continuing to activate the control lines, the memory cells on the word lines in the selected memory cell array are deactivated. Data to the sense amplifier column, and after a certain time, in the non-selected memory cell array, one or more word lines are activated to store the data in the memory cells on the one or more word lines. It is characterized in that it has a writing structure.

A semiconductor memory device according to a fifth aspect of the present invention is a semiconductor memory device including a memory cell array having a plurality of word lines and a plurality of bit lines,
A switch for connecting to the bit line and the VDD line and the VSS line is provided, and the bit line is connected to the VDD line or the VSS line after / RAS input within one / RAS cycle under a predetermined mode setting, A configuration in which high-level or low-level data is collectively written to memory cells on the one or more word lines by activating one or more word lines in the memory cell array It is characterized by taking.

[0017]

According to the constitutions of claims 1, 2, 3, and 4 of the present invention,
When the same data is written to all the memory cells in the memory cell array, the writing can be completed in one / RAS cycle, so the write operation time is about 1 / (compared to the conventional flash write function. (Total number of words)
Can be Furthermore, it is possible to write a certain data pattern to the memory cell array, and the write operation time is about 1 / (the number of bits simultaneously written × the total number of words / data pattern 1) of the write time by random access. Number of words required for group)
Can be

Further, according to the configuration of claim 5 of the present invention, when the same data is written in all the memory cells in the memory cell array, the writing can be completed in one / RAS cycle, so that the write operation time is It can be reduced to about 1 / (total number of words) as compared with the conventional flash write function.

[0019]

Embodiments of the present invention will be described with reference to the drawings.

First, FIG. 1 shows a block diagram of a general dual port memory. In FIG. 1, 101 is / R
AS, 102 is / CAS, 103 is / WE, and 104 is / OE.
Reference numeral 108 is an address (A0 to A8), and 109 is a data input / output signal (IO0 to IO3). 122 is an address buffer, 119 is a memory cell array, 124 is a row decoder for selecting a word line in the memory cell array 119, 1
Reference numeral 25 is a column decoder for selecting the sense amplifier 127 to which the bit line in the memory cell array 119 is connected,
Reference numeral 130 is a data input / output buffer for randomly inputting / outputting data between the sense amplifier 127 and the outside.
Reference numeral 121 denotes a timing generation circuit, which is a timing generation circuit which receives signals 101 to 107 and generates signals for controlling the circuit blocks 122 to 131 in the figure. This configuration is common to all the embodiments of the present invention.

(Embodiment 1) FIG. 2 shows a block diagram of a core portion including a memory cell array, a sense amplifier, and a row decoder of a semiconductor memory device according to Embodiment 1 of the present invention. In FIG. 2, the memory cell array 119 has n word lines WL (1) 20 selected by the row decoder 124.
1 to WL (n) 210 and sense amplifier 127 are connected m
A set of bit line pairs BLP (1) 211 to BLP (m) 214 are formed, and m × n memory cells 120 are arranged. 23
0 is a sense amplifier activation signal (SE), as shown in FIG.
In the timing generation circuit 121, the signal is set so as to activate the sense amplifier 127. In this embodiment, a predetermined mode setting (batch writing function setting)
At the time of batch writing of data, the row decoder 124 is controlled to activate a plurality of word lines at the same time.

FIG. 3 shows a timing chart of the same data write operation to all the memory cells in the semiconductor memory device of this embodiment having the above-mentioned structure. The operation will be described below. First, write data in advance with WL (1)
Data is written in the memory cell 120 on 201 and a predetermined mode is set. Then activate / RAS101,
After activating WL (1) 201 with an externally specified address, SE 230 is activated and BLP (1) 211-
Data is read to the sense amplifier 127 via the BLP (m) 214 (data reading). Then, collectively WL (2) 2
02-WL (n) 210 is activated, and the data stored in the sense amplifier is used for the memory cell 1 on each word line.
Write data to 20 (batch write). Finally, the predetermined mode is released, and the word line and SE230 are reset at the rising edge of / RAS101.

As described above, according to this embodiment, all the memory cells in the memory cell array are activated by simultaneously activating a plurality of word lines at the time of batch writing after reading data under a predetermined mode setting. When writing the same data, since it is completed in one / RAS cycle, the total write time can be reduced to about 1 / (total number of words) as compared with the conventional flash write function. Furthermore, it is possible to write a certain data pattern to the memory cell array, and the write operation time is about 1 / l of the write time by random access.
(Number of bits written simultaneously × total number of words / number of words required for one data pattern set).

(Embodiment 2) FIG. 4 shows a block diagram of a core portion including a memory cell array, a sense amplifier and a row decoder of a semiconductor memory device according to Embodiment 2 of the present invention. In FIG. 4, those having the same functions as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. Reference numeral 240 denotes a data transfer line used for data transfer between the memory cell arrays 119a and 119b, the number of which is the same as that of bit line pairs. 250
Reference numerals a and 250b are column selection lines (hereinafter, Y) for selecting the sense amplifiers of the respective memory cores, and in the present embodiment, the sense amplifiers are collectively selected when a predetermined mode is set (batch write function setting).

FIG. 5 shows a timing chart of the same data write operation to all memory cells in the semiconductor memory device of the present embodiment having the above-mentioned structure. The operation will be described below. First, write data is written in advance in the memory cell 120 on the WL (1) 201a in the memory cell array 119a to set a predetermined mode. Next, / RAS101 is activated, and WL (1) 201 in the memory cell array 119a is activated by an externally specified address.
a is activated and at the same time WL in the memory cell array 119b is activated.
(1) 201b to WL (n) 210b are activated. afterwards
The SE 230a is activated to activate the memory cell array 11
Data on WL (1) 201a in 9a is converted to BLP (1) 211a
After reading the data to the sense amplifier 127a via the BLP (m) 214a, the Y250a is transferred to the data transfer line 240 in the fully selected state (data read). Then, in the memory cell array 119b, the Y250b is fully selected to connect the BLP (1) 211b to BLP (m) 214b to the data transfer line 240, and the SE 230b is activated to activate the memory cells on each word line in the memory cell array 119b. Data is written to 120 (collective write cycle). Finally, the predetermined mode is released, and SE 230a and 230b are reset at the rising edge of / RAS101.

As described above, according to this embodiment, all the memory cells in the memory cell array are activated by simultaneously activating a plurality of word lines at the time of batch writing after reading data under a predetermined mode setting. When writing the same data, since it is completed in one / RAS cycle, the total write time can be reduced to about 1 / (total number of words) as compared with the conventional flash write function. Furthermore, it is possible to write a certain data pattern to the memory cell array, and the write operation time is about 1 / l of the write time by random access.
(Number of bits written simultaneously × total number of words / number of words required for one data pattern set).

(Embodiment 3) FIG. 6 shows a block diagram of a core portion including a memory cell array, a sense amplifier, and a row decoder of a semiconductor memory device according to Embodiment 3 of the present invention. 6, those having the same functions as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. In the configuration of this embodiment, the memory cell arrays 119a and 119b are connected to the sense amplifier 12.
7 are arranged on the left and right, and shared switches 137a, 13
The sense amplifier and the bit line of each memory cell array are connected via 7b. The shared switch 137
a and 137b are shared switch control signals (L)
It is controlled by (hereinafter, SSL) 260a and shared switch control signal (R) (hereinafter, SSR) 260b. Normally, when / RAS is inactive (standby), the sense amplifier and the left and right memory cell arrays are connected at the same time for precharging, but when / RAS is active (operating), the selected memory cell array is connected. Only the sense amplifier is connected to read and write data. In the present embodiment, the shared switches 137a and 137b are characterized in that the sense amplifier and the left and right memory cell arrays are simultaneously connected when data is collectively written in a predetermined mode setting (collective writing function setting).

Next, FIG. 7 shows a circuit example of the shared sense amplifier 136 in FIG. The sense amplifier 136 includes shared switches 137a and 137b, a latch type sense amplifier, and a bit line equalize / precharge signal (hereinafter referred to as EQ) 231 which controls the bit line equalize /
A source of the latch type sense amplifier, which is composed of a precharge circuit, is driven by a sense amplifier driver 135 controlled by the SE 230.

FIG. 8 shows a timing chart of the same data write operation to all memory cells in the semiconductor memory device of the present embodiment having the above-mentioned structure. The operation will be described below. First, write data is written in advance in the memory cell 120 on the WL (1) 201a in the memory cell array 119a to set a predetermined mode. Next, / RAS101 is activated, and WL (1) 201 in the memory cell array 119a is activated by an externally specified address.
a is activated and at the same time WL in the memory cell array 119b is activated.
(1) 201b to WL (n) 210b are activated, EQ231, SS
R260b is inactivated. After that, the SE 230 is activated and the WL (1) 20 in the memory cell array 119a is activated.
The data on 1a is read to the sense amplifier 127 via the BLP (1) 211a to BLP (m) 214a (data reading). After confirming the data reading, SSR260b
Are activated to connect the memory cell array 119b and the sense amplifier 127, and the data is written to the memory cells 120 on each word line in the memory cell array 119b (collective writing). Finally, release the specified mode and / RAS
At the rising edge of 101, SE230 is reset and EQ231
Activate.

As described above, according to the present embodiment, all the memory cells in the memory cell array are activated by simultaneously activating a plurality of word lines at the time of batch writing after reading data under a predetermined mode setting. When writing the same data, since it is completed in one / RAS cycle, the total write time can be reduced to about 1 / (total number of words) as compared with the conventional flash write function. Furthermore, it is possible to write a certain data pattern to the memory cell array, and the write operation time is about 1 / l of the write time by random access.
(Number of bits written simultaneously × total number of words / number of words required for one data pattern set).

(Embodiment 4) Only the points of the configuration of the semiconductor memory device according to Embodiment 4 of the present invention which are different from those of Embodiment 3 will be described. The basic configuration is as shown in FIGS. 6 and 7, but in this embodiment, the shared switches 137a and 137b are set to / RAS1 when a predetermined mode is set (batch write function setting).
Regardless of the state of 01, it is controlled so as to always connect to the memory cell array.

FIG. 9 shows a timing chart of the same data write operation to all memory cells in the semiconductor memory device of the present embodiment having the above-mentioned structure. The operation will be described below. First, write data is written in advance in the memory cell 120 on the WL (1) 201a in the memory cell array 119a to set a predetermined mode. Next, / RAS101 is activated, and WL (1) 201 in the memory cell array 119a is activated by an externally specified address.
Activates a and simultaneously deactivates EQ231. After that, the SE 230 is activated and the memory cell array 11
Data on WL (1) 201a in 9a is transferred to BLP (1) 211a-B
Data is read to the sense amplifier 127 via the LP (m) 214a (data reading). At this time, the SSR 260b is still activated, so the BL in the memory cell array 119b is
The data is written in P (1) 211b to BLP (m) 214b. After the data reading is confirmed, WL (1) 201b to WL (n) 210b in the memory cell array 119b are activated, and the data is written to the memory cells 120 on each word line in the memory cell array 119b (collective writing). Finally, the predetermined mode is released, SE230 is reset at the rising edge of / RAS101, and EQ231 is activated.

As described above, according to the present embodiment, all the memory cells in the memory cell array are activated by simultaneously activating a plurality of word lines at the time of batch writing after reading data under a predetermined mode setting. When writing the same data, since it is completed in one / RAS cycle, the total write time can be reduced to about 1 / (total number of words) as compared with the conventional flash write function. Furthermore, it is possible to write a certain data pattern to the memory cell array, and the write operation time is about 1 / l of the write time by random access.
(Number of bits written simultaneously × total number of words / number of words required for one data pattern set).

(Fifth Embodiment) FIG. 10 shows a block diagram of a semiconductor memory device according to a fifth embodiment of the present invention. Figure 10
2 having the same functions as those in FIG. 2 are denoted by the same reference numerals and the description thereof will be omitted. 138 is a bit line pair BLP (1) 2
A write power supply selection switch block that connects the 11 to BLP (m) 214 and the VDD line and the VSS line is controlled by the VDD switch control signal 233 and the VSS switch control signal 234.

Write power source selection switch block 1
Write power source selection switch 139 for 1 bit in 38
The details are shown in FIG. In FIG. 11, the write power supply selection switch 139 includes a PMOSFET in which the VDD switch control signal 233 is connected to the gate, the VDD line is connected to the source, and the BL (1) 211-1 is connected to the drain, and the VSS switch control signal 234.
/ BL (1) 21 is the inverted signal of
A series connection of PMOSFETs in which 1-2 is connected to the drain, and an NMOSFE in which the VSS switch control signal 234 is connected to the gate, the VSS line is connected to the source, and BL (1) 211-1 is connected to the drain.
The inverted signal of T and VDD switch control signal 233 is used as a gate,
It is configured by a series connection of NMOSFETs in which the VSS line is connected to the source and / BL (1) 211-2 is connected to the drain.

FIG. 12 shows a timing chart of the high / low batch write operation to all the memory cells in the semiconductor memory device of this embodiment configured as described above. The operation will be described below. First, a predetermined mode setting is performed.
Next, / RAS101 is activated and the logic of data to be written is specified from the outside. At the same time as releasing the bit line equalize / precharge, VD based on the data logic
Either the D switch control signal 233 or the VSS switch control signal 234 is activated. This allows bit line pairs
BLP (1) 211 to BLP (m) 214 are all written with either high level data or low level data. Then, all the word lines WL (1) 201 to WL (n) 210 are activated at the same time, and high-level or low-level data is collectively written (collective writing). Finally, release the specified mode, / RAS10
Bit line equalization / precharge is performed at the rising edge of 1.

As described above, according to the present embodiment, when the same data is written in all the memory cells in the memory cell array under the predetermined mode setting, the writing can be completed in one / RAS cycle. Therefore, the write operation time is about 1 time compared to the conventional flash write function.
It can be / (total number of words).

(Sixth Embodiment) FIG. 13 shows a block diagram of a semiconductor memory device according to a sixth embodiment of the present invention. FIG.
In FIG. 12, those having the same functions as those in FIG. 140 is a bit line pair BLP (1)
211 to BLP (m) 214 and a power supply (hereinafter, VPP) line boosted to a voltage higher than VDD and a VSS power supply select switch block for connecting the VPP switch control signal 23.
5 and VSS switch control signal 234.

The write power source selection switch block 1
Write power source selection switch 141 for 1 bit in 40
The details of the above are shown in FIG. In FIG. 14, the write power supply selection switch 141 includes an NMOSFET in which the VPP switch control signal 235 is connected to the gate, a VPP line is connected to the source, and BL (1) 211-1 is connected to the drain, and a VSS switch control signal 234.
To the gate, VPP line to the source, / BL (1) 211-2 connected to the drain in series, and the VSS switch control signal 234 to the gate, VSS line to the source, BL
(1) NMOSFET with 211-1 connected to drain and VPP switch control signal 235 at gate, VSS line at source, / BL
(1) It is configured by series connection of NMOSFETs in which 211-2 is connected to the drain.

FIG. 15 shows a timing chart of the high / low batch write operation to all the memory cells in the semiconductor memory device of the present embodiment configured as described above. The operation will be described below. First, a predetermined mode setting is performed.
Next, / RAS101 is activated and the logic of data to be written is specified from the outside. At the same time that the bit line equalize / precharge is released, VP is
Either the P switch control signal 235 or the VSS switch control signal 234 is activated. This allows bit line pairs
BLP (1) 211 to BLP (m) 214 are all written with either high level data or low level data. Then, all the word lines WL (1) 201 to WL (n) 210 are activated at the same time, and high-level or low-level data is collectively written (collective writing). Finally, release the specified mode, / RAS10
Bit line equalization / precharge is performed at the rising edge of 1.

As described above, according to this embodiment, when the same data is written in all the memory cells in the memory cell array under the predetermined mode setting, the writing can be completed in one / RAS cycle. Therefore, the write operation time is about 1 time compared to the conventional flash write function.
It can be / (total number of words).

By using the VPP line for writing high level data, all the switching transistors in the write power supply selection switch 141 are NMOSFETs.
Therefore, the layout area can be reduced and the control line of the write power supply selection switch can be reduced as compared with the case of the fifth embodiment including the PMOSFET and the NMOSFET.

(Embodiment 7) FIG. 16 shows a block diagram of a semiconductor memory device according to Embodiment 7 of the present invention. FIG.
2 having the same functions as those in FIG. 2 are denoted by the same reference numerals and the description thereof will be omitted. Reference numerals 146 and 147 denote row address predecode circuits, which are internal signals of / RAS101.
It is activated by the internal RAS 306, and the addresses 301 and 303 are input, and the predecode signals 302 and 30 are input.
4 is output. The address 303 is generated by the address degeneration signal 305 delayed by a certain time with respect to / RAS101 when a predetermined mode is set (collective write function setting).
This is an address degenerated in the predecode circuit 147.

FIG. 17 shows details of the predecode circuit and row decoder when the address is 6 bits. FIG. 17
In A, the degenerate address 303 is set to A0 to A3, the non-degenerate address is set to A4 and A5, and they are input to the degenerate address predecode circuits 147a and 147b and the non-degenerate address predecode circuit 146, respectively. The degenerate address predecode circuits 147a and 147b are connected to the degenerate address 303 and In
The first NAND circuit 144 input by the internal RAS 306, the output of the first NAND circuit 144, and the address degeneration signal 3
The second NAND circuit 145, to which 05 is input, outputs (predecode signals) 304-1 to 3 in normal operation.
One output of 04-4 is selected, and when one of the outputs (predecode signals) 304-1 to 304-4 is selected when a predetermined mode is set (batch write function setting), all are output by the address degeneration signal 305. The selected state is set. The non-degenerate address predecode circuit 146 is ANDed by the non-degenerate address 301 and the Internal RAS 306.
One of the outputs (predecode signal) 302 is selected regardless of the mode setting. Therefore, when a predetermined mode is set (batch write function setting), for example, when all the input addresses are 0, the WL (1) 201 in the row decoder 124 is generated by the predecode signal 304 by the degenerate address and the predecode signal 302 by the non-degenerate address. Is selected first, then WL (1) 201
The word line of WL (4) 204 ... Is selected.

FIG. 18 shows a timing chart of the same data write operation to all the memory cells in the semiconductor memory device of this embodiment having the above-mentioned structure. The operation will be described below. First, write the data for writing in WL
(1) The data is written in the memory cell 120 on 201 and a predetermined mode is set. Next, activate / RAS101 and activate predecode signals 302-1, 304a-1, 304b-1 by an externally specified address, and WL
(1) After activating 201, SE230 is activated and data is read to the sense amplifier 127 via BLP (1) 211 to BLP (m) 214 (data reading). After a certain period of time, the address degeneration signal 305 is activated so that the other predecode signals 304a-2 to 304a are activated.
-4, 304b-2 to 304b-4 are activated, and WL (2)
202-WL (4) 204 -... are activated. Then, the data held in the sense amplifier is used to write the data in the memory cells 120 on each word line (collective writing). Finally, the predetermined mode is released, and SE230 is reset at the rising edge of / RAS101.

As described above, according to the present embodiment, all the memory cells in the memory cell array are activated by simultaneously activating a plurality of word lines at the time of batch writing after reading data under a predetermined mode setting. When writing the same data, since it is completed in one / RAS cycle, the total write time can be reduced to about 1 / (total number of words) as compared with the conventional flash write function. Furthermore, it is possible to write a certain data pattern to the memory cell array, and the write operation time is about 1 / l of the write time by random access.
(Number of bits written simultaneously × total number of words / number of words required for one set of data patterns).

(Embodiment 8) FIG. 19 shows a block diagram of a semiconductor memory device according to an embodiment 8 of the present invention. Further, FIG. 20 shows details of the predecode circuit and the row decoder when the address is 6 bits. 19 and 20, those having the same functions as those in FIGS. 16 and 17 are designated by the same reference numerals and description thereof will be omitted. In the case of the present embodiment, the address degeneration signal 305 in the seventh embodiment is divided into two systems, a first address degeneration signal 305a and a second address degeneration signal 305b, and the first address degeneration signal 305a and the second address degeneration are performed at different timings. Signal 305b
Activate. The first address degenerate signal 305a and the second address degenerate signal 305b are input to the predecode circuits 147a and 147b, respectively, and the predecode signal 30 is input when a predetermined mode is set (batch write function setting).
4a-1 to 304a-4, 304b-1 to 304b-4
To select all.

FIG. 21 shows a timing chart of the same data write operation to all memory cells in the semiconductor memory device of the present embodiment having the above-mentioned configuration. The operation will be described below. First, write the data for writing in WL
(1) The data is written in the memory cell 120 on 201 and a predetermined mode is set. Next, activate / RAS101 and activate predecode signals 302-1, 304a-1, 304b-1 by an externally specified address, and WL
(1) After activating 201, SE230 is activated and data is read to the sense amplifier 127 via BLP (1) 211 to BLP (m) 214 (data reading). After a certain time, first, the address degeneration signal 305a is activated to make the predecode signals 304a-2 to 304
a-4 is activated, and WL (5) 205 ... Is activated. Next, the address degeneration signal 305b is activated to activate the predecode signals 304b-2 to 304b-4, and WL (2) 202 to WL (4) 204 and WL (6) 206 to WL
(8) Activate 208, ... Then, after activating all the desired word lines, the data held in the sense amplifier is used to write the data to the memory cells 120 on each word line (collective writing). Finally, the predetermined mode is released, and SE230 is reset at the rising edge of / RAS101.

As described above, according to the present embodiment, all the memory cells in the memory cell array are activated by simultaneously activating a plurality of word lines at the time of batch writing after reading data under a predetermined mode setting. When writing the same data, since it is completed in one / RAS cycle, the total write time can be reduced to about 1 / (total number of words) as compared with the conventional flash write function. Furthermore, it is possible to write a certain data pattern to the memory cell array, and the write operation time is about 1 / l of the write time by random access.
(Number of bits written simultaneously × total number of words / number of words required for one set of data patterns).
Further, by providing two systems of address degeneration signals, multiple selection of word lines at the time of setting a predetermined mode (collective write function setting) can be performed in a distributed manner, so that the peak current can be alleviated and the element current can be reduced. It is effective for improving reliability.

(Embodiment 9) FIG. 22 shows a block diagram of a semiconductor memory device in Embodiment 9 of the present invention. FIG. 22
2 having the same functions as those in FIG. 2 are denoted by the same reference numerals and the description thereof will be omitted. Reference numeral 148 denotes an internal address generating circuit. Inside the circuit, an internal address generating means 148a for generating an address based on an external input address 307 and an internally generated address 308 which is an output of the external input address 307 and the internal address generating means 148a. And a selector 148b for selecting and. The predecode circuit 149 predecodes the internal address 309 which is the output of the selector, and outputs the predecode signal 31.
0 is generated and input to the row decoder 124.

FIG. 23 shows a timing chart of the same data write operation to all memory cells in the semiconductor memory device of the present embodiment configured as described above. The operation will be described below. First, write data in advance to WL
(1) Data is written in the memory cell 120 on 201 and a predetermined mode is set. Next, / RAS 101 is activated and the address 108 designated externally is fetched, and the external input address 307 is used as the internal address generation circuit 14
Enter in 8. In the internal address generating circuit 148, the internal address generating means 148 receives the control signal A311.
The operation of a is stopped, and the selector 14 is activated by the control signal B312.
In 8b, the external input address 307 is sent to the predecode circuit 149 as the internal address 309, and the predecode signal 310 is activated. After the WL (1) 201 is activated by the predecode signal 310, SE230
Is activated to read data from the BLP (1) 211 to BLP (m) 214 to the sense amplifier 127 (data reading). After a fixed time, the internal address generating circuit 148 outputs the control signal A311 to the internal address generating means 14
After the operation of 8a is started, the internal address generating means 14 is operated in the selector 148b by the control signal B312.
The internally generated address 308, which is the output of 8a, is switched as the internal address 309 to the predecode circuit 149. After that, the internal address generating means 148
In a, addresses are sequentially generated based on the external input address 307 and input to the predecode circuit 149 to change the selection state of the predecode signal 310, and WL (2) 2
02-WL (4) 204 -... are sequentially activated, and the data previously stored in the sense amplifier is used to write the data to the memory cells 120 on each word line (collective writing). Finally, the predetermined mode is released, and SE230 is reset at the rising edge of / RAS101.

As described above, according to this embodiment, a plurality of word lines are simultaneously activated at the time of batch writing after the data is read under a predetermined mode setting, so that the memory cell array When the same data is written to all memory cells of the above, it is completed in one / RAS cycle. Therefore, compared with the conventional flash write function, the total write time is about 1 / (total word). Number). Further, it is possible to write a certain data pattern to the memory cell array, and the write operation time is about 1 / l of the write time by random access.
(Number of bits written simultaneously × total number of words / number of words required for one set of data patterns).

(Embodiment 10) FIG. 24 shows a first embodiment of the present invention.
2 is a block diagram of the semiconductor memory device in FIG. In FIG. 24, those having the same functions as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. Reference numeral 316 is an address buffer control signal, which is an address 1 when / CAS and / RAS are activated in a predetermined mode setting (batch write function setting).
This is a signal for controlling the buffer so as to capture 08.

FIG. 25 shows a timing chart of the same data write operation between word lines in the semiconductor memory device of the present embodiment configured as described above. The operation will be described below. First, write data in advance to WL (1) 2
01 is written in the memory cell 120 and / CAS, / O
Activate E and set the specified mode (batch write function setting). At this time, the row address 1 is designated by the address 108, the row address 1 is fetched by the address buffer control signal 316, and is input to the predecode circuit 149 as the internal address 309. After the WL (1) 201 is activated by the row address 1, the SE 230 is activated and the data is read to the sense amplifier 127 via the BLP (1) 211 to BLP (m) 214 (data read). ). After a certain period of time, / RAS is activated, the row address 2 is designated by the address 108 at that time, the row address 2 is fetched by the address buffer control signal 316, and the row address 2 is input to the predecode circuit 149 as the internal address 309. The WL (2) 202 is activated by the row address 2, and the data previously stored in the sense amplifier is used to write the data to the memory cell 120 on the WL (2) 202 (collective writing). Finally, the predetermined mode is released, and SE230 is reset at the rising edge of / RAS101.

As described above, according to this embodiment, / CAS, / O
By activating E before / RAS, the specified mode setting (batch write function setting) is performed, and by specifying the address when activating / CAS and / RAS, one / RAS operation is performed. In a cycle, the data on the word lines can be collectively written on different word lines, and the write operation time can be about 1 / (the number of bits simultaneously written) of the random access write time.

(Embodiment 11) FIG. 26 shows an embodiment 1 of the present invention.
1 is a block diagram of the semiconductor memory device in FIG. 26, those having the same functions as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted. 152 is the memory core unit 1
It is a boosted power supply generation circuit that generates and applies a voltage (hereinafter, VPP) 221 boosted to a voltage higher than VDD to 18. The booster power supply generation circuit 152 is composed of two systems, a booster power supply generation circuit A 150 and a booster power supply generation circuit B 151, and is controlled by an internal RAS 306 and a booster power supply generation circuit control signal 313 generated by the timing generation circuit 121. .

In the semiconductor memory device of the present embodiment configured as described above, the boosting power supply power supply capability of the boosting power supply generation circuit 152 is set to the capability required for the normal operation of the boosting power supply generation circuit A150. The step-up power supply generation circuit B151 is set to have a capability required for word line multiplex selection operation in a predetermined mode setting (collective write function setting), and the boost power supply generation circuit B151 is set in the predetermined mode setting (collective write function setting). By the control signal 313, the operation circuit is switched from the boosted power supply generation circuit A150 to the boosted power supply generation circuit B151 to improve the capability.

The boosting power supply generating circuit 152 is set to have a boosting power supply capability required for normal operation of the boosting power generation circuit A150, and a predetermined mode setting (collective operation) is set for the boosting power generation circuit B150. It is set to the difference between the ability required in the word line multiplex selection operation in the write function setting) and the ability required in the normal operation, and is set by the boost power supply generation circuit control signal 313 in the predetermined mode setting (collective write function setting). The capacity may be improved by operating the boosting power supply generation circuit A150 and the boosting power supply generation circuit B150 at the same time.

As described above, according to the present embodiment, by providing two systems of boosting power supply generation circuits having different capacities, the level of the VPP 221 is lowered during the word line multiplex selection operation in the predetermined mode setting (collective write function setting). Can be prevented.

(Embodiment 12) FIG. 27 shows an embodiment 1 of the present invention.
2 is a block diagram of the semiconductor memory device in FIG. 27, those having the same functions as those in FIG. 26 are designated by the same reference numerals, and the description thereof will be omitted. Boost power supply generation circuit 152
Is a charge pump 155 and a VPP level detection circuit 156.
And a two-system ring oscillator (ring oscillator A1
53 and a ring oscillator B154).
Here, the ring oscillator A 153 and the ring oscillator B 154 are the internal RAS 306 generated by the timing generation circuit 121, the boosting power supply generation circuit control signal 3
13 and the VPP level detection signal 315 generated by the VPP level detection circuit 156. The VPP level detection signal 315 monitors the level of the VPP 221 in the VPP level detection circuit 156, activates when the level of the VPP 221 becomes lower than the set VPP level, and activates when the level of the VPP 221 is set. This signal is inactivated when it rises above the level.

In the semiconductor memory device of this embodiment configured as described above, the oscillation frequency of the ring oscillator in the boosted power supply generation circuit 152 is set to the ring oscillator.
A153 is set to the oscillation frequency that generates the boosted power supply capability required during normal operation, and the ring oscillator B154 is supplied with the boosted power required during word line multiplex selection operation during the specified mode setting (collective write function setting). By setting the oscillation frequency for generating the capacity, and switching the ring oscillator to be operated from the ring oscillator A153 to the ring oscillator B154 by the step-up power supply generation circuit control signal 313 at the predetermined mode setting (collective write function setting), Improves boost power supply capability.

As described above, according to this embodiment, by providing two systems of ring oscillators having different oscillation frequencies, the level of the VPP 221 is lowered during the word line multiplex selection operation in the predetermined mode setting (collective write function setting). Can be prevented.

(Embodiment 13) FIG. 28 shows a first embodiment of the present invention.
3 is a block diagram of the semiconductor memory device in FIG. 28, those having the same functions as those in FIG. 26 are designated by the same reference numerals, and the description thereof will be omitted. Boost power supply generation circuit 152
Is the Internal generated by the timing generation circuit 121.
A circuit controlled by the RAS 306 and the address degeneration signal 305, which is composed of a charge pump and a control circuit.
The address degeneration signal 305 is a signal that is input to the row decoder 124 and degenerates an address for performing word line multiplex selection in a predetermined mode setting (collective write function setting). Become active.

In the semiconductor memory device of the present embodiment configured as described above, the state transition detection signals of the Internal RAS 306 and the address degeneration signal 305 are generated in the boosting power supply generation circuit 152, and the state transition detection signal is used. By controlling the charge pump, the Intern
It is possible to improve the boosting power supply capability of the boosting power supply generation circuit 152 as compared with the case where the configuration is controlled only by the state transition signal of the RAS 306.

Further, two systems of ring oscillators having different oscillation frequencies are provided in the control circuit in the step-up power supply generation circuit 152,
Even if the configuration is such that the operation is switched from the ring oscillator having a low oscillation frequency to the ring oscillator having a high oscillation frequency in the predetermined mode setting (batch write function setting) by the address degeneration signal 305, The supply capacity can be improved.

As described above, according to this embodiment, the address degeneration signal for the multiple selection operation of the word lines is used for controlling the boosting power supply generation circuit, so that the predetermined mode setting (batch write function setting) is performed. It is possible to prevent the level of the VPP 221 from being lowered during the word line multiplex selection operation.

Although the above-mentioned first to thirteenth embodiments have been described for the case of the dual port memory, the general-purpose DRAM and SR
It may be AM.

[0068]

As described above, according to the present invention, under a predetermined mode setting, a sense amplifier control signal for constantly activating the sense amplifier row is activated during a plurality of / RAS cycles until the mode setting is released. Either by providing or by providing a means for activating a plurality of word lines within one / RAS cycle under a predetermined mode setting, the write time of the same data can be shortened and a certain fixed time can be achieved. The data pattern can also be written, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a general dual port memory.

FIG. 2 is a block configuration diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 3 is a timing chart diagram of the same data write operation to all memory cells in the semiconductor memory device in the embodiment.

FIG. 4 is a block diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a timing chart diagram of the same data write operation to all memory cells in the semiconductor memory device in the embodiment.

FIG. 6 is a block configuration diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 7 is a configuration diagram of a shared switch in the semiconductor memory device according to the same embodiment.

FIG. 8 is a timing chart of the same data write operation to all memory cells in the semiconductor memory device according to the same embodiment.

FIG. 9 is a timing chart diagram of the same data write operation to all memory cells in the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 10 is a block configuration diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 11 is a configuration diagram of a write power supply selection switch in the semiconductor memory device according to the same embodiment.

FIG. 12 is a timing chart of a high / low batch write operation to all memory cells in the semiconductor memory device according to the embodiment.

FIG. 13 is a block configuration diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 14 is a configuration diagram of a write power supply selection switch in the semiconductor memory device according to the same embodiment.

FIG. 15 is a timing chart diagram of a high / low batch write operation to all memory cells in the semiconductor memory device in the example.

FIG. 16 is a block configuration diagram of a semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 17 is a configuration diagram of a predecode circuit and a row decoder when an address is 6 bits in the semiconductor memory device according to the same embodiment.

FIG. 18 is a timing chart diagram of the same data write operation to all memory cells in the semiconductor memory device in the embodiment.

FIG. 19 is a block configuration diagram of a semiconductor memory device according to an eighth embodiment of the present invention.

FIG. 20 is a configuration diagram of a predecode circuit and a row decoder when an address is 6 bits in the semiconductor memory device in the embodiment.

FIG. 21 is a timing chart of the same data write operation to all memory cells in the semiconductor memory device in the example.

FIG. 22 is a block configuration diagram of a semiconductor memory device according to a ninth embodiment of the present invention.

FIG. 23 is a timing chart diagram of the same data write operation to all memory cells in the semiconductor memory device in the example.

FIG. 24 is a block configuration diagram of a semiconductor memory device according to a tenth embodiment of the present invention.

FIG. 25 is a timing chart of the same data write operation to all memory cells in the semiconductor memory device in the example.

FIG. 26 is a block configuration diagram of a semiconductor memory device according to an eleventh embodiment of the present invention.

FIG. 27 is a block configuration diagram of a semiconductor memory device according to a twelfth embodiment of the present invention.

FIG. 28 is a block configuration diagram of a semiconductor memory device according to a thirteenth embodiment of the present invention.

[Figure 29] Block diagram of 1Mbit dual-port DRAM with flash write function

FIG. 30 is an operation timing chart of the flashlight function.

[Explanation of symbols]

 119 memory cell array 121 timing generation circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akihiro Sawada 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Masashi Agata, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. 72) Inventor Shunichi Iwanari 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (17)

[Claims] 1. A semiconductor memory device comprising: a memory cell array having a plurality of word lines and a plurality of bit lines; a row decoder for selecting the word lines; and a sense amplifier connected to the bit lines. Under the specified mode setting, within one / RAS cycle, / R
By activating a word line by an address designated at the time of AS input, reading the data of the memory cell on the word line to the sense amplifier column, and activating a different word line or a plurality of word lines after a certain period of time, A semiconductor memory device, wherein the data is written to the memory cells on the one or more word lines. 2. A semiconductor memory device comprising a memory cell array having a plurality of word lines and a plurality of bit lines, a row decoder for selecting the word lines, and a plurality of sense amplifiers connected to the bit lines. , Under the specified mode setting, within one / RAS cycle, / R
A word line in a memory cell array selected by an address designated at the time of AS input and a sense amplifier row connected to the selected memory cell array are activated, and at the same time, one or more word lines in a non-selected memory cell array. To read the data of the memory cell on the word line in the selected memory cell array to the sense amplifier row, transfer the data to the sense amplifier row connected to the non-selected memory cell array, and after a certain time, A semiconductor memory device characterized in that the data is written into the memory cells on the one or more word lines by activating a sense amplifier column connected to the non-selected memory cell array. 3. A memory cell array having a plurality of word lines and a plurality of bit lines and row decoders for selecting the word lines are arranged on the left and right of a sense amplifier column, and the sense amplifier column is connected via a shared switch. In the semiconductor memory device connected to the bit lines of the left and right memory cell arrays, / R is set in one / RAS cycle under a predetermined mode setting.
A word line in the memory cell array selected by the address designated at the time of AS input is activated, and also one or more word lines are activated in the non-selected memory cell array. At the same time, the non-selected memory cell array and the sense amplifier row are also activated. After deactivating the shared switch control line that connects the memory cell array and the memory cell on the word line in the selected memory cell array, the data is read out to the sense amplifier column, and after a certain period of time, the non-selected memory cell array and the sense amplifier column are switched to each other. A semiconductor memory device, characterized in that the data is written in a memory cell on the one or a plurality of word lines by activating a shared switch control line to be connected. 4. A memory cell array having a plurality of word lines and a plurality of bit lines and row decoders for selecting the word lines are arranged on the left and right of a sense amplifier column, and the sense amplifier column is connected via a shared switch. In the semiconductor memory device connected to the bit lines of the left and right memory cell arrays, / R is set in one / RAS cycle under a predetermined mode setting.
A word line in the memory cell array selected by an address designated at the time of AS input is activated, and a shared switch control line connecting the selected memory cell array and the sense amplifier row and a non-selected memory cell array and the sense amplifier row are connected. The shared switch control line is continuously activated to read the data of the memory cell on the word line in the selected memory cell array to the sense amplifier column, and after a certain time, in the non-selected memory cell array, one or more word lines Is activated to write the data to the memory cells on the one or more word lines. 5. A semiconductor memory device comprising a memory cell array having a plurality of word lines and a plurality of bit lines, wherein the bit lines, power supply lines (hereinafter VDD lines) and ground lines (hereinafter VSS lines) A switch to connect to the bit line is connected to the VDD line or the VSS line after inputting / RAS within a single / RAS cycle under the specified mode setting. A semiconductor memory device, wherein high-level or low-level data is collectively written to the memory cells on the one or more word lines by activating the word lines. 6. The VD for high level writing according to claim 5.
A semiconductor memory device characterized by using a power supply voltage higher than D. 7. The method according to any one of claims 1 to 6,
Under the specified mode setting, after predecoding the address specified at the / RAS input, generate a signal to degenerate the address to / RAS at a certain timing, and predecode the address degenerating the address degeneration signal. A semiconductor memory device, comprising: inputting to a decoding circuit, setting all output signals of the predecoding circuit to a selected state, and activating a word line, a shared switch control signal, a sense amplifier activation signal and the like in a multiple manner. 8. The method according to any one of claims 1 to 6,
Under the specified mode setting, after pre-decoding the address specified at the / RAS input, generate multiple systems of signals that have a certain timing with respect to / RAS and degenerate an address with a delay difference, The address degeneration signal is input to a predecode circuit for degenerating the address, the output signals of the predecode circuit are sequentially activated, and finally all selected states are set, and word lines, shared switch control signals,
A semiconductor memory device having multiple activations of sense amplifier activation signals and the like. 9. A semiconductor memory device comprising: a memory cell array having a plurality of word lines and a plurality of bit lines; a row decoder for selecting the word lines; and a sense amplifier column connected to the bit lines. By providing an internal address generation circuit and selecting the word line by the address specified at the / RAS input within one / RAS cycle under the specified mode setting, the data of the memory cell on the word line is selected. After reading out to the sense amplifier column, after a certain time, using different addresses sequentially generated by the internal address generation circuit based on the address,
A semiconductor memory device characterized in that the data is written into memory cells on one or a plurality of word lines by sequentially activating the word lines. 10. A semiconductor memory device comprising: a memory cell array having a plurality of word lines and a plurality of bit lines; a row decoder for selecting the word lines; and a sense amplifier connected to the bit lines. Under the specified mode setting, select a word line at the address specified when / RAS is input, and multiplex different word lines by using the address specified when the column address strobe signal (hereinafter, / CAS) is input. A semiconductor memory device which is activated to transfer data between word lines. 11. The boosting power supply generation circuit for generating a power supply voltage higher than VDD according to claim 1, wherein the boosting power supply generation circuit is for normal operation and word line multiple selection operation. The boosting power source generating circuit for the word line multiple selection operation is set to be larger than the boosting power source supplying capacity of the boosting power source generating circuit for normal operation, and a predetermined mode setting is performed. Then, the semiconductor memory device is characterized in that the boosting power supply generating circuit for normal operation is switched to the boosting power supply generating circuit for word line multiple selection operation. 12. The boosting power supply generation circuit for generating a power supply voltage higher than VDD according to claim 1, wherein the boosting power supply generation circuit is for normal operation and for word line multiple selection operation. The boosting power supply capability of the boosting power supply generation circuit for the word line multiplex selection operation is set to a predetermined difference between the ability required for the word line multiplex selection and the ability required for the normal operation. According to the mode setting, the semiconductor memory device is characterized in that the step-up power supply generation circuit for normal operation and the step-up power supply generation circuit for word line multiplex selection operation are simultaneously operated. 13. The ring oscillator according to claim 1, further comprising a step-up power supply generation circuit for generating a power supply voltage higher than VDD, wherein a ring oscillator for controlling a charge pump in the step-up power supply generation circuit is in normal operation. And the word line multiplex selection operation, and the oscillation frequency of the word line multiplex selection operation ring oscillator is set higher than the oscillation frequency of the normal operation ring oscillator to set a predetermined mode. Under the circumstances, the semiconductor memory device is characterized in that the ring oscillator for normal operation is switched to the ring oscillator for word line multiple selection operation. 14. A boosting power supply generation circuit for generating a power supply voltage higher than VDD according to claim 11, 12, or 13, and degenerates an address at a certain timing with respect to / RAS under a predetermined mode setting. A semiconductor memory device characterized by generating a signal and controlling a charge pump in the boosted power supply generation circuit by / RAS and the address degeneration signal. 15. The semiconductor memory device according to claim 1, further comprising a pin for applying a power supply voltage higher than VDD. 16. The timing for activating / RAS after activating an output enable signal (hereinafter, / OE) and / CAS at the timing of mode setting according to any one of claims 1 to 15. A semiconductor memory device characterized by being used. 17. A semiconductor memory device according to claim 1, wherein a mode setting pin is provided and a mode setting signal is input from the pin.