JPH0628870A - Association memory device - Google Patents

Abstract

PURPOSE:To obtain a device with a high function and with a small circuit area by constituting a logicical operation circuit for AND retrieval and LINK retrieval with three Nch MOSFETs. CONSTITUTION:An association memory device is connected between a memory cell column and a match flag 5, and the gate and the drain of a first FET are conncted to a match line ML, and the gate of a second FET is connected to the inverse output line of the match flag 5 and the source of the second FET is connected to an AND enable signal line AME. The second FET is turned on when the latch data of the match flag is uncoincident at an AND retrieving time, and the match line ML is discharged. At a third FET, drain is connected to the source of the first FET, and gate is connected to the inverse output line of the match flag 5 of an adjacent memory cell column, and source is connected to a LINK enable signal line LME, and the third FET is turned on when the latch data of the match flag in adjacent memory cell column unit is uncoincident at a LINK retrieving time, and the match line ML is discharged. By such a constitution, the association memory device with a small area and with a high function is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a content address memory (Conten) for detecting an address using stored content as search data.
t Addressable Memory: CAM).

[0002]

2. Description of the Related Art The basic function of a CAM is to use the stored contents as search data, as opposed to an ordinary memory that uses addresses as search data, and to search the address of a memory where data matching this search data is stored. Is output as, and this operation is called a match search. The CAM is generally composed of a plurality of CAM cells arranged in a two-dimensional array in the row and column directions.

FIG. 2 shows "A 288-kbit fully parallel c".
ontent addressable memory using stacked capacitor c
ell structure, ”(Proc. CICC ■ 91, May 1991, pp.1
It is a circuit diagram of the dynamic CAM cell shown in 0-3), and (a) shows the case where the result of the match search using this CAM cell is a match, and (b) shows the case where it does not match.

The CAM cell is orthogonal to the word line WL to which a plurality of CAM cells that store data in word units are commonly connected, the match line ML that outputs the result of the match search, and the word line WL and the match line ML. , A pair of bit line BL and inverted bit line / BL that determine the stored value of the CAM cell, and the cell plate potential
It is connected to Vcp, and it has five Mw0, Mw1, Ms0, Ms1, Md
It consists of an N-channel MOS transistor and two capacitors Cs0 and Cs1.

More specifically, the transistor Mw0 is
The gate is connected to the word line WL, the source is connected to the bit line BL, the drain is connected to the node N0, and the transistor Mw1 has a gate for the word line WL and a source for the inverted bit line / BL (hereinafter,
"/" Indicates an inverted signal), and the drain is connected to the node N1. The gate of the transistor Ms0 is at the node N0,
The source is connected to the bit line BL, the drain is connected to the node N2, the transistor Ms1 has the gate connected to the node N1, the source connected to the inverted bit line / BL, the drain connected to the node N2, and the transistor Md has the source connected to the node N2. In addition, the drain and the gate are connected to the match line ML. The capacitor Cs0 is connected to the node N0 and the cell plate potential Vcp, and the capacitor Cs1 is connected to the node N1 and the cell plate potential Vcp.
Connected to cp.

Next, the operation will be described. Less than,
“1” and “0” represent binary logic levels, and also “H”
Represents a power supply potential or a potential in the vicinity thereof, and "L" represents a ground potential or a potential in the vicinity thereof. FIG. 2A shows a CAM cell holding "1" as storage data ("H" at node N0 and "L" at node N1). After precharging the match line ML to “H”, the bit line pair is set to “1” as search data (“H” to bit line BL, inverted bit line / BL
Is supplied to the match line ML, the match line ML does not have a discharge path and is kept at “H”.

FIG. 2B shows a CAM cell holding “1” (“H” in the node N0 and “L” in the node N1) as the storage data, as described above. If the match line ML is precharged to “H” and then “0” is given to the bit line pair (“L” to the bit line BL and “H” to the inverted bit line / BL) as search data, the match line The charge of ML is discharged to the bit line BL via the transistors Md and Ms0, and the match line ML becomes “L”. As described above, as a result of providing search data, this CAM shows a matching search result (logical level is “1”) if the match line ML is “H”, and a mismatching search result (logical level if it is “L”). The level represents “0”).

FIG. 3 is a block diagram showing the structure of a CAM in which the CAM cells as described above are arranged in a two-dimensional array. Common match line MLn (n = 0,1,2, ...) and common word line WL
A CAM word 2 consisting of a column of CAM cells connected to n is arranged in the row direction. The match line MLn of each CAM word 2 is connected to the corresponding sense amplifier (S / A) 3, and the sense amplifier 3 is connected to the match flag 5 via the logical operation circuit 4.

Next, the operation will be described. As described above, when the search data is given to the bit line pair (BLn, / BLn), the potential indicating the matching / mismatching search result is output to the match line MLn for each CAM word 2, and each potential corresponds to the corresponding sense. It is amplified by the amplifier (S / A) 3 and a logical level indicating a search result is output for each word. This search result is transferred to the logical operation circuit 4 in all words in parallel, the logical operation circuit 4 performs a simple logical operation in all words in parallel, and the results of this logical operation are transferred to the match flag corresponding to each word in all words in parallel. To be done.

AND search, OR search, LINK search, and the like have been reported as match search operations involving such logical operations.
T. Ogura et. Al “A 20-kbit associative memory LSI
forartificial intelligence machines, ”IEEE J. Sol
id-States Circuit, vol. 24, pp.1014-1020, Aug. 198
9).

The AND search and LINK search will be described below. FIG. 4 is a circuit diagram showing a configuration around a conventional logical operation circuit 40 having logical operation functions of AND search and LINK search. The match line ML is connected to the match flag 5 via the MOS transistors 6 and 7 which are turned on by the activation of the control signals TG1 and TG2, respectively, and the sense amplifier 3 is connected between the MOS transistors 6 and 7. The logical operation circuit 40 includes a NAND gate 8 which receives the match flag MF and the potential of the intermediate node N3 between the MOS transistors 6 and 7, an inverter 9 connected to the output terminal of the NAND gate 8, and a source connected to the output of the inverter 9. , AND, the drain of which is connected to the match flag MF, and the AND search enable signal AME is used as a gate input for the AND search section, and the NAND gate 11 and the NAND which receives the potential of the node N3 and the match flag MF of the adjacent word as inputs.
It consists of an inverter 12 connected to the output terminal of the gate 11, a source connected to the output of the inverter 12, a drain connected to the match flag MF, and a LINK search unit consisting of a MOS transistor 13 whose gate input is the LINK search enable signal LME. ,
The logical operation circuit 40 is provided for each CAM word 2.

First, a normal search operation will be described.
The potential output to the match line ML as a search result activates the control signal TG1 of the transistor 6 to activate the node N.
It is transmitted to 3 and amplified by the sense amplifier 3. Further, by activating the control signal TG2 of the transistor 7, the potential of the node N3 is transferred to the node MF of the match flag 5 (hereinafter, match flag MF) and latched in the match flag MF as a search result.

Next, the AND search operation will be described. The potential output to the match line ML as a search result activates the control signal TG1 of the transistor 6 to activate the node N3.
And is amplified by the sense amplifier 3. The potential of the node N3 and the potential of the match flag MF are ANDed by the NAND gate 8 and the inverter 9, and the result is output to the node N4. Further, the potential of the node N4 is input to the gate of the transistor 10 AND search enable signal
It is transferred to the match flag MF by activating AME and is latched as a search result.

Next, the LINK search operation will be described. The potential output to the match line ML as a search result activates the control signal TG1 of the transistor 6 to activate the node N3.
And is amplified by the sense amplifier 3. The potential of the node N3 and the potential of the match flag MF (P) of the adjacent word are ANDed by the NAND gate 11 and the inverter 12, and the result is output to the node N5. More nodes
The potential of N5 is transferred to the match flag MF by activating the LINK search enable signal LME input to the gate of the transistor 13 and latched as the search result.

As described above, in the normal search, the match line is
The search data of ML is latched as it is in the match flag MF as the search result, and in AND search, the search data of the match line ML is ANDed with the latch data of the match flag MF and then latched again in the match flag MF as a new search result. , LI
In the NK search, the search data of the match line ML is ANDed with the latch data of the match flag MF (P) of the adjacent word, and then latched in the match flag MF as the search result.

When the AND search function as described above is used, the AND operation of the search results of a plurality of times can be executed in all words in parallel,
For example, a complicated relational search can be realized by combining with an OR search. Further, by using the LINK search function, it is possible to search for long data over a plurality of words by sequentially searching for a plurality of adjacent words.

[0017]

By the way, in order to use CAM for the above-mentioned relation retrieval and database retrieval, CAM is used.
It is necessary to increase the capacity of the CAM, but to increase the capacity and increase the integration density of memory cells, the area of each CAM cell is reduced, and the pitch of the CAM word is also reduced as the area of the CAM cell is reduced. There is a need.

The logical operation circuit 40 described above is, for example, a CMOS.
When configured in a circuit, P-channel MOS transistor 6
14 MOS transistors, 8 N-channel MOS transistors in total
A transistor is needed. Therefore, if the logical operation circuit 40 is added to improve the functionality of CAM,
In order to add 14 transistors, it is necessary to lay out many transistors and wirings in a narrow word pitch, so it is difficult to make the layout of the logic operation circuit part compact and improve the cell area efficiency. Furthermore, if the logic operation circuit 40 is composed of a CMOS circuit,
Since it is necessary to provide wells, the circuit area is further increased.

The present invention has been made to solve such a problem, and realizes a high function with a small circuit area by suppressing the layout area of the logical operation circuits of the matching search result comrades to be small. An object is to provide an associative memory device.

[0020]

An associative memory device according to the present invention includes a first transistor connected between a plurality of memory cell columns and a match flag, and having a gate and a drain connected to a match line. The drain is connected to the source of the first transistor, the gate is connected to the inverted signal output line of the match flag, and the source is connected to the AND enable signal line.
At the time of search, when the latch data of the match flag is data indicating a mismatch, the second transistor is turned on to discharge the match line, the drain is the source of the first transistor, and the gate is the match flag of the adjacent memory cell column. The source is connected to the LINK enable signal line to the inversion signal output line, and when the latch data of the match flag of the adjacent memory cell column unit at the time of LINK search is a data indicating a mismatch, it is turned on and the match line is discharged. It is characterized by including a logical operation circuit composed of the transistor.

[0021]

In the associative memory device according to the present invention, when the latch data of the match flag indicates a match during AND search,
Since the second transistor does not turn on, the match line is not discharged, the match / mismatch search result of the memory cell row is latched as is in the match flag, and the AND operation of the match flag latch data and the match search result is performed. The result of is obtained. On the other hand, when the latch data of the match flag indicates a mismatch during the AND search, the second transistor is turned on, so that the match line is discharged via the first and second transistors, and the latch data of the match flag and the match search result are compared. Similarly to the case where the AND operation is performed, the search mismatch data is latched in the match flag.

Further, when the latch data of the match flag in the adjacent memory cell column indicates a match during the LINK search, the third transistor is not turned on, the match line is not discharged, and a match / mismatch search of the memory cell column is performed. The result is latched in the match flag as it is, and a similar result is obtained in which the latch data of the match flag in the adjacent memory cell column and the match search result are ANDed. On the other hand, if the latch data of the match flag in the adjacent memory cell columns indicates non-coincidence during the LINK search, the third
Since the transistor is turned on, the match line is discharged via the first and third transistors, so that the latch data of the match flag in the adjacent memory cell column and the match search result
Similarly to the case where the AND operation is performed, the search mismatch data is latched in the match flag.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments. FIG. 1 is a circuit diagram showing an embodiment of a CAM according to the present invention. One unit of a CAM word in which a plurality of CAM cells 1 are connected to a common word line WL and a match line ML (for simplicity, 1 Only one CAM cell 1 is shown). Match line ML of 1 unit CAM word is AND search / LI
A match flag is passed through a logical operation circuit 41 for performing NK search, a MOS transistor 6 having a control signal TG1 as a gate input, and a MOS transistor 7 having a control signal TG2 as a gate input.
The sense amplifier 3 is connected to the node N3 between the transistors 6 and 7, which is connected to the transistor 5.

The logical operation circuit 41 includes three N channel MOSs.
The MOS transistor 14 which is the first transistor has a gate and a drain connected to the match line ML, and the MOS transistor 15 which is the second transistor has a drain which is the MOS transistor. Inverted gate to the source of transistor 14 Match flag / MF
The source of the third transistor is connected to the inverted AND search enable signal / AME (the inverted signal of the AND search enable signal AME).
The drain of the MOS transistor 16 is the MOS transistor
Inverted match flag with gate adjacent to 14 sources
/ MF (P) (Inverted signal of match flag MF (P) of adjacent word)
In addition, the source is connected to the inverted LINK search enable signal / LME (the inverted signal of the LINK search enable signal LME).

The CAM cell 1 is similar to the CAM cell of FIG. 2 and is composed of five MOS transistors and two capacitors, and in particular, its match comparison part and the output part to the match line ML. Is a MOS transistor 24,25,26 (MSd, MS
1, corresponding to MS0).

Next, the operation will be described. In the case of a normal match search operation, first, the match line ML is charged to "H". Then, for CAM cell 1, bit line BL and inverted bit line /
Data is given to BL, and the match comparison result is output to the match line ML via the MOS transistor 24 according to the gate potentials of the MOS transistors 25 and 26. At this time, the logical operation circuit
Since both the inverted AND search enable signal / AME and the inverted LINK search enable signal / LME of 41 maintain the potential level of "H", the logical operation circuit 41 does not operate and the match line ML normally receives the potential level of the search result. Is output. This potential level is latched at the node N3 by activating and then deactivating the control signal TG1, amplified by the sense amplifier 3, and further activated and deactivated by the control signal TG2 to obtain the match flag. It is transferred to the MF and the normal match search result is latched in the match flag MF.

Next, the AND search operation will be described. First, the match line ML is set to "H" as in the normal match search operation.
To charge. Then, data is applied to the bit line BL and the inverted bit line / BL for the CAM cell 1, and the match comparison result is output to the match line ML via the MOS transistor 24 according to the gate potentials of the MOS transistors 25 and 26. It at the same time,
The inverted AND search enable signal / AME of the logical operation circuit 41 is activated and becomes "L". At this time, the match flag is "1"
If the match flag MF is "H" and the inverted match flag / MF is "L", the MOS transistor 15 is off and the logic operation circuit 41 does not discharge the match line ML. Therefore, the logic operation circuit 41 does not operate, the potential level of the normal search result is output to the match line ML, and as a result, the AND operation result with the latch data of the match flag MF is the match flag MF.
Latched on.

On the other hand, if the match flag is "0" (the match flag MF is "L" and the inverted match flag / MF is "H")
Since the MOS transistor 15 is turned on, the match line ML is discharged by the logical operation circuit 41, and as a result, the potential level of the AND operation result of the normal search data and the latch data of the match flag MF is output to the match line ML. This potential level is
When the control signal TG1 is activated and then deactivated, it is taken into the node N3, amplified by the sense amplifier 3, and when the control signal TG2 is activated and then deactivated, new data is added to the match flag MF. Transferred as
The result of the AND search operation is latched in the match flag MF.

Next, the LINK search operation will be described. First, the match line ML is set to "H" as in the normal match search operation.
To charge. Then, data is applied to the bit line BL and the inverted bit line / BL for the CAM cell 1, and the match comparison result is output to the match line ML via the MOS transistor 24 according to the gate potentials of the MOS transistors 25 and 26. It at the same time,
The inverted LINK search enable signal / LME of the logical operation circuit 41 is activated and becomes "L". At this time, the match flag of the adjacent word is "1" (the match flag MF of the adjacent word is "H",
If the inverted match flag / MF (P) from the adjacent word is "L", the MOS transistor 16 is off and the logic operation circuit 41 does not discharge the match line ML. Therefore, the logical operation circuit 41 does not operate, the potential level of the normal search data is output to the match line ML, and as a result, the AND operation result with the latch data of the match flag MF of the adjacent word, that is, the LINK search result is concerned. Latched in the match flag MF of the word.

On the other hand, the match flag of the adjacent word is "0".
If the match flag MF of the adjacent word is "L" and the inverted match flag / MF (P) from the adjacent word is "H", the MOS transistor 16 is turned on, and the match line ML is discharged by the logical operation circuit 41. As a result, in the match line ML, the normal search result data of the word and the match flag MF of the adjacent word
The potential level of the AND operation result of the latch data of (P) is output. This potential level is taken into the node N3 by activating and then deactivating the control signal TG1, amplified by the sense amplifier 3, and further activating the control signal TG2 and then deactivating it to obtain the match flag MF. Are transferred to the match flag MF as new data.

[0031]

As described above, the associative memory device according to the present invention has three logical operation circuits for AND search and LINK search.
Since it is composed of N-channel MOS transistors, it has an excellent effect that high functionality is realized with a small number of transistors, that is, a small circuit area, and the degree of integration can be improved with the increase in capacity.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a CAM according to the present invention.

FIG. 2 is a circuit diagram illustrating a search operation by a CAM cell.

FIG. 3 is a block diagram showing a configuration of a conventional CAM.

FIG. 4 is a circuit diagram of a logical operation circuit of a conventional CAM.

[Explanation of symbols]

 1 CAM cell 5 Match flag 14,15,16 MOS transistor 41 Logical operation circuit WL Word line ML Match line AME AND Search enable signal LME LINK Search enable signal MF Match flag MF (P) Match flag of adjacent word

Front Page Continuation (72) Inventor Takeshi Hamamoto 4-1-1 Mizuhara, Itami City, Hyogo Prefecture LS Electric Co., Ltd. LSE Research Institute (72) Inventor Yoshito Yamagata 4-1-1 Mizuhara, Itami City, Hyogo Mitsubishi Electric LSI Co., Ltd. (72) Inventor Masaaki Mihara 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Co., Ltd. LSI Research Institute (72) Hideyuki Ozaki 4-c, Mizuhara, Itami-shi, Hyogo No. 1 Mitsubishi Electric Corporation LSI Research Center

Claims (1)

[Claims] 1. A plurality of memory cell rows for storing word-by-word data consisting of a plurality of bits, a common word line for driving the plurality of memory cell rows, and search data provided in units of the plurality of memory cell rows. Is connected to a match line that outputs a search result of a match or a mismatch with a match flag circuit, and the plurality of memory cell columns are arranged in an array,
In an associative memory device having a logical operation circuit capable of AND search or LINK search in units of memory cell columns, the logical operation circuit is connected between a memory cell column and a match flag of the memory cell column, and a gate and A first transistor having a drain connected to the match line, a drain having a source connected to the first transistor, a gate having a match flag inverted signal output line, and a source connected to an AND search enable signal line; and a drain Is the source of the first transistor, the gate is the inverted signal output line of the match flag of the adjacent memory cell column, and the source is LIN.
An associative memory device comprising a third transistor connected to a K search enable signal line.