JPH06284486A - Atm cell exchange switch - Google Patents

Abstract

PURPOSE:To reduce the number of cells to be abandoned by duplication of destinations by providing switching network circuits, which subjecting cells outputted from input cell buffers to routing processing to send them to destinations, to perform processing of the cells having the same destination by different circuits. CONSTITUTION:Input cell buffers 10 to 13 where cells inputted from incoming lines are temporarily stored and output cell buffers 15 to 18 which control transmission of cells to outgoing lines are provided. Switching network circuits 23 and 24 which send sells, which are outputted from buffers 10 to 13, to buffers 15 to 18 for destinations of cells by prescribed routing processing and cell selectors S0 and S3 which select the circuits 23 and 24 are provided. A cell contention circuit 25 selects the cell to be out putted to the circuit 23 or 24 from cells in buffers 10 to 13 so that cells contending for a destination are not outputted to the same circuit 23 or 24. Outputs of circuits 23 and 24 are multiplexed and outputted with respect to each destination, Thus, the line use ratio of incoming lines is improved to reduce the number of cells to be abandoned.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM cell switching switch for sending cells input from a plurality of incoming lines in an ATM switch to a predetermined outgoing line targeted by each cell.

[0002]

2. Description of the Related Art In an ATM switch, an ATM cell exchange switch for sending cells input from a plurality of incoming lines to a predetermined outgoing line (destination) targeted by each cell,
Up to now, a plurality of input cell buffers are provided for each incoming line accommodated by the ATM switch and temporarily hold cells input from the corresponding incoming line, and are provided for each outgoing line accommodated by the ATM switch. A plurality of output cell buffers for controlling cell transmission to the corresponding output line, and one output cell buffer for transmitting the cells held in each of the input cell buffers described above to a predetermined output cell buffer for each target output line. A configuration including a cell switch unit has been proposed.

Here, the cell switching section sends a cell output from each input cell buffer to a predetermined output cell buffer for a target output line of each cell, and a plurality of switch network circuits in which the target output line competes. Cell competition circuit that selects cells to be output to the switching network circuit from cells held in the input cell buffer so that the cells are not simultaneously output to the same switching network circuit.

The cell competing circuit in the cell switch section corresponds to the root network in the following document 1.

[Reference 1] SE87-132 "Study on high-speed packet switching switch" A supplementary explanation of the cell competing circuit of the cell switch section used in the above-mentioned conventional method is as follows.

The cell contention circuit is composed of a batcher network with a survival report function and a survival report circuit. In the batcher network with a survival report function, the cell to be output next from each input cell buffer is The header (destined destination (outgoing line number) is described) is synchronously transmitted. In the batcher network with a survival report function that receives headers from each input cell buffer, the received plurality of headers are sorted in order of destinations and passed to the award report circuit. This residual report circuit has header arrival terminals for the number of outgoing lines accommodated in the ATM switch,
Receiving headers sorted in order of destination by each header arrival terminal, and comparing the destinations of the headers between adjacent arrival terminals, and if they are different from each other, the batcher with the survival report function that the header has passed through. The route in the network is traced back and "remaining" is reported to the corresponding input cell buffer. If the destination of the header is the same between adjacent arrival terminals, only one of them will be "winning".
To report.

Each input cell buffer sends one header to the cell contention circuit, and it is set as one cycle until the presence or absence of the "winning" report for the header is determined from the cell contention circuit, and the same processing is repeated an appropriate number of times. Be done.

However, in the next cycle, the input cell buffer which has received the victory report sends the same header as the previous time, but the input cell buffer which has not received the victory report is stored in the buffer. The cell header will be sent to the cell contention circuit. The header that has won once has the mechanism to survive the next cycle and beyond.

By repeating the selection process by the cell competition circuit as many times as necessary, it is possible to avoid the duplication of the destinations of the cells output from the respective input cell buffers to the switching network circuit. Then, more cells having different destinations can be collectively sent to the switching network circuit.

[0010]

By the way, the recent improvement of digital communication technology is remarkable, and the data transmission speed may be further improved in the future due to the spread of the technology such as ATM (asynchronous transfer mode). for that purpose,
There is also a demand for development of an ATM cell exchange switch or the like which efficiently processes a larger number of cells to a predetermined destination in a shorter time.

From the viewpoint as described above, in the above-mentioned conventional ATM cell exchange switch, when the cell discard rate in the cell contention circuit is 10-10 or less, the line utilization rate of the incoming line is 80% at maximum. There is a problem in that the level can be increased only to a certain degree, and the level required in the future (for example, increasing the line utilization rate of the incoming line to 90% or more) cannot be satisfied.

The present invention has been made in view of the above circumstances, and it is possible to improve the line utilization rate of incoming lines and satisfy the demand for high level communication quality in the future.
An object is to provide a TM cell switching switch.

[0013]

SUMMARY OF THE INVENTION An ATM cell exchange switch according to the present invention comprises a plurality of input cell buffers provided for each incoming line accommodated in an ATM switch and temporarily storing cells input from the corresponding incoming line. And a plurality of output cell buffers provided for each outgoing line accommodated in the ATM switch to control cell transmission to the corresponding outgoing line, and a cell output from each input cell buffer by a predetermined routing process. A plurality of switching network circuits for sending to the output cell buffer for the intended destination of each cell,
A cell selector which is provided for each of the above-mentioned input cell buffers and which selects the switching network circuit as a destination of the cells output from the respective input cell buffers, and a plurality of competing cells whose destinations are the same are the same switching network A cell contention circuit for selecting a cell to be output to the switching network circuit from the cells held in the plurality of input cell buffers so as not to be output to the circuit.

Then, the cell competing circuit suppresses the existence of cells having the same destination as the cells to be transmitted next by each of the plurality of input cell buffers within the range of the number of the installed switching network circuits. At the same time, the destination selection in the cell selector is controlled so that cells having the same destination are transmitted to different switching network circuits.

As the output cell buffer provided for each outgoing line, a multi-input one-output type cell buffer circuit that multiplexes and outputs cells of the same destination output from each switching network circuit is used. .

With the above configuration, cell input / output in the ATM switch is controlled.

[0017]

The ATM cell switching switch according to the present invention is equipped with a plurality of switching network circuits for sending the cells output from the input cell buffer to the intended destination of each cell by a predetermined routing process, and to the same destination. Since the preceding cells are processed by different switching network circuits, discarding of cells in the cell competition circuit is limited when cells of the same destination overlap and there are more than the installed number of switching network circuits. It is possible to significantly reduce the number of cell discards due to the overlapping of the destinations.

Therefore, the actual throughput of cells from the input cell buffer to the switching network circuit is improved, and the line utilization rate of the incoming line is considered under the condition that the cell discard rate of the entire ATM cell switching switch is kept at a constant value. When compared with the conventional case where only a single switching network circuit was equipped,
The line utilization rate of incoming lines can be greatly improved, and it will be possible to sufficiently meet future high-level communication quality requirements.

[0019]

1 shows an embodiment of an ATM cell exchange switch according to the present invention. AT of this embodiment
The M cell exchange switch is used when the number of inputs N is 4
The four incoming lines ip0 to ip3 accommodated by the exchange and the four input cell buffers 10 and 1 provided for each incoming line and temporarily storing cells input from the corresponding incoming line
1, 12 and 13 and four outgoing lines op0 accommodated in the ATM exchange corresponding to the four incoming lines ip0 to ip3
To op3, four output cell buffers 15, 16, 17, 18 provided for each of these output lines and controlling cell transmission to the corresponding output lines, and the above-mentioned input cell buffers 10, 11, The output cell buffers 15 for the destinations (outgoing lines) of the cells stored in the cells 12 and 13 are subjected to a predetermined routing process,
Two switching network circuits 23, 2 for sending to 16, 17, 18
4 and cell selectors S0 to S3 which are provided for each of the input cell buffers and which select the switching network circuits 23 and 24 to which the cells output from the input cell buffers are sent.
The switching network circuit 23, among the cells held in the four input cell buffers 10, 11, 12, and 13 described above, is provided so that a plurality of competing cells of the intended destination are not simultaneously output to the same switching network circuit. 24 and a cell competition circuit 25 for selecting a cell to be output to 24.

In this embodiment, since the number of inputs N is 4, the switching network circuits 23 and 24 have four cell input ports SRD0 to SRD3 and four cell output ports SSD0 to SSD3. The cells input to any cell input port can be sent to the cell output port according to the destination by the multi-staged route selection switches.

The cell competing circuit 25 corresponds to the routing network described in the conventional example, in which the header of the cell to be output next from the input cell buffer (destined destination (outgoing line number) is described. 4 header input terminals NRD0 to NRD3 and the contents (addresses) of the headers received by each of these header input terminals NRD0 to NRD3. A cell selection circuit (not shown) with a survival report function for selecting a cell to be output is configured.

Then, the cell selection circuit with a survival report function of the cell competition circuit 25 avoids that cells of the same destination are sent to the same switching network circuit at the same time (during one cell cycle period). As described above, the cell contention control processing is executed, but the processing method is different from the conventional method.

In this embodiment, in the cell selection circuit with the survival report function of the cell contention circuit 25, the above-mentioned four input cell buffers 10, 11, 12, 13 are the cells to be transmitted next, and the intended destinations. The number of cells having the same number is determined by the number of installed switching network circuits (ie, two in one embodiment)
In addition, the destination selection in each of the cell selectors S0 to S3 described above is controlled so that cells having the same destination are transmitted to different switching network circuits.

FIG. 2 shows the headers of cells stored in the input cell buffers 10, 11, 12, and 13 during one cell period (competition cell data = data describing the destination).
6 are shown in the order of input. As each of the input cell buffers 10, 11, 12, and 13, a memory having a capacity capable of accumulating data of several tens of cells is used.

In FIG. 2, a square frame is one cell,
The number written in it is the intended destination (outgoing line number). The destination enclosed in parentheses () is a cell whose winning or losing is determined by the competition process (that is, a cell which the input cell buffer should next output to the switching network circuit). The subscripted numbers 23 and 24 attached to the destinations in parentheses indicate the switching network circuits 23 and 24 selected by the cell selectors S0 to S3.

In the cell contention circuit 25 of one embodiment, the same contention control processing is repeated four times in order to determine the cells output from the respective input cell buffers 10, 11, 12, 13.
The number L (numerical value 1, 2, 3, 4) attached to the top of FIG.
Indicates the order of cells to be subjected to contention control processing.

The specific contention control processing in the cell contention circuit 25 of one embodiment is as follows. First, the head of the cells stored in each of the input cell buffers 10, 11, 12, and 13 (the order L = 1 in FIG. 2) corresponds to the header arrival terminals NRD0 to NRD of the cell competition circuit 25.
3 and contention control processing is performed. In the first contention control process, the header of the head cell of the input cell buffer 10 (destination 1), the header of the head cell of the input cell buffer 11 (destination 2), and the head of the input cell buffer 12 The cell header (destination 2) is selected as the winner.

As for the ones selected as the winning combination, the notification is notified to the corresponding input cell buffers 10, 11, 12 and the destinations in the cell selectors S0 to S2 are set. In the case of the leading cell of the input cell buffer 10 (destination 1) and the leading cell of the input cell buffer 11 (destination 2), the destination is the switching network circuit 23. In the case of the head cell of the input cell buffer 12 (destination 2), since it is the same destination as that of the input cell buffer 11, the destination is set to the switching network circuit 24 so as not to collide on the switching network circuit. It The header (destination 2) of the first cell of the input cell buffer 13 is not selected in the first competition control process because the cell of the destination 2 has already been selected as the winning cell.

The second competition control process is performed only for the input cell buffers that have not been selected as the winners in the first competition control process. In the case of this embodiment, only the input cell buffer 13 is the processing target. The header (destination 2) of the cell having the competition order L = 2 accumulated in the input cell buffer 13 is output again to the header arrival terminal NRD3, and the cells of the other input cell buffers selected at the first time are included. It is judged whether or not two destinations have already been selected as the same destination. If the destinations are the same as those already selected as two destinations, no winning selection is made. Since the destination of the header of the second cell of the input cell buffer 13 is 2, and two headers have already been selected, they are not selected even in the current conflict control process.

The third competition selection process is performed on the input cell buffer in which the unsuccessful cell is not selected in the competition selection processes up to the second time. In the case of this embodiment, only the input cell buffer 13 is the processing target. The header (destination 0) of the cell with the competition order L = 3 accumulated in the input cell buffer 13 is output again to the header arrival terminal NRD3, and the cells of other input cell buffers selected up to the second time are included. It is determined whether or not two destinations have already been selected as the same destination. If the destinations are the same as those already selected as two destinations, no winning selection is made. Since the destination of the third cell header of the input cell buffer 13 is 0, and two headers have not been selected yet, it is selected as a win, and the fact is notified to the input cell buffer 13, and the above contention control is performed. Since it is the destination that first appeared in the process, the switching network circuit 23 is selected as the destination in the cell selector S3.

In principle, the contention control process is repeated four times by shifting the contention order in sequence, but if the cells to be output from all the input cell buffers 10, 11, 12, 13 are determined before that time, that time is reached. Then, the competition control process in the cell competition circuit 25 ends.

When the contention control processing for one cell cycle in the cell contention circuit 25 is completed, each input cell buffer 10,
The cells 11, 12, and 13 output the cells selected as the winning combination to the cell selectors S0 to S3, and the cell selectors S0 to S3.
In step S3, the received cell is sent to each switching network circuit 23, 24 based on the destination set by the cell contention circuit 25.

In each of the switching network circuits 23 and 24, the received cell is subjected to a predetermined routing process (a known method may be used) for the output cell buffer 15 of an intended destination of each cell.
Output to 16, 17, and 18.

The input cell buffers 10, 11, 12, and 13 that have sent cells to the cell selectors S0 to S3 have a vacancy in the position of the cell that has been sent out. lose. Then, the cells newly input to the input cell buffers 10, 11, 12, and 13 from the incoming lines ip0 to ip3 are added to the end of the accumulated cell string in each of the input cell buffers.

FIG. 3 shows the process of filling empty positions after cell transmission and the storage state of cells in each of the input cell buffers 10, 11, 12, and 13 after receiving a new cell as described above. It is shown.

In this way, when the empty state is restored, the headers of the cells having the competition order L = 1 are sent to the corresponding header arrival terminals NRD0 to NRD3 of the cell competition circuit 25 again for the next cell cycle. Sent out.

Further, the four output cell buffers 15, 16, 17, provided for each of the outgoing lines op0 to op3 described above,
As shown in FIG. 4, each of the 18 has a multiplex output circuit 27 which has two cell input sections A and B and multiplexes and outputs the cells input to these cell input sections A and B. When,
A two-input one-output type cell buffer circuit having a FiFo memory 28 which holds the output of the multiplex output circuit 27 and outputs it to the corresponding output line in the order of input, and includes the two switching network circuits 23, The cells of the same destination outputted from 24 are multiplexed and outputted to the outgoing line.

The multiplex output circuit 27 is for ensuring the order of the cells, and the cells input to the cell input sections A and B are alternated in the order of A side and B side during one cell cycle period. Multiplex. As shown in FIG. 5, the column of cells multiplexed by the multiplexing output circuit 27 is written in the FiFo memory 28 except for the empty, and is read out from the FiFo memory 28 to the output line in the order of input. In addition, F of this one embodiment
In this embodiment, the iFo memory 28 has a capacity capable of holding data of tens to hundreds of cells.

In the ATM cell exchange switch of the above embodiment, two exchange network circuits are provided as the exchange network circuits for transmitting the cells output from the input cell buffers 10 to 13 to the intended destination of each cell by a predetermined routing process. Two
Since the cells of the same destination are processed by different switching network circuits by equipping the cells 3 and 24, the cells of the cell competition circuit 25 are discarded in three or more cells of the same destination. In this case, the number of cells discarded due to the overlapping of destinations in the cell competition circuit 25 can be significantly reduced.

Accordingly, the substantial throughput of cells from the input cell buffers 10 to 13 to the switching network circuits 23 and 24 is improved, and the ATM cell switching switch as a whole has a cell discard rate set to a constant value on the incoming line. In consideration of the line utilization rate of, the line utilization rate of the incoming line can be significantly improved as compared with the conventional case where only a single switching network circuit is required.

According to a simulation actually conducted by the inventors of the present invention, when the input cell buffers are divided into two groups and the contention control is individually performed as in the embodiment, the line utilization rate of the incoming line can be improved. It was confirmed that it was possible to sufficiently meet future high level communication quality requirements.

In the above embodiment, two switching network circuits are provided and up to two cells are allowed to have the same destination. However, the number of switching network circuits to be provided is three or more. The presence of cells of the same destination may be permitted as long as the number of installed switching network circuits is within the number, and the number of switching network circuits installed is not limited to that of the embodiment.

In the embodiment, the number N of inputs is 4 and the switch size in the switching network circuit is 4 × 4. However, the present invention can be applied to any number of inputs. Needless to say.

[0044]

As is apparent from the above description, the ATM cell switching switch according to the present invention is a switching network circuit for sending cells output from an input cell buffer to a destination intended by each cell by a predetermined routing process. Since multiple cells are installed and different cells of the same destination are processed by different switching network circuits, discarding of cells in the cell contention circuit is more than the number of switching network circuits installed because the cells of the same destination overlap. This is limited to the case where there are many cells, and the number of cells discarded due to overlapping of destinations in the cell contention circuit can be greatly reduced.

Therefore, the actual throughput of cells from the input cell buffer to the switching network circuit is improved, and the line utilization rate of the incoming line is considered under the condition that the cell discard rate is kept at a constant value in the entire ATM cell switching switch. When compared with the conventional case where only a single switching network circuit was equipped,
It is possible to significantly improve the line utilization rate of incoming lines, and it will be possible to sufficiently meet future demands for high-level communication quality.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of a competition control process according to an embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of a competition control process according to an embodiment of the present invention.

FIG. 4 is a configuration diagram of an output cell buffer according to an embodiment of the present invention.

FIG. 5 is an operation explanatory diagram of the output cell buffer according to the embodiment of the present invention.

[Explanation of symbols]

 ip0 to ip3 Ingress line 10, 11, 12, 13 Input cell buffer 15, 16, 17, 18 Output cell buffer 23, 24 Switching network circuit 25 Cell competition circuit A, B Cell input unit 27 Multiplexing output circuit 28 FiFo memory

Claims (1)

[Claims] 1. A plurality of input cell buffers, which are provided for each incoming line accommodated in an ATM exchange and temporarily store cells input from the corresponding incoming line, and are provided for each outgoing line accommodated in the ATM exchange. Output cell buffers that control cell output to the corresponding output lines, and the cells output from each input cell buffer are output to the output cell buffer for the intended destination of each cell by a predetermined routing process. A plurality of switching network circuits, a cell selector provided for each of the input cell buffers described above, and a cell selector for selecting the switching network circuit to which the cells output from each input cell buffer are to be sent, and competition for the intended destination. Switching among the cells held in the plurality of input cell buffers so that the plurality of cells are not simultaneously output to the same switching network circuit. An ATM cell exchange switch for controlling input / output of cells in an ATM switch, comprising: a cell contention circuit for selecting cells to be output to the circuit, wherein the cell contention circuit has a plurality of input cell buffers. As the cells to be transmitted to the destination cell, the existence of cells having the same destination is suppressed within the range of the number of the installed switching network circuits, and the cells having the same destination are transmitted to different switching network circuits. The output cell buffer, which is configured to control the destination selection in the cell selector and is provided for each outgoing line, is a multi-input 1 that multiplexes and outputs cells of the same destination output by each switching network circuit. An ATM cell exchange switch characterized by using an output type cell buffer circuit.