JPH0628312A - Serial data transfer system - Google Patents

Abstract

PURPOSE:To increase the data transfer speed without reqiring any operation to the transmitted data in a data transfer system where the data are transferred between a control part consisting of a microcomputer and a peripheral device working under the control of the control part via a serial port. CONSTITUTION:A control part keeps the non-active state of a transfer control signal CNT for a period longer than the access cancel informing time T1 to inform all peripheral devices of the access cancel state. Then, the signal CNT is kept active for a prescribed access request informing time T2 so that an access request is reported. The signal CNT is set in a non-active state again with the access request. This non-active state is kept for a period shorter than the time T1 and equal to a period of duration that is set in response to the address of the peripheral device to which the data are transferred. Thus, this peripheral device, i.e., the data transfer destination is esignated. Then, the data are transferred to the designated peripheral device via a serial data line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system via a serial port between a control unit composed of a microcomputer and peripheral devices controlled by the control unit to operate.

[0002]

2. Description of the Related Art In a digital communication device or the like, a microcomputer of about 4 bits to 16 bits is used as a control unit to control the operation of a large number of peripheral devices such as PLLs and D / A converters. To do this control,
The control unit transfers control data such as setting data to the peripheral device at any time and writes a numerical value in a register in the device.
For example, a frequency division ratio is set in the PLL circuit or a reference voltage is set in the D / A converter.

Conventionally, in a data transfer method from a control unit using a microcomputer or the like to a peripheral device controlled by the control unit, the peripheral device is connected to a main bus in the apparatus in the same manner as data transfer to a memory. Connect and transfer data from the control unit (microcomputer). The main bus is composed of a plurality of bit lines of an address bus and a data bus. The address bus designates a peripheral device as a transfer destination and transfers data in bit parallel.

The control device is provided with a serial interface port to serially transfer addresses and data. There are two methods.

Due to the restrictions on the mounting structure of the device, the device in which the main bus cannot be provided between the control unit and the peripheral device, and the peripheral device in parallel while the memory device uses the main bus for DMA transfer or the like. A device that requires control (data transfer from the control unit) or the like uses the bit serial transfer method because the parallel transfer method cannot be adopted.

FIG. 7 is a diagram showing a serial data transfer system targeted by the present invention. As shown in FIG. 7, the control unit 1
The serial transfer between the device and multiple peripheral devices 2-1 to 2-N is performed by an interface that uses three types of signals: transfer clock CLK, transfer control signal CNT, and serial data signal DATA. Devices 2-1 to 2-N are control unit 1
Are connected to the three signal lines from 1 to 3 by the multi-drop method.

The transfer control signal CNT is a chip select signal or an enable signal. While the transfer control signal CNT is active, the data on the serial data line is valid, and the peripheral device activates the transfer control signal CNT. When the status is detected, the data is received by loading the serial data into the internal register at the timing of the transfer clock signal CLK.

At this time, it is necessary to transmit address data in order to specify a specific peripheral device of a data transfer destination from a plurality of peripheral devices. However, since the address data line is not provided, in the conventional technology, the address data is transmitted using the serial data line to specify the device of the transfer destination.

[0009]

FIG. 8 is a diagram showing the problems of the prior art. In the above-mentioned conventional method, as shown in FIG. 8, assuming that the interface is 1 byte (8 bits), it is necessary to transfer two types of data, an address and a transmission data, in this 8-bit serial data.
Since the specific bits in the transfer frame are assigned to the address data, the number of bits of the transmission data is reduced. Therefore, in order to transfer 8-bit data as the setting data, it is necessary to transfer the data in plural times, and there is a problem that the transfer speed decreases.

That is, ^{assuming that} there are N (= 2 ⁿ ) peripheral devices, since ⁿ bits of the transfer data of m bits per access are used for addressing, the data that can be written in one transfer is m. -N bits, and if the data to be sent to the peripheral device is p bits, p /
(M−n) times of transfer is required. If the number of types of transmission data is small, a method is conceivable in which the data is encoded by an encoder and the number of bits is shortened before transmission, so that one transfer is sufficient. There is a problem that a decoder is required and the amount of hardware increases.

The present invention has been made in view of the above problems, and an object of the present invention is to increase the data transfer rate in bit serial transfer without operating the transmission data.

[0012]

FIG. 1 is an operation timing chart of an interface signal in the serial data transfer system of the present invention, showing transition of a signal sent from a control unit to each peripheral device and its function. Is.

In order to solve the above-mentioned problems, the serial data transfer system of the present invention, as shown in FIG. 1, uses a transfer clock CLK, a transfer control signal CNT, and a serial data signal DATA from a control unit to control a plurality of peripheral devices. In the method in which one of the above is selected to transfer the serial data, the control unit notifies all peripheral devices of the access release by continuing the non-active state of the transfer control signal CNT for the access release notification time T1 or more. In the access release state, the transfer control signal CNT is made active for a predetermined access request notification time T2 to notify the access request, and the transfer control signal is set to the non-active state subsequently to the access request. It is shorter than the access cancellation notification time T1 and the address of the peripheral device of the destination to which the data is to be transferred is By designating the peripheral device of the data transfer destination by continuing the non-active state for the duration set to correspond, and then transferring the data to the designated peripheral device via the serial data line, Further, in the above description, the peripheral device as the data transfer destination is designated by sending address data through the serial data line during the non-active state of the transfer control signal CNT after the access request.

[0014]

FIG. 2 is a diagram showing the transition of the operating state of the peripheral device by the transfer control signal.

After the data transfer is completed, the peripheral device recognizes that the control unit has received the access release notification when the transfer control signal remains inactive for the access release notification time T1 or longer, and enters the non-operation state A (transition). ).
Transfer control signal CN when peripheral device is in non-operation state A
When T changes to active, the peripheral device transits to the pseudo access state B and measures the active duration. After entering the pseudo access state B, transfer control signal CN
When the active state of T continues for the predetermined access request notification time T2, the access permission state C is entered, and when the active continuation is outside the access request notification time T2, the non-operating state A is restored. In the access permission state C, the transfer control signal CN
When T is detected to be inactive for the time TA corresponding to the address of the own device, it recognizes that the own device has been designated, enters the data acquisition start state D, and continues non-active for the access release notification time T1 or longer. It returns to the non-operating state A, and remains in the access permission state C at other times.

In the data acquisition start state D, the transfer signal CNT is active and the transfer data is acquired, and the data acquisition end state E is set. In the data transfer end state E,
When the non-active state of the transfer control signal CNT continues for the access release notification time T1 or longer, the state becomes the non-operating state A. When the non-active state continues for the address corresponding period TA of the own device, it is recognized again that the own device is designated and the data acquisition starts. Return to state D ', otherwise remain in data transfer end state E.

By combining the value of the transfer control signal CNT and its time in this way, it is not necessary to allocate a bit for addressing at the time of serial data transfer from the control unit to the peripheral device. The actual data transfer amount can be increased, and the transfer speed can be improved.

[0018]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 3 is an operation timing chart of the embodiment of the first invention, and FIG.
Is a hardware configuration diagram of the peripheral device according to the method of the first invention, FIG. 5 is an operation timing diagram of the embodiment of the second invention,
FIG. 6 is a hardware configuration diagram of a peripheral device according to the method of the second invention. The same reference numerals denote the same objects throughout the drawings.

FIG. 3 shows the timing of various signals and the operation of peripheral devices in the method of designating an address by the inactive state duration of the transfer control signal. This drawing shows an example in which four peripheral devices a, b, and c connected to the control unit via the serial interface are sequentially accessed to transfer 4-bit transmission data.

In the figure, the transfer clock CLK, the transfer control signal CNT, and the serial data signal DATA are transmitted to all peripheral devices which are multi-drop connected to the signal line from the control section.

The fifth line in the figure shows the accessible state in all peripheral devices, where "1" is the accessible state and "0" is the access released state. Lines 6-8 are
Each indicates the access permission state of the peripheral device having the addresses a, b, and c, where "1" is being accessed,
“0” indicates a non-access state. The access release notification time T1, the access request notification time T2, and the non-active state duration for addressing in the transfer control signal CNT are determined by the total number of addresses of connected peripheral devices. For example, in FIG. 3, address a, address b,
Non-active duration Ta, T that specifies address c
Assuming that b and Tc are times of 1, 2, and 3 cycles of the transfer clock CLK, respectively, and that there is no other address to be accessed, the access cancellation notification time T1 is set to 5 clock cycles. Further, in the pseudo access in which all the peripheral devices judge the access request notification from the control unit, the active continuation time T2 of the transfer control signal is set to 5 clock cycles which is the same as the active time at the time of normal data transfer. By doing so, high-speed transfer can be realized.

Next, the configuration and operation of the peripheral device accessed by the interface signal will be described with reference to FIG. In FIG. 4, 21 is an access determination unit, 22 is an address identification unit, 23 is a device function unit, and 24 is a data fetching unit.

First, the first state is a state in which the transfer control signal is in the non-active state (logic "0") for a predetermined time or more (5 clock cycles or more), and the peripheral device does not access. It is assumed that it is in a state, that is, in a state in which it is not accepted even if data is transferred.

The control unit that is going to perform data transfer uses the transfer control signal line for a predetermined clock cycle T1 (T1 = 5 cycles in the figure).
During this period, the active state (logic "1") is set. The access determination unit 21 in which the transfer clock CLK and the transfer control signal CNT are constantly input starts operation by the transfer control signal active, and the transfer control signal CNT is set with the transfer clock as a time reference.
Measure the active duration of. When the transfer control signal CNT that is active for T2 = 4 clock cycles is detected, it is recognized as an access request notification signal and the address determination unit
The access permission signal AEN is output to 22.

The control section sets the transfer control signal CNT to the non-active state for one clock cycle corresponding to the address a of the first data transfer destination. In each peripheral device, the address identification unit 22 in which the access permission signal AEN has become active enters the operating state, and the non-active duration of the transfer control signal that follows is measured based on the clock cycle. Then, in the peripheral device a, the measured non-active duration is assigned to its own device address 1
It detects that it is equal to the clock cycle, determines that the own device has been accessed, outputs the address match signal CS to the device function unit 23, and enables the data fetch function.

The control section subsequently activates the transfer control signal CNT and sends the transfer data Da to be sent bit serially via the serial data line. The data fetch unit 24 is composed of a serial input / parallel output shift register having a bit width corresponding to a data transfer block having an m-bit length (4 bits in this embodiment). When the transfer control signal CNT is active, the transfer clock timing is set. The data on the serial data line is constantly fetched while being updated bit by bit, and the parallel-converted m-bit data is constantly output to the device function unit 23. The device function unit 23 is enabled after m transfer clock cycles from the timing when the address coincidence signal CS is notified, and at that time, the m-bit parallel data output by the data acquisition unit 24 is simultaneously fetched and written in the internal register.

In the case of this embodiment in which the data transfer destination is sequentially moved to continuously transfer the data to a plurality of devices, when the data transfer to the device a is completed, the control unit will move to the next transfer destination address b. During the period Ta (2 clock cycles) corresponding to, the transfer control signal CNT is made non-active. At this time, all the peripheral devices are in the accessible state by the first access request notification and the non-active duration time is measured. Therefore, the peripheral device b determines that the address of its own device is next designated as the data transfer destination. Is recognized, an access permission signal is issued, and the next transfer data Db is fetched.

When the data transfer to the predetermined peripheral device is completed in this way, the control section makes the transfer control signal CNT non-active, and the signal on the serial data line becomes meaningless. Then, the control unit sets this non-active state to T
It continues for 1 (5 clock cycles) or more. As a result, the access determination unit 21 stops its operation, deactivates all control signals, and returns to the non-operation state.

Next, an embodiment of the second invention will be described with reference to FIGS. The second invention is a method of designating a transfer destination by address data transferred via a serial data line while the transfer control signal CNT is inactive.

In this embodiment, all devices are made accessible by the first active period duration T2 of the transfer control signal, and the address information Aa, Ab, Ac is transferred through the serial data line during the subsequent non-active period. This is different from the first embodiment in that it is performed by doing so, and other points are the same as the first embodiment.

As shown in FIG. 5, the control unit controls the transfer control signal.
CNT access request notification time T1 (= 4 clock cycles)
During this period, the active state is maintained and an access request notification is issued, and then, for example, inactive for 3 clock cycles, and 3-bit address data Aa, Ab, Ac for designating the transfer destination is transmitted to the transfer data line. On the other hand, FIG.
On the peripheral device side, when the access determination unit 21 detects the access request notification and enters the pseudo access state, the access identification signal AEN is issued to the address identification unit 22, as shown in FIG.
The serial data line is input to the address identification unit 22 ', and subsequently, the 3-bit address data transferred in bit serial on the serial data line is taken in, and the address code preset in the own device is taken. If it is equal to, it determines that its own address is designated as the destination, issues the data capture signal CS, and writes the transfer data captured by the data capture unit 24 in the next transfer control signal active period to the device function unit 23.

In the above embodiment, an example in which data transfer is performed by designating one of a plurality of peripheral devices has been described, but it is composed of one peripheral device having a plurality of data registers and a control unit. In the system described above, it is also applicable when data is transferred by designating a specific data register. In this case, the address identification unit identifies the address of the register based on the address designation information, and controls the serial data captured by the data capture unit to be written to the designated address.

Any of the peripheral device access detection functions can be realized by a simple logic circuit.

[0034]

As described above, according to the present invention, by combining the value of the transfer control signal CNT and the duration thereof, the bit for addressing is specified during serial data transfer from the control unit to the peripheral device. Since there is no need to allocate, the amount of actual data transferred per access can be increased, and the transfer speed can be improved.

[Brief description of drawings]

FIG. 1 is an operation timing chart of an interface signal in the serial data transfer system of the present invention.

FIG. 2 is a diagram showing a transition of operating states of peripheral devices by a transfer control signal.

FIG. 3 is an operation timing chart of the embodiment of the first invention.

FIG. 4 is a hardware configuration diagram of a peripheral device according to the method of the first invention.

FIG. 5 is an operation timing chart of the embodiment of the second invention.

FIG. 6 is a hardware configuration diagram of a peripheral device according to the method of the second invention.

FIG. 7 is a diagram showing a serial data transfer system targeted by the present invention.

FIG. 8 is a diagram showing problems of the conventional technology.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Control part (microcomputer) 2-1 to 2-n ... Peripheral device, 21 ... Access determination part, 22 ... Address identification part,
23 ... Device function section, 24 ... Data acquisition section

Claims (2)

[Claims] 1. A transfer clock (CLK), a transfer control signal (CNT) and a serial data signal (DATA) from a control unit
In the method of selecting one of a plurality of peripheral devices and transferring serial data, the control unit keeps all peripheral devices in the inactive state of the transfer control signal (CNT) for at least the access release notification time T1. The access request is notified by notifying that it is in the non-access state, and after the non-access state, the transfer control signal (CNT) is activated for the access request notification time T2 to notify the access request, and the transfer control signal is continuously issued after the access request. Peripheral device of the data transfer destination by making CNT non-active state and continuing the non-active state for a time shorter than the access cancellation notification time T1 and set for the address correspondence of the peripheral device of the destination to which the data is to be transferred. And then to the specified peripheral device via the serial data line. Serial data transfer method is characterized in that so as to transfer the data. 2. The serial data transfer method according to claim 1, wherein the peripheral device of the data transfer destination is designated, and the address data is transmitted through the serial data line during the non-active period of the transfer control signal CNT after the access request. A serial data transfer method characterized in that it is performed by doing so.